M1651T ALi Super Tualatin Northbridge AGP 4X, PCI and SDR/DDR Memory Controller Product Brief INTRODUCTION With AGP 1x/2x/4x support, M1651T prepares M1651T is ALi's new generation of PCI Northbridge system designers with enough head room to interface with different graphics solutions to fulfill chip supporting the latest Slot-1, Socket-370 TM TM TM Celeron , Pentium II , Pentium III , and Tualatin various market requirements. ALi also manufactures Processors. It interfaces with the 100/133 front side a series of feature-rich, highly integrated southbridge bus (FSB). It is a single chip solution which provides devices (M1543C, M1535(D), M1535(D)+) which seamlessly work with high performace memory interface for both M1651T as a complete, flexible and cost-effective 66/100/133 SDR and 133/200/266 DDR. The solution for notebook designers. M1651T also feasible PC-266 DDR enables 2.1 GB/s peak incorporate ALi's proven power management bandwidth between the system memory and Northbridge to boost system performance to the next support which is particularly crucial to mobile applications level. Processor Support n n n n n n n TM TM TM Supports the Celeron , Pentium II , Pentium III , and Tualatin processors. Host bus frequency can be either 100,133MHz. 64-bit data bus and 32-bit addressing Optimum buffering architecture design for CPU to memory, AGP and PCI read/write Flexible configured to support back to back read transfer in 1QW or 2QW Supports back to back write transfer Optimized processor command scheduling and reordering Supports synchronous / asynchronous clock mode between processor and memory interface with optimized latency Memory Support n Supports SDRAM / DDR w/ 66, 100, 133MHz n Supports symmetrical and asymmetrical SDRAM / DDR addressing n Supports 4, 16, 64, 128, 256, 512Mbit SDRAM / DDR n Maximum memory size : 3GB n Supports 6 memory rows with per byte access on each row n Supports memory shadowing n x-1-1-1-1-1-1-1 back-to-back page hit n CAS before RAS and self refresh for SDRAM n Pipelined SDRAM / DDR cycle control with hidden pre-charge n Dynamic switching CKE algorithm n Supports LVTTL / SSTL2 signal level Accelerated Graphics Port (AGP) Interface n Supports AGP specification V2.0 n Supports up to 128 entries table look aside buffer for Graphic Address Remapping Table (GART) n AGP 66MHz protocol n AGP 1X/2X/4X sideband function n 28 entries Request queue n 64 QWORDs Read buffer n 32 QWORDs Write buffer PCI Bus Support n Supports synchronous / asynchronous clock mode between the processor bus and the PCI bus n 32-bit Address / Data PCI bus using PCI bus driver technology n Supports up to 6 PCI masters excluding the M1651T and PCI-to-ISA bridge n Parity protection on all PCI bus signals n Fully supports PCI Configuration Space Enable (CSE) protocol n Fully compliant with PCI Rev. 2.2 n Supports delayed transaction n Dynamic memory prefetch algorithm and programmable post write flush algorithm n Data Collection/Write assembly of line bursts n Supports concurrent PCI bus burst transfer at zero wait-states n 133 MB/sec data streaming for PCI bus to SDRAM / DDR access with minimum latency Power Management n Supports ACPI 1.0b and Legacy green n Supports PCI Mobile CLKRUN# n Supports AGP Mobile BUSY# / STOP# n Internally dynamic clock stop Packaging 528 balls 35x35mm BGA package n Homepage : www.ali.com.tw Ver 0.10 April 12, 2001 Acer Labs: 11F, 45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Page 1 M1651T Intel P6 Standalone Super Northbridge AGP 4X, PCI and SDR/DDR Memory Controller M1651T PC-266 SDRAM Architecture Slot1/ Socket-370 100/133MHz FSB Graphic Accelerator AGP4X 32 bits M1651T PCI PC-266 64 bits PC-266 DDR 32 bits 33 MHz South Bridge M1651T PC-133 SDRAM Architecture Slot1/ Socket-370 100/133MHz FSB Graphic Accelerator AGP4X 32 bits M1651T PCI PC-133 64 bits PC-133 SDR 32 bits 33 MHz South Bridge Homepage : www.ali.com.tw Ver 0.10 April 12, 2001 Acer Labs: 11F, 45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030Page 2