A417308 Series 128K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Document Title 128K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Revision History Rev. No. History Issue Date Remark 0.0 Initial issue September 01, 1997 Preliminary 0.1 Modify 26/24-pin SOJ package outline drawing and June 17, 1998 Dimensions 1.0 Add 28-pin TSOP type I package July 27, 1998 1.1 Final spec release September 8, 1998 (September, 1998, Version 1.1) Final AMIC Technology, Inc. A417308 Series 128K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Features n Organization: 131,072 words X 8 bits n High speed - 35/40/45 ns RAS access time - 18/20/22 ns column address access time - 12 ns CAS access time n Low power consumption - Operating: 160mA - Standby: 3 mA (TTL) n 256 refresh cycles, 8 ms refresh interval n Read-modify-write, RAS -only, CAS -before- RAS , Hidden refresh capability n TTL-compatible, three-state I/O n JEDEC standard packages - 300mil, 26/24-pin SOJ - 28-pin TSOP type I n Single 5V power supply/built-in VBB generator Pin Configuration n SOJ n TSOP (Type I) 26 VSS 2 25 I/O8 I/O2 3 24 I/O7 I/O3 4 23 I/O6 22 I/O5 21 CAS 19 OE 5 6 RAS 8 A0 9 18 A8(column Add. only) A1 10 17 A7 A2 11 16 A6 A3 12 15 A5 VCC 13 14 A4 (September, 1998, Version 1.1) 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A417308V ~ ~ I/O4 WE CAS I/O5 I/O6 I/O7 I/O8 VSS VSS NC I/O1 I/O2 I/O3 I/O4 NC WE ~ ~ 1 I/O1 A417308S VSS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 OE A8 A7 A6 A5 A4 NC VCC NC A3 A2 A1 A0 RAS AMIC Technology, Inc. A417308 Pin Descriptions Symbol Description A0 - A8 Address Inputs RAS Row Address Strobe I/O1 - I/O8 Data Input/Output OE Output Enable CAS Column Address Strobe WE Write Enable VCC Power (+5V 10%) VSS Ground Selection Guide Symbol Description -35 -40 -45 Unit tRAC Maximum RAS Access Time 35 40 45 ns tAA Maximum Column Address Access Time 18 20 22 ns tCAC Maximum CAS Access Time 12 12 12 ns tOEA Maximum Output Enable ( OE ) Access Time 12 12 12 ns tRC Minimum Read or Write Cycle Time 70 75 80 ns tPC Minimum Fast Page Mode Cycle Time 20 22 25 ns ICC1 Maximum Operating Current 160 150 140 mA ICC6 Maximum CMOS Standby Current 2.0 2.0 2.0 mA Functional Description The A417308 is a high performance CMOS Dynamic Random Access Memory organized as 131,072 words X 8 bits. The A417308 is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. address strobe ( CAS ) which acts as an output enable independent of RAS . Very fast CAS to output access time eases system design. All inputs are TTL compatible. Fast Page Mode operation allows random access up to 512 X 8 bits within a page, with cycle time as short as 20 ns. The A417308 features a high speed page mode operation in which high speed read, write and read-write are performed on any of the 512 X 8 bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease the system level timing constraints associated with multiplexed addressing. Output is tri-stated by a column (September, 1998, Version 1.1) The A417308 is best suited for graphics, digital signal processing and high performance peripherals. The A417308 is available in JEDEC standard 26/24-pin plastic SOJ packages and TSOP 28L type I plastic packages. 2 AMIC Technology, Inc. A417308 REFRESH CONTROLLER Block Diagram VCC VSS I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 DATA I/O BUFFER Y0 - Y8 COLUMN DECODER SENSE AMP 512 X 8 A2 RAS CLOCK GENERATOR A3 A4 A5 A6 CAS A7 A8 CAS CLOCK GENERATOR WE WE CLOCK GENERATOR OE OE CLOCK GENERATOR ADDRESS BUFFERS A1 RAS X0 - X7 ROW DECODER A0 256 256 X 512 X 8 ARRAY (1,048,576) SUBSTRATE BIAS GENERATOR Recommended Operating Conditions (Ta = 0C to +70C) Symbol VCC Description Supply Voltage VSS VIH Input Voltage VIL (September, 1998, Version 1.1) Min. Typ. Max. Unit 4.5 5.0 5.5 V 0.0 0.0 0.0 V 2.4 - VCC + 1 V -1.0 - 0.8 V 3 AMIC Technology, Inc. A417308 Absolute Maximum Ratings* *Comments Input Voltage (Vin) . . . . . . . . . . . . . . . . . -1.0V to +7.0V Output Voltage (Vout) . . . . . . . . . . . . . . -1.0V to +7.0V Power Supply Voltage (VCC) . . . . . . . . . -1.0V to +7.0V Operating Temperature (TOPR) . . . . . . . . . 0C to +70C Storage Temperature (TSTG) . . . . . . . . -55C to +150C Soldering Temperature X Time (TSOLDER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260C X 10sec Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . .1W Short Circuit Output Current (Iout) . . . . . . . . . . . . 50Ma Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . 200mA Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (VCC = 5V 10%, VSS = 0V, Ta = 0C to +70C) Symbol Parameter -35 -40 -45 Unit Min. Max. Min. Max. Min. Max. Test Conditions Notes IIL Input Leakage Current -10 +10 -10 +10 -10 +10 A 0V Vin +5.5V Pins not under Test = 0V IOL Output Leakage Current -10 +10 -10 +10 -10 +10 A DOUT disabled, 0V Vout +5.5V ICC1 Operating Power Supply Current - 160 - 150 - 140 mA RAS , CAS , Address cycling; tRC = min. ICC2 TTL Standby Power Supply Current - 3.0 - 3.0 - 3.0 mA RAS = CAS = VIH ICC3 Average Power Supply Current, RAS Refresh Mode - 160 - 140 - 140 mA RAS cycling, CAS = VIH, tRC = min. 1 ICC4 Fast Page Mode Average Power Supply Current - 160 - 150 - 140 mA RAS = VIL, CAS Address cycling; tPC = min. 1, 2 ICC5 CAS -before- RAS Refresh Power Supply Current - 160 - 150 - 140 mA RAS , CAS cycling; tRC = min. ICC6 CMOS Standby Power Supply Current - 2.0 - 2.0 - 2.0 mA RAS = CAS = VCC - 0.2V VOH Output Voltage 2.4 - 2.4 - 2.4 - V IOUT = -5.0mA - 0.4 - 0.4 - 0.4 V IOUT = 4.2mA VOL (September, 1998, Version 1.1) 4 1, 2 1 AMIC Technology, Inc. A417308 AC Characteristics (VCC = 5V 10%, VSS = 0V, Ta = 0C to +70C) # JEDEC Symbol Std Symbol -35 -40 -45 Parameter Unit Min. Max. Min. Max. Min. Max. Notes 1 tRL2RL2 tRC Random Read or Write Cycle Time 70 - 75 - 80 - ns 2 tRH2RL2 tRP RAS Precharge Time 25 - 25 - 25 - ns 3 tRL1RH1 tRAS RAS Pulse Width 35 75K 40 75K 45 75K ns 4 tCL1CH1 tCAS CAS Pulse Width 12 - 12 - 12 - ns 5 tRL1CL1 tRCD RAS to CAS Delay Time 15 23 16 30 17 33 ns 6 6 tRL1AV tRAD RAS to Column Address Delay Time 10 17 11 22 12 23 ns 7 7 tCL1RH1 tRSH(R) CAS to RAS Hold Time (Read) 12 - 12 - 12 - ns 8 tRL1CH1 tCSH RAS to CAS Hold Time 35 - 40 - 45 - ns 9 tCH2RL2 tCRP CAS to RAS Precharge Time 5 - 5 - 5 - ns 10 tAVRL2 tASR Row Address Setup Time 0 - 0 - 0 - ns 11 tRL1AX tRAH Row Address Hold Time 5 - 6 - 7 - ns tT tT Transition Time (Rise and Fall) 3 50 3 50 3 50 ns 4, 5 tRVRV tREF Refresh Period - 8 - 8 - 8 ns 3 tCL1QX tCLZ CAS to Output in Low Z 0 - 0 - 0 - ns 8 12 (September, 1998, Version 1.1) 5 AMIC Technology, Inc. A417308 Read Cycle (VCC = 5V 10%, VSS = 0V, Ta = 0C to +70C) # JEDEC Symbol Std Symbol Parameter -35 -40 -45 Min. Max. Min. Max. Min. Max. Unit Notes 13 tRL1QV tRAC Access Time from RAS - 35 - 40 - 45 ns 6 14 tCL1QV tCAC Access Time from CAS - 12 - 12 - 12 ns 6, 13 15 tAVQV tAA Access Time from Address - 18 - 20 - 22 ns 7, 13 16 tRL1AZ tAR(R) Column Add Hold from RAS 28 - 30 - 35 - ns 17 tWH2CL2 tRCS Read Command Setup Time 0 - 0 - 0 - ns 18 tCH2WX tRCH Read Command Hold Time to CAS 0 - 0 - 0 - ns 9 19 tRH2WX tRRH Read Command Hold Time to RAS 0 - 0 - 0 - ns 9 20 tAVRH1 tRAL Column Address to RAS Lead Time 18 - 20 - 22 - ns 21 tCH2CL2 tCRP CAS Precharge Time 5 - 5 - 5 - ns 22 tRH2OL1 tODS Output Disable Setup Time 0 - 0 - 0 - ns 23 tCH2QZ tOFF Output Buffer Turn-Off Time 0 7 0 8 0 9 ns (September, 1998, Version 1.1) 6 8, 10 AMIC Technology, Inc. A417308 Write Cycle (VCC = 5V 10%, VSS = 0V, Ta = 0C to +70C) # JEDEC Symbol Std Symbol -35 -40 -45 Parameter Unit Min. Max. Min. Max. Min. Max. Notes 24 tAVWL2 tASC Column Address Setup Time 0 - 0 - 0 - ns 25 t1CL1AX tCAH Column Address Hold Time 5 - 6 - 7 - ns 26 tRL1AX tAWR Column Address Hold Time to RAS 28 - 30 - 35 - ns 27 tWL1CL2 tWCS Write Command Setup Time 0 - 0 - 0 - ns 11 28 tCH2WH1 tWCH Write Command Hold Time 5 - 6 - 6 - ns 11 29 tRL1WH1 tWCR Write Command Hold Time to RAS 28 - 30 - 35 - ns 30 tWL1WH1 tWP Write Command Pulse Width 5 - 6 - 6 - ns 31 tWL1RH1 tRWL Write Command to RAS Lead Time 12 - 12 - 12 - ns 32 tWL1CH1 tCWL Write Command to CAS Lead Time 12 - 12 - 12 - ns 33 tDVWL2 tDS Data-in setup Time 0 - 0 - 0 - ns 12 34 tWL1DX tCL1DX tDH Data-in Hold Time 5 - 6 - 6 - ns 12 35 tRL1DX tDHR Data-in Hold Time to RAS 28 - 33 - 35 - ns Read-Modify-Write Cycle (VCC = 5V 10%, VSS = 0V, Ta = 0C to +70C) # JEDEC Symbol Std Symbol -35 -40 -45 Parameter Unit Min. Max. Min. Max. Min. Max. Notes 36 tRL2RL2 tRWC Read-Modify-Write Cycle Time 115 - 120 - 130 - ns 37 tRL1WL2 tRWD RAS to WE Delay Time 57 - 63 - 69 - ns 11 38 tCL1WL2 tCWD CAS to WE Delay Time 29 - 30 - 31 - ns 11 39 tAVWL2 tAWD Column Address to WE Delay Time 35 - 38 - 41 - ns 11 40 tCL1RH1 tRSH(W) CAS to RAS Hold Time (Write) 12 - 12 - 12 - ns 41 tCL1CH1 tCAS(W) CAS Pulse Width (Write) 12 - 12 - 12 - ns (September, 1998, Version 1.1) 7 AMIC Technology, Inc. A417308 Fast Page Mode Cycle (VCC = 5V 10%, VSS = 0V, Ta = 0C to +70C) # JEDEC Symbol Std Symbol -35 -40 -45 Parameter Min. Max. Min. Max. Min. Max. Unit Notes 42 tAVAV tWL2WL2 tPC Read-Write Cycle Time (Fast Page) 20 - 22 - 25 - ns 14 43 tCH2CQV tCAP Access Time from CAS Precharge - 21 - 23 - 25 ns 13 44 tCH2CL2 tCP CAS Precharge Time (Fast Page) 6 - 7 - 7 - ns 45 tCL2CL2 tPCM FAST PAGE Mode RMW Cycle 52 - 55 - 58 - ns 46 tCL2CH2 tCRW Page Mode CAS Pulse Width (RMW) 45 - 49 - 60 - ns 47 tRLRH1 tRASP RAS Pulse Width 35 125K 40 125K 45 125K ns Refresh Cycle (VCC = 5V 10%, VSS = 0V, Ta = 0C to +70C) # JEDEC Symbol Std Symbol -35 -40 -45 Parameter Min. Max. Min. Max. Min. Max. Unit Notes 48 tCL1RL2 tCSR CAS Setup Time ( CAS before- RAS ) 5 - 5 - 5 - ns 3 49 tRL1CH1 tCHR CAS Hold Time ( CAS before- RAS ) 10 - 10 - 10 - ns 3 50 tRH2CL2 tRPC RAS Precharge to CAS Hold Time 5 - 5 - 5 - ns 51 tCL1CH1 (refresh) tCPT CAS Precharge Time ( CAS -before- RAS Counter Test) 20 - 20 - 20 - ns (September, 1998, Version 1.1) 8 AMIC Technology, Inc. A417308 Output Cycle (VCC = 5V 10%, VSS = 0V, Ta = 0C to +70C) # JEDEC Symbol Std Symbol Parameter -35 -40 -45 Unit Min. Max. Min. Max. Min. Max. 52 tOL1RH1 tROH RAS Hold Time Reference to OE 5 - 5 - 5 - ns 53 tOL1QV tOEA OE Access Time - 12 - 12 - 12 ns 54 tOH2QX tOED OE to Data Delay 7 - 8 - 9 - ns 55 tOH2QZ tOEZ Output Buffer Turn-off Delay from OE 0 7 0 8 0 9 ns 56 tWL1OL2 tOEH OE Command Hold Time 0 - 0 - 0 - ns Notes 8 Notes: 1. ICC1, ICC3, ICC4, and ICC6 depend on cycle rate. 2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 3. An initial pause of 200s is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before- RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8ms). 4. AC Characteristics assume tT = 5ns. All AC parameters are measured with a load equivalent to two TTL loads and 100pF, VIL (min.) GND and VIH (max.) VCC. 5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. 6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC. 7. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA. 8. Assumes three state test load (5pF and a 380 Thevenin equivalent). 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. 11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (min.) and tWCH tWCH (min.), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD tRWD (min.) , tCWD tCWD (min.) and tAWD tAWD (min.), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles. 13. Access time is determined by the longest of tAA or tCAC or tCAP. 14. tASC tCP to achieve tPC (min.) and tCAP (max.) values. 15. These parameters are sampled and not 100% tested. Key to Switching Waveforms Don t Care Input (September, 1998, Version 1.1) Rising Input Falling Input 9 Undefined Output AMIC Technology, Inc. A417308 Timing Waveform of Read Cycle tRC(1) tRAS(3) tRSH(7) tRCD(5) tRP(2) RAS tCSH(8) tCAH(25) tASC(24) tRCS(17) tCRP(9) CAS tCAS(4) tAR(16) tRAD(6) tASR(10) Address tRAH(11) tRAL(20) Row Address Col Address tRRH(19) tRCH(18) WE tROH(52) OE tOEA(53) tOEZ(55) tRAC(13) tAA(15) tCAC(14) tCLZ(12) tOFF(23) I/O Data Out Timing Waveform of Early Write Cycle tRC(1) tRAS(3) tRP(2) RAS tCSH(8) tRSH(40) tCRP(9) tRCD(5) tCAS(41) CAS tAWR(26) tRAD(6) tASR(10) Address tRAH(11) tRAL(20) tASC(24) Row Address tCAH(25) Col Address tWCR(29) tCWL(32) tRWL(31) tWP(30) tWCH(28) tWCS(27) WE OE tDHR(35) tDS(33) I/O (September, 1998, Version 1.1) tDH(34) Data In 10 AMIC Technology, Inc. A417308 Timing Waveform of Write Cycle tRC(1) tRAS(3) tRP(2) RAS tCSH(8) tRSH(40) tCRP(9) tRCD(5) tCAS(41) CAS tAWR(26) tRAD(6) tASR(10) Address tRAH(11) tRAL(20) tASC(24) Row Address tCAH(25) Col Address tWCR(29) tCWL(32) tRWL(31) tWP(30) WE tOEH(56) OE tDHR(35) tOED(54) tDS(33) tDH(34) I/O Data In Timing Waveform of Read-Write Cycle tRWC(36) tRAS(3) tRP(2) RAS tCSH(8) tCRP(9) tRSH(7) tRCD(5) tCAS(41) CAS tAR(16) tASR(10) Address tRAD(6) tRAH(11) tRAL(20) tASC(24) Row Address tCAH(25) Col Address tRWD(37) tRWL(31) tAWD(39) tRCS(17) tCWL(32) tCWD(38) tWP(30) WE tOEZ(55) tOEA(53) tOED(54) OE tRAC(13) tDS(33) tAA(15) tCAC(14) tDH(34) tCLZ(12) I/O (September, 1998, Version 1.1) Data Out 11 Data In AMIC Technology, Inc. A417308 Timing Waveform of Fast Page Mode Read Cycle tRASP(47) tRP(2) RAS tCSH(8) tCRP(11) tRSH(7) tRCD(3) tCAS(4) tCP(44) tPC(42) CAS tAR(16) tRAL(20) tRAD(6) tRAH(11) tASR(10) Address tASC(24) Row Col Address tCAH(25) Col Address Col Address tRCH(18) tRCS(17) tRCS(17) tRCH(18) tRRH(19) WE tOEA(53) tOEA(53) OE tRAC(13) tCAC(14) tOFF(23) tCAP(43) tAA(15) tCLZ(12) tOEZ(55) I/O Data Out Data Out Data Out Timing Waveform of Fast Page Mode Early Write Cycle tRASP(47) tRAH(11) tRWL(31) RAS tASC(24) tCSH(8) tCRP(9) tPC(42) tRSH(7) tRCD(5) tCAS(41) tWCS(27) tCP(44) tCAH(25) CAS tRAL(20) tAR(16) tASR(10) Address tRAD(6) Row address Col Address Col Address Col Address tCWL(32) tWP(30) tOEH(56) tWCH(28) WE OE tDHR(35) tDS(33) I/O (September, 1998, Version 1.1) tDH(34) tOED(54) Data In Data In 12 Datat In AMIC Technology, Inc. A417308 Timing Waveform of Fast Page Mode Read-Write Cycle tRASP (47) tRP (2) RAS tPCM(45) tCSH(8) tRCD(5) tCAS(41) tCRP(9) tCP(44) CAS tRAD(6) tCAH(25) tRAH (11) tASR(10) Address Row Ad tRAL(20) tCAH(25) tCAH(25) Col Ad Col Ad Col Address tRWL(31) tRWD(37) tRCS(17) tCWD(38) tCWD(38) tCWD(38) tAWD(39) tAWD (39) tCWL(32) tWP (30) WE tOEZ (55) tOEA (53) tOED(54) tOEA (53) OE tAA (15) tDH(34) tRAC(13) tCLZ(12) tCAC(14) tCLZ(12) tDS(33) tCAC(14) I/O tCAP (43) tDS(33) Data In tCLZ(12) Data In Data Out Data Out Data In Data Out Timing Waveform of RAS Only Refresh Cycle ( WE = OE = VIH or VIL) tRC(1) tRAS(3) tRP(2) RAS tCRP(9) CAS tARS(10) Address tRAH(11) Row Address Timing Waveform of CAS -before- RAS Refresh Cycle ( WE = A8 = VIH or VIL) tRC (1) tRP (2) tRAS (3) RAS tRPC (50) tCRP (21) tCSR (48) tCHR (49) CAS tOFF (23) I/O (September, 1998, Version 1.1) 13 AMIC Technology, Inc. A417308 Timing Waveform of Hidden Refresh Cycle (Read) tRC(1) tRC(1) tRAS(3) tRP(2) tRAS(3) tRP(2) RAS tCHR(49) tCPR(9) tRCD(5) tRSH(7) tCRP(9) CAS tAR(16) tRAD(6) tRAH(11) tASR(10) Address tASC(24) Row Col Address tRCS(17) tRRH(19) WE OE tRAC(13) tOFF(23) tAA(15) tCAC(14) tOEZ(55) tCLZ(12) Data Out I/O Timing Waveform of Hidden Refresh Cycle (Write) tRC(1) tRAS(3) tRP(2) RAS tCRP(9) tRCD(5) tRSH(40) CAS tAR(16) tRAD(6) tRAH(11) Address tRAL(20) tCAH(25) tASC(24) tASR(10) Row Address Col Address tRWL(31) tWCR(29) tWP(30) tWCS(27) tWCH(28) WE tDS(33) tDH(34) tDHR(35) I/O Data In OE (September, 1998, Version 1.1) 14 AMIC Technology, Inc. A417308 Timing Waveform of CAS -before- RAS Refresh Counter Test Cycle tRAS (3) tRP (2) RAS tRSH (7) tCSR (48) tCHR (49) tCPT (51) tCAS (4) CAS tRAL (20) tCAH (25) Address Col Address tAA (15) tCAC (14) tCLZ (12) tOFF (23) I/O Data Out tRRH (19) Read Cycle tRCS (17) tRCH (18) WE tOEA (53) tROH (52) OE tRWL(31) tCWL(32) tWP(30) tWCS(27) tWCH(28) Write Cycle WE tDS (33) tDH (34) I/O Data In OE tWP (30) tAWD(39) tCWD(38) tRCS (17) tCWL(32) Read-Write Cycle WE tOEA(53) tOED (54) OE tAA (15) tCLZ (12) tOEZ(55) tCAC (14) I/O (September, 1998, Version 1.1) Data Out 15 tDS (33) tDH (34) Data In AMIC Technology, Inc. A417308 Capacitance15 (f = 1MHz, Ta = Room Temperature, VCC = 5V 10%) Symbol Signals Parameter Max. Unit Test Conditions 5 pF Vin = 0V CIN1 A0 - A8 CIN2 RAS , CAS , WE , OE Input Capacitance 7 pF Vin = 0V CI/O I/O1 - I/O8 I/O Capacitance 7 pF Vin = Vout = 0V Ordering Codes RAS Access Time Max. (ns) Operating Current Max. (mA) Standby Current Max. (mA) (CMOS) Package A417308S-35 35 160 2 26/24Pin SOJ A417308S-40 40 150 2 26/24Pin SOJ A417308S-45 45 140 2 26/24Pin SOJ A417308V-35 35 160 2 28Pin TSOP (I) A417308V-40 40 150 2 28Pin TSOP (I) A417308V-45 45 140 2 28Pin TSOP (I) Part No. (September, 1998, Version 1.1) 16 AMIC Technology, Inc. A417308 Package Information SOJ 26L/24L (300mil) Outline Dimensions unit: inches/mm 18 13 6 7 12 E1 19 1 E D 24 -yS b b2 A A A1 A2 C Pin 1 Identifier e Seating Plane 0.004 Symbol A E2 y Dimensions in inches Dimensions in mm Min Nom Max Min Nom Max A - - 0.140 - - 3.56 A1 0.070 0.080 0.090 1.78 2.03 2.29 A2 0.095 0.100 0.105 2.41 2.54 2.67 b 0.016 0.018 0.022 0.41 0.46 0.56 b2 0.026 0.028 0.032 0.66 0.71 0.81 C 0.008 0.010 0.014 0.20 0.25 0.36 D - 0.675 0.686 - 17.15 17.42 E 0.327 0.337 0.347 8.31 8.56 8.81 E1 0.295 0.300 0.305 7.49 7.62 7.75 E2 0.245 0.265 0.285 6.22 6.73 7.24 e 0.044 0.050 0.056 1.12 1.27 1.42 S - - 0.048 - - 1.22 0 - 10 0 - 10 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension E2 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (September, 1998, Version 1.1) 17 AMIC Technology, Inc. A417308 Package Information TSOP 28L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm D1 Detail "A" 28 A1 E c A A2 1 e 14 L 15 D D Detail "A" y S Dimensions in inches Symbol b Dimensions in mm Min Nom Max Min Nom Max A - - 0.049 - - 1.25 A1 0.002 - - 0.05 - - A2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.007 0.009 0.011 0.17 0.22 0.27 c 0.005 - 0.008 0.12 - 0.21 E 0.311 0.315 0.319 7.90 8.00 8.10 L 0.012 0.020 0.028 0.30 0.50 0.70 D 0.520 0.528 0.536 13.20 13.40 13.60 D1 0.461 0.465 0.469 11.70 11.80 11.90 e 0.022 BSC 0.55 BSC S 0.017 TYP 0.425 TYP y - - 0.004 - - 0.10 0 - 5 0 - 5 Notes: 1. The maximum value of dimension D1 includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. (September, 1998, Version 1.1) 18 AMIC Technology, Inc.