A417308 Series
128K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
(September, 1998, Version 1.1) AMIC Technology, Inc.
Document Title
128K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue September 01, 1997 Preliminary
0.1 Modify 26/24-pin SOJ package outline drawing and June 17, 1998
Dimensions
1.0 Add 28-pin TSOP type I package July 27, 1998
1.1 Final spec release September 8, 1998 Final
A417308 Series
128K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
(September, 1998, Version 1.1) 1AMIC Technology, Inc.
Features
nOrganization: 131,072 words X 8 bits
nHigh speed
-35/40/45 ns RAS access time
-18/20/22 ns column address access time
-12 ns CAS access time
nLow power consumption
-Operating: 160mA
-Standby: 3 mA (TTL)
n256 refresh cycles, 8 ms refresh interval
nRead-modify-write, RAS-only, CAS -before-RAS,
Hidden refresh capability
nTTL-compatible, three-state I/O
nJEDEC standard packages
- 300mil, 26/24-pin SOJ
- 28-pin TSOP type I
nSingle 5V power supply/built-in VBB generator
Pin Configuration
n SOJ n TSOP (Type I)
VSS
I/O
1
I/O
2
I/O
3
I/O
4
A0
A1
A2
A3
VCC A4
A5
A6
A7
A8(column Add. only)
I/O
6
I/O
7
I/O
8
VSS
A417308S
1
2
3
4
5
9
10
11
12
13 14
15
16
17
18
22
23
24
25
26
WE
RAS 8
6CAS
21
I/O
5
OE
19
A417308V
1
9
28
20
2
3
4
5
6
7
8
10
11
12
13
14
VSS
NC
27
26
25
24
23
22
21
19
18
17
16
15
I/O
6
I/O
5
I/O
2
I/O
1
A1
A0
A5
VSS
I/O
7
CAS OE
~
~~
~
I/O
8
I/O
3
I/O
4
NC
WE
A8
A7
A6
A4
NC
VCC
NC
A3
A2
RAS
A417308
(September, 1998, Version 1.1) 2AMIC Technology, Inc.
Pin Descriptions
Symbol Description
A0 - A8 Address Inputs
RAS Row Address Strobe
I/O1 - I/O8Data Input/Output
OE Output Enable
CAS Column Address Strobe
WE Write Enable
VCC Power (+5V ± 10%)
VSS Ground
Selection Guide
Symbol Description -35 -40 -45 Unit
tRAC Maximum RAS Access Time 35 40 45 ns
tAA Maximum Column Address Access Time 18 20 22 ns
tCAC Maximum CAS Access Time 12 12 12 ns
tOEA Maximum Output Enable (OE) Access Time 12 12 12 ns
tRC Minimum Read or Write Cycle Time 70 75 80 ns
tPC Minimum Fast Page Mode Cycle Time 20 22 25 ns
ICC1 Maximum Operating Current 160 150 140 mA
ICC6 Maximum CMOS Standby Current 2.0 2.0 2.0 mA
Functional Description
The A417308 is a high performance CMOS Dynamic
Random Access Memory organized as 131,072 words X
8 bits. The A417308 is fabricated with advanced CMOS
technology and designed with innovative design
techniques resulting in high speed, extremely low power
and wide operating margins at component and system
levels.
The A417308 features a high speed page mode
operation in which high speed read, write and read-write
are performed on any of the 512 X 8 bits defined by the
column address. The asynchronous column address
uses an extremely short row address capture time to
ease the system level timing constraints associated with
multiplexed addressing. Output is tri-stated by a column
address strobe ( CAS ) which acts as an output enable
independent of RAS. Very fast CAS to output access
time eases system design.
All inputs are TTL compatible. Fast Page Mode operation
allows random access up to 512 X 8 bits within a page,
with cycle time as short as 20 ns.
The A417308 is best suited for graphics, digital signal
processing and high performance peripherals.
The A417308 is available in JEDEC standard 26/24-pin
plastic SOJ packages and TSOP 28L type I plastic
packages.
A417308
(September, 1998, Version 1.1) 3AMIC Technology, Inc.
Block Diagram
RAS CLOCK
GENERATOR
DATA
I/O
BUFFER
SENSE AMP
COLUMN
DECODER
REFRESH
CONTROLLER
ADDRESS BUFFERS
WE CLOCK
GENERATOR
CAS CLOCK
GENERATOR
SUBSTRATE
BIAS
GENERATOR
256 X 512 X 8
ARRAY
(1,048,576)
ROW DECODER
RAS
CAS
A0
A8
A7
A6
A5
A4
A3
A2
A1
VSS
VCC
I/O
8
I/O
7
I/O
6
I/O
5
Y0 - Y8
512 X 8
256
X0 - X7
I/O
4
I/O
3
I/O
2
I/O
1
OE CLOCK
GENERATOR
WE
OE
Recommended Operating Conditions (Ta = 0°C to +70°C)
Symbol Description Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
VSS 0.0 0.0 0.0 V
VIH Input Voltage 2.4 -VCC + 1 V
VIL -1.0 -0.8 V
A417308
(September, 1998, Version 1.1) 4AMIC Technology, Inc.
Absolute Maximum Ratings*
Input Voltage (Vin) . . . . . . . . . . . . . . . . . -1.0V to +7.0V
Output Voltage (Vout) . . . . . . . . . . . . . . -1.0V to +7.0V
Power Supply Voltage (VCC) . . . . . . . . . -1.0V to +7.0V
Operating Temperature (TOPR) . . . . . . . . . 0°C to +70°C
Storage Temperature (TSTG) . . . . . . . . -55°C to +150°C
Soldering Temperature X Time (TSOLDER) . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260°C X 10sec
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . .1W
Short Circuit Output Current (Iout) . . . . . . . . . . . . 50Ma
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . 200mA
DC Electrical Characteristics (VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C)
Symbol Parameter -35 -40 -45 Unit Test Conditions Notes
Min. Max. Min. Max. Min. Max.
IIL Input Leakage Current -10 +10 -10 +10 -10 +10 µA 0V ≤ Vin ≤ +5.5V
Pins not under
Test = 0V
IOL Output Leakage
Current -10 +10 -10 +10 -10 +10 µA DOUT disabled,
0V ≤ Vout ≤ +5.5V
ICC1 Operating Power
Supply Current -160 -150 -140 mA RAS, CAS ,
Address cycling;
tRC = min.
1, 2
ICC2 TTL Standby Power
Supply Current -3.0 -3.0 -3.0 mA RAS = CAS = VIH
ICC3 Average Power Supply
Current, RAS Refresh
Mode
-160 -140 -140 mA RAS cycling,
CAS = VIH,
tRC = min.
1
ICC4 Fast Page Mode
Average Power Supply
Current
-160 -150 -140 mA RAS = VIL,
CAS Address
cycling;
tPC = min.
1, 2
ICC5 CAS -before-RAS
Refresh Power Supply
Current
-160 -150 -140 mA RAS, CAS cycling;
tRC = min. 1
ICC6 CMOS Standby Power
Supply Current -2.0 -2.0 -2.0 mA RAS =CAS =
VCC - 0.2V
VOH Output Voltage 2.4 -2.4 -2.4 -V IOUT = -5.0mA
VOL -0.4 -0.4 -0.4 V IOUT = 4.2mA
A417308
(September, 1998, Version 1.1) 5AMIC Technology, Inc.
AC Characteristics (VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C)
#JEDEC
Symbol Std
Symbol Parameter -35 -40 -45 Unit Notes
Min. Max. Min. Max. Min. Max.
1tRL2RL2 tRC Random Read or Write
Cycle Time 70 -75 -80 -ns
2tRH2RL2 tRP RAS Precharge Time 25 -25 -25 -ns
3tRL1RH1 tRAS RAS Pulse Width 35 75K 40 75K 45 75K ns
4tCL1CH1 tCAS CAS Pulse Width 12 -12 -12 -ns
5tRL1CL1 tRCD RAS to CAS Delay Time 15 23 16 30 17 33 ns 6
6tRL1AV tRAD RAS to Column Address
Delay Time 10 17 11 22 12 23 ns 7
7tCL1RH1 tRSH(R) CAS to RAS Hold Time
(Read) 12 -12 -12 -ns
8tRL1CH1 tCSH RAS to CAS Hold Time 35 -40 -45 -ns
9tCH2RL2 tCRP CAS to RAS Precharge
Time 5-5-5-ns
10 tAVRL2 tASR Row Address Setup Time 0-0-0-ns
11 tRL1AX tRAH Row Address Hold Time 5-6-7-ns
tTtTTransition Time (Rise and
Fall) 3 50 3 50 3 50 ns 4, 5
tRVRV tREF Refresh Period -8-8-8ns 3
12 tCL1QX tCLZ CAS to Output in Low Z 0-0-0-ns 8
A417308
(September, 1998, Version 1.1) 6AMIC Technology, Inc.
Read Cycle (VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C)
#JEDEC
Symbol Std
Symbol Parameter -35 -40 -45 Unit Notes
Min. Max. Min. Max. Min. Max.
13 tRL1QV tRAC Access Time from RAS -35 -40 -45 ns 6
14 tCL1QV tCAC Access Time from CAS -12 -12 -12 ns 6, 13
15 tAVQV tAA Access Time from Address -18 -20 -22 ns 7, 13
16 tRL1AZ tAR(R) Column Add Hold from RAS 28 -30 -35 -ns
17 tWH2CL2 tRCS Read Command Setup Time 0-0-0-ns
18 tCH2WX tRCH Read Command Hold Time
to CAS 0-0-0-ns 9
19 tRH2WX tRRH Read Command Hold Time
to RAS 0-0-0-ns 9
20 tAVRH1 tRAL Column Address to RAS
Lead Time 18 -20 -22 -ns
21 tCH2CL2 tCRP CAS Precharge Time 5-5-5-ns
22 tRH2OL1 tODS Output Disable Setup Time 0-0-0-ns
23 tCH2QZ tOFF Output Buffer Turn-Off Time 070809ns 8, 10
A417308
(September, 1998, Version 1.1) 7AMIC Technology, Inc.
Write Cycle (VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C)
#JEDEC
Symbol Std
Symbol Parameter -35 -40 -45 Unit Notes
Min. Max. Min. Max. Min. Max.
24 tAVWL2 tASC Column Address Setup Time 0-0-0-ns
25 t1CL1AX tCAH Column Address Hold Time 5-6-7-ns
26 tRL1AX tAWR Column Address Hold Time
to RAS 28 -30 -35 -ns
27 tWL1CL2 tWCS Write Command Setup Time 0-0-0-ns 11
28 tCH2WH1 tWCH Write Command Hold Time 5-6-6-ns 11
29 tRL1WH1 tWCR Write Command Hold Time
to RAS 28 -30 -35 -ns
30 tWL1WH1 tWP Write Command Pulse
Width 5-6-6-ns
31 tWL1RH1 tRWL Write Command to RAS
Lead Time 12 -12 -12 -ns
32 tWL1CH1 tCWL Write Command to CAS
Lead Time 12 -12 -12 -ns
33 tDVWL2 tDS Data-in setup Time 0-0-0-ns 12
34 tWL1DX
tCL1DX tDH Data-in Hold Time 5-6-6-ns 12
35 tRL1DX tDHR Data-in Hold Time to RAS 28 -33 -35 -ns
Read-Modify-Write Cycle (VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C)
#JEDEC
Symbol Std
Symbol Parameter -35 -40 -45 Unit Notes
Min. Max. Min. Max. Min. Max.
36 tRL2RL2 tRWC Read-Modify-Write Cycle
Time 115 -120 -130 -ns
37 tRL1WL2 tRWD RAS to WE Delay Time 57 -63 -69 -ns 11
38 tCL1WL2 tCWD CAS to WE Delay Time 29 -30 -31 -ns 11
39 tAVWL2 tAWD Column Address to WE
Delay Time 35 -38 -41 -ns 11
40 tCL1RH1 tRSH(W) CAS to RAS Hold Time
(Write) 12 -12 -12 -ns
41 tCL1CH1 tCAS(W) CAS Pulse Width (Write) 12 -12 -12 -ns
A417308
(September, 1998, Version 1.1) 8AMIC Technology, Inc.
Fast Page Mode Cycle (VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C)
#JEDEC
Symbol Std
Symbol Parameter -35 -40 -45 Unit Notes
Min. Max. Min. Max. Min. Max.
42 tAVAV
tWL2WL2 tPC Read-Write Cycle Time
(Fast Page) 20 -22 -25 -ns 14
43 tCH2CQV tCAP Access Time from CAS
Precharge -21 -23 -25 ns 13
44 tCH2CL2 tCP CAS Precharge Time
(Fast Page) 6-7-7-ns
45 tCL2CL2 tPCM FAST PAGE Mode RMW
Cycle 52 -55 -58 -ns
46 tCL2CH2 tCRW Page Mode CAS Pulse
Width (RMW) 45 -49 -60 -ns
47 tRLRH1 tRASP RAS Pulse Width 35 125K 40 125K 45 125K ns
Refresh Cycle (VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C)
#JEDEC
Symbol Std
Symbol Parameter -35 -40 -45 Unit Notes
Min. Max. Min. Max. Min. Max.
48 tCL1RL2 tCSR CAS Setup Time (CAS -
before-RAS)
5-5-5-ns 3
49 tRL1CH1 tCHR CAS Hold Time (CAS -
before-RAS)
10 -10 -10 -ns 3
50 tRH2CL2 tRPC RAS Precharge to CAS
Hold Time 5-5-5-ns
51 tCL1CH1
(refresh) tCPT CAS Precharge Time
(CAS -before-RAS Counter
Test)
20 -20 -20 -ns
A417308
(September, 1998, Version 1.1) 9AMIC Technology, Inc.
Output Cycle (VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C)
#JEDEC
Symbol Std
Symbol Parameter -35 -40 -45 Unit Notes
Min. Max. Min. Max. Min. Max.
52 tOL1RH1 tROH RAS Hold Time Reference
to OE
5-5-5-ns
53 tOL1QV tOEA OE Access Time -12 -12 -12 ns
54 tOH2QX tOED OE to Data Delay 7-8-9-ns
55 tOH2QZ tOEZ Output Buffer Turn-off Delay
from OE 070809ns 8
56 tWL1OL2 tOEH OE Command Hold Time 0-0-0-ns
Notes:
1. ICC1, ICC3, ICC4, and ICC6 depend on cycle rate.
2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
3. An initial pause of 200µs is required after power-up followed by any 8 RAS cycles before proper device operation is
achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before-RAS initialization cycles instead of 8
RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than
8ms).
4. AC Characteristics assume tT = 5ns. All AC parameters are measured with a load equivalent to two TTL loads and
100pF, VIL (min.) ≥ GND and VIH (max.) ≤ VCC.
5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured
between VIH and VIL.
6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference
point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC.
7. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA.
8. Assumes three state test load (5pF and a 380Ω Thevenin equivalent).
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output
voltage levels.
11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only. If tWCS ≥ tWCS (min.) and tWCH ≥ tWCH (min.), the cycle is an early write cycle
and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD ≥ tRWD (min.) , tCWD ≥
tCWD (min.) and tAWD ≥ tAWD (min.), the cycle is a read-write cycle and the data out will contain data read from the
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is
indeterminate.
12. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write
cycles.
13. Access time is determined by the longest of tAA or tCAC or tCAP.
14. tASC ≥ tCP to achieve tPC (min.) and tCAP (max.) values.
15. These parameters are sampled and not 100% tested.
Key to Switching Waveforms
Don′t Care Input Rising Input Falling Input Undefined Output
A417308
(September, 1998, Version 1.1) 10 AMIC Technology, Inc.
Timing Waveform of Read Cycle
Timing Waveform of Early Write Cycle
t
CLZ
(12)
t
ASR
(10) t
RAH
(11)
t
CSH
(8) t
CAH
(25)
t
CAS
(4)
t
ASC
(24)
t
RCS
(17)t
CRP
(9)
t
RC
(1)
t
RP
(2)
t
RAS
(3)
t
RSH
(7)
t
RCD
(5)
t
RCH
(18)
t
RRH
(19)
t
RAL
(20)
t
AR
(16)
t
RAD
(6)
t
ROH
(52)
t
RAC
(13)
t
AA
(15)
t
OEA
(53)
t
CAC
(14)
t
OEZ
(55)
t
OFF
(23)
Row Address Col Address
Data Out
RAS
CAS
Address
WE
OE
I/O
t
DH
(34)
t
DS
(33)
t
RC
(1)
t
RP
(2)t
RAS
(3)
t
RSH
(40)
t
CAS
(41)
t
CSH
(8)
t
RCD
(5)t
CRP
(9)
t
WCH
(28)
t
AWR
(26)
t
RAL
(20)t
RAD
(6)
t
ASR
(10) t
RAH
(11) t
ASC
(24) t
CAH
(25)
t
WCR
(29)
t
CWL
(32)
t
RWL
(31) t
WP
(30)
t
DHR
(35)
Col AddressRow Address
Data In
RAS
CAS
Address
WE
OE
I/O
t
WCS
(27)
A417308
(September, 1998, Version 1.1) 11 AMIC Technology, Inc.
Timing Waveform of Write Cycle
Timing Waveform of Read-Write Cycle
t
AR
(16)
t
RAL
(20)
Col AddressRow Address
t
RWC
(36)
t
RAS
(3) t
RP
(2)
t
RSH
(7)
t
CAS
(41)
t
CSH
(8)
t
RCD
(5)t
CRP
(9)
t
ASC
(24) t
CAH
(25)t
RAH
(11)
t
RAD
(6)
t
ASR
(10)
t
WP
(30)
t
RWD
(37)
t
AWD
(39) t
CWD
(38)t
RCS
(17) t
CWL
(32)
t
OEZ
(55)
t
RAC
(13)
t
AA
(15) t
CAC
(14) t
DS
(33)
t
CLZ
(12) t
DH
(34)
RAS
CAS
Address
WE
OE
I/O Data Out Data In
t
RWL
(31)
t
OEA
(53) t
OED
(54)
t
RC
(1)
t
RP
(2)t
RAS
(3)
t
RSH
(40)
t
CAS
(41)
t
CSH
(8)
t
RCD
(5)t
CRP
(9)
t
AWR
(26)
t
RAL
(20)t
RAD
(6)
t
ASR
(10) t
RAH
(11) t
ASC
(24) t
CAH
(25)
t
WCR
(29)
Col AddressRow Address
RAS
CAS
Address
t
WP
(30)
t
RWL
(31)
t
CWL
(32)
t
OEH
(56)
t
DHR
(35)
t
DS
(33) t
DH
(34)
WE
OE
I/O Data In
t
OED
(54)
A417308
(September, 1998, Version 1.1) 12 AMIC Technology, Inc.
Timing Waveform of Fast Page Mode Read Cycle
t
ASR
(10)
Address
I/O
t
RASP
(47) t
RP
(2)
t
RCD
(3)
Row Col Address Col Address Col Address
t
CAS
(4)
t
CSH
(8)
t
CP
(44) t
PC
(42)
t
RSH
(7)
t
CRP
(11)
t
RAH
(11)
t
RAD
(6) t
AR
(16)
t
ASC
(24) t
CAH
(25)
t
RAL
(20)
t
RCS
(17) t
RCH
(18) t
RCS
(17)
t
RCH
(18)
t
RRH
(19)
t
OEA
(53) t
OEA
(53)
Data Out Data OutData Out
t
CAP
(43)
t
RAC
(13)
t
AA
(15)
t
CAC
(14) t
OFF
(23)
t
OEZ
(55)
RAS
CAS
WE
OE
t
CLZ
(12)
Timing Waveform of Fast Page Mode Early Write Cycle
t
PC
(42)
Row address Col Address Col Address Col Address
t
RAH
(11) t
RASP
(47) t
RWL
(31)
t
RSH
(7)
t
RAL
(20)
t
CP
(44)t
WCS
(27)t
CAS
(41)
t
CSH
(8)
t
RCD
(5)t
CRP
(9)
t
ASR
(10) t
RAD
(6) t
AR
(16)
t
CWL
(32)
t
WP
(30)
t
WCH
(28)
t
OED
(54)t
DH
(34)t
DS
(33)
t
DHR
(35)
RAS
CAS
Address
WE
OE
I/O Data In Data In Datat In
t
ASC
(24)
t
CAH
(25)
t
OEH
(56)
A417308
(September, 1998, Version 1.1) 13 AMIC Technology, Inc.
Timing Waveform of Fast Page Mode Read-Write Cycle
t
DS
(33)
t
RWL
(31)
Row Ad Col AdCol Ad Col Address
Data In Data In Data In
Data Out Data OutData Out
RAS
CAS
Address
WE
OE
I/O
t
RASP
(47) t
RP
(2)
t
RCD
(5) t
CAS
(41)
t
CSH
(8) t
PCM
(45)
t
CP
(44) t
CRP
(9)
t
RAD
(6)
t
RAH
(11) t
RAL
(20)
t
CAH
(25)t
CAH
(25)
t
CAH
(25)
t
AWD
(39) t
AWD
(39)
t
CWD
(38)
t
CWD
(38)t
CWD
(38)
t
RWD
(37)
t
RCS
(17)
t
WP
(30)
t
OEA
(53) t
OEZ
(55) t
OED
(54) t
OEA
(53)
t
RAC
(13)
t
AA
(15)
t
CLZ
(12)
t
CAC
(14)
t
CAP
(43)
t
CAC
(14)
t
CLZ
(12) t
CLZ
(12)
t
DS
(33)
t
ASR
(10)
t
CWL
(32)
t
DH
(34)
Timing Waveform of
RAS
Only Refresh Cycle (WE = OE = VIH or VIL)
Timing Waveform of
CAS
-before-
RAS
Refresh Cycle (WE = A8 = VIH or VIL)
RAS
I/O
t
RPC
(50)
t
CRP
(21)
t
RAS
(3)t
RP
(2)
t
RC
(1)
t
OFF
(23)
t
CHR
(49)t
CSR
(48)
CAS
Row Address
t
RAS
(3) t
RP
(2)
t
RC
(1)
t
CRP
(9)
t
RAH
(11)t
ARS
(10)
RAS
CAS
Address
A417308
(September, 1998, Version 1.1) 14 AMIC Technology, Inc.
Timing Waveform of Hidden Refresh Cycle (Read)
Timing Waveform of Hidden Refresh Cycle (Write)
t
ASR
(10)
t
RAS
(3) t
RAS
(3) t
RP
(2)
t
RC
(1)
t
RP
(2)
t
RC
(1)
t
ASC
(24)
t
RAD
(6)
t
RSH
(7)t
RCD
(5)t
CPR
(9)
t
AR
(16)
t
CRP
(9)
t
CHR
(49)
t
RAC
(13)
t
RCS
(17) t
RRH
(19)
t
AA
(15)t
CAC
(14)
t
CLZ
(12)
t
OFF
(23)
Row Col Address
Data Out
RAS
CAS
Address
WE
OE
I/O
t
RAH
(11)
t
OEZ
(55)
t
DS
(33)
t
RC
(1)
t
RP
(2)t
RAS
(3)
t
RSH
(40)t
RCD
(5)t
CRP
(9)
t
RAL
(20)
t
AR
(16)
t
RAD
(6)
t
RAH
(11) t
CAH
(25)
t
WCH
(28)
t
WP
(30)
t
WCR
(29)
t
RWL
(31)
t
DHR
(35)
t
DH
(34)
Row Address Col Address
Data In
RAS
CAS
Address
WE
OE
I/O
t
ASR
(10)
t
WCS
(27)
t
ASC(
24)
A417308
(September, 1998, Version 1.1) 15 AMIC Technology, Inc.
Timing Waveform of
CAS
-before-
RAS
Refresh Counter Test Cycle
t
CAC
(14)
t
RAS
(3)
t
RSH
(7)
t
RP
(2)
t
CPT
(51)
t
CHR
(49) t
CAS
(4)
t
RAL
(20)
t
CAH
(25)
t
AA
(15)
t
CAC
(14)
t
CLZ
(12) t
OFF
(23)
t
RCH
(18)t
RCS
(17) t
RRH
(19)
t
RWL
(31)
t
CWL
(32)
t
WP
(30)
t
WCH
(28)t
WCS
(27)
t
DH
(34)t
DS
(33)
t
WP
(30)t
CWL
(32)
t
AWD
(39)
t
CWD
(38)
t
OED
(54)t
OEA
(53)
t
DH
(34)
t
CLZ
(12) t
AA
(15)
Col Address
Data Out
Data In
Data InData Out
RAS
CAS
Address
WE
I/O
OE
I/O
I/O
WE
OE
WE
OE
Read CycleWrite CycleRead-Write Cycle
t
OEA
(53) t
ROH
(52)
t
CSR
(48)
t
RCS
(17)
t
DS
(33)
t
OEZ
(55)
A417308
(September, 1998, Version 1.1) 16 AMIC Technology, Inc.
Capacitance15 (f = 1MHz, Ta = Room Temperature, VCC = 5V ± 10%)
Symbol Signals Parameter Max. Unit Test Conditions
CIN1 A0 - A8 5pF Vin = 0V
CIN2 RAS,CAS ,
WE , OE
Input Capacitance 7pF Vin = 0V
CI/O I/O1 - I/O8I/O Capacitance 7pF Vin = Vout = 0V
Ordering Codes
Part No. RAS Access Time
Max. (ns) Operating Current
Max. (mA) Standby Current
Max. (mA) (CMOS) Package
A417308S-35 35 160 2 26/24Pin SOJ
A417308S-40 40 150 2 26/24Pin SOJ
A417308S-45 45 140 2 26/24Pin SOJ
A417308V-35 35 160 2 28Pin TSOP (I)
A417308V-40 40 150 2 28Pin TSOP (I)
A417308V-45 45 140 2 28Pin TSOP (I)
A417308
(September, 1998, Version 1.1) 17 AMIC Technology, Inc.
Package Information
SOJ 26L/24L (300mil) Outline Dimensions unit: inches/mm
E1
E
A2
e
E
2
12
1324
S
y
A1
b
2
b
19 18
1 6 7
Pin 1 Identifier
- y -
Seating Plane 0.004
A
AA
θ
D
C
Dimensions in inches Dimensions in mm
Symbol Min Nom Max Min Nom Max
A- - 0.140 - - 3.56
A10.070 0.080 0.090 1.78 2.03 2.29
A20.095 0.100 0.105 2.41 2.54 2.67
b0.016 0.018 0.022 0.41 0.46 0.56
b20.026 0.028 0.032 0.66 0.71 0.81
C0.008 0.010 0.014 0.20 0.25 0.36
D-0.675 0.686 -17.15 17.42
E0.327 0.337 0.347 8.31 8.56 8.81
E10.295 0.300 0.305 7.49 7.62 7.75
E20.245 0.265 0.285 6.22 6.73 7.24
e0.044 0.050 0.056 1.12 1.27 1.42
S- - 0.048 - - 1.22
θ0°-10°0°-10°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E1 does not include resin fins.
3. Dimension E2 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
A417308
(September, 1998, Version 1.1) 18 AMIC Technology, Inc.
Package Information
TSOP 28L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm
Dimensions in inches Dimensions in mm
Symbol Min Nom Max Min Nom Max
A- - 0.049 - - 1.25
A10.002 - - 0.05 - -
A20.037 0.039 0.041 0.95 1.00 1.05
b0.007 0.009 0.011 0.17 0.22 0.27
c0.005 -0.008 0.12 -0.21
E0.311 0.315 0.319 7.90 8.00 8.10
L0.012 0.020 0.028 0.30 0.50 0.70
D0.520 0.528 0.536 13.20 13.40 13.60
D10.461 0.465 0.469 11.70 11.80 11.90
e0.022 BSC 0.55 BSC
S0.017 TYP 0.425 TYP
y- - 0.004 - - 0.10
θ0°-5°0°-5°
Notes:
1. The maximum value of dimension D1 includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
D
1
E
e
D
L
A
A2
c
Detail "A"
D
y
Detail "A"
S
A1
b
28
15
1
14
θ
