HI-301, HI-303 (R) Data Sheet May 2002 FN3125.7 CMOS Analog Switches Features The HI-301 and HI-303 series of switches are monolithic devices fabricated using CMOS technology and the Intersil dielectric isolation process. These switches feature break before-make switching, low and nearly constant ON resistance over the full analog signal range, and low power dissipation, (a few mW for the Hl-301 and HI-303). * Analog Signal Range (15V Supplies) . . . . . . . . . . 15V * Low Leakage at 25oC . . . . . . . . . . . . . . . . . . . . . . . 40pA * Low Leakage at 125oC . . . . . . . . . . . . . . . . . . . . . . . 1nA * Low On Resistance at 25oC . . . . . . . . . . . . . . . . . . . 35 * Break-Before-Make Delay . . . . . . . . . . . . . . . . . . . . 60ns The HI-301 and HI-303 are TTL compatible and have a logic "0" condition with an input less than 0.8V and a logic "1" condition with an input greater than 4V. (See pinouts for switch conditions with a logic "1" input.) Ordering Information PART NUMBER TEMP. RANGE (oC) * Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . 30pC * TTL, CMOS Compatible * Symmetrical Switch Elements * Low Operating Power (Typ) . . . . . . . . . . . . . . . . . . . . 1.0mW PACKAGE PKG. NO. Applications 14 Ld SOIC M14.15 * Sample and Hold (i.e., Low Leakage Switching) -55 to 125 14 Ld CERDIP F14.3 * Op Amp Gain Switching (i.e., Low On Resistance) HI1-0303-5 0 to 75 14 Ld CERDIP F14.3 * Portable, Battery Operated Circuits HI3-0303-5 0 to 75 14 Ld PDIP E14.3 * Low Level Switching Circuits HI9P0303-5 0 to 75 14 Ld SOIC M14.15 * Dual or Single Supply Systems HI9P0303-9 -40 to 85 14 Ld SOIC M14.15 HI9P0301-5 0 to 75 HI1-0303-2 Functional Diagram S IN N P D Pinouts Switch States Shown For A Logic "1" Input SPST HI-301 (SOIC) TOP VIEW DUAL SPDT HI-303 (PDIP, CERDIP, SOIC) TOP VIEW NC 1 14 V+ NC 1 14 V+ D1 2 13 D2 S3 2 13 S4 NC 3 12 NC D3 3 12 D4 S1 4 11 S2 D1 4 11 D2 NC 5 10 NC S1 5 10 S2 IN 6 9 NC IN1 6 8 V- GND 7 9 IN2 8 V- GND 7 LOGIC SW1 SW2 LOGIC SW1, SW2 SW3, SW4 0 OFF ON 0 OFF ON 1 ON OFF 1 ON OFF 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved HI-301, HI-303 Schematic Diagrams SWITCH CELL A V+ MN1B MN2B MN3B MP5B MP4B IN OUT MN4B MN6B MP3B MP2B MP1B V- A DIGITAL INPUT BUFFER AND LEVEL SHIFTER V+ D2A MP1A MP2A MP3A MP4A MP5A MP6A MP7A MP8A 200 A A LOGIC IN D1A MN1A MN2A MN3A MN4A MN5A MN6A MN7A MN8A GND VSWITCH CELL DRIVER (ONE PER SWITCH CELL) 2 HI-301, HI-303 Absolute Maximum Ratings Thermal Information Voltage Between Supplies (V+ to V-) . . . . . . . . . . . . . . . 44V (22V) Digital Input Voltage. . . . . . . . . . . . . . . . . . . . . . (V+) +4V to (V-) -4V Analog Input Voltage . . . . . . . . . . . . . . . . . . (V+) +1.5V to (V-) -1.5V Typical Derating Factor . . . . . . . . . 1.5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 80 24 PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 120 N/A Maximum Junction Temperature Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range HI-30X-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HI-30X-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC HI-30X-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Supplies = +15V, -15V; VIN = Logic Input. VIN - for Logic "1" = 4V, for Logic "0" = 0.8V. Unless Otherwise Specified -2 -5, -9 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS Switch ON Time, tON 25 - 210 300 - 210 300 ns Switch OFF Time, tOFF 25 - 160 250 - 160 250 ns Break-Before-Make Delay, tOPEN 25 - 60 - - 60 - ns Charge Injection Voltage, V (Note 7) 25 - 3 - - 3 - mV OFF Isolation (Note 6) 25 - 60 - - 60 - dB Input Switch Capacitance, CS(OFF) 25 - 16 - - 16 - pF Output Switch Capacitance, CD(OFF) 25 - 14 - - 14 - pF Output Switch Capacitance, CD(ON) 25 - 35 - - 35 - pF Digital Input Capacitance, CIN 25 - 5 - - 5 - pF Input Low Level, VINL Full - - 0.8 - - 0.8 V Input High Level, VINH (Note 10) Full 4 - - 4 - - V Input Leakage Current (Low), IINL (Note 5) Full - - 1 - - 1 A Input Leakage Current (High), IINH (Note 5) Full - - 1 - - 1 A Analog Signal Range Full -15 - +15 -15 - +15 V ON Resistance, rON (Note 2) 25 - 35 50 - 35 50 Full - 40 75 - 40 75 25 - 0.04 1 - 0.04 5 nA Full - 1 100 - 0.2 100 nA 25 - 0.04 1 - 0.04 5 nA Full - 1 100 - 0.2 100 nA 25 - 0.03 1 - 0.03 5 nA Full - 0.5 100 - 0.2 100 nA PARAMETER DYNAMIC CHARACTERISTICS DIGITAL INPUT CHARACTERISTICS ANALOG SWITCH CHARACTERISTICS OFF Input Leakage Current, IS(OFF) (Note 3) OFF Output Leakage Current, ID(OFF) (Note 3) ON Leakage Current, ID(ON) (Note 4) 3 HI-301, HI-303 Electrical Specifications Supplies = +15V, -15V; VIN = Logic Input. VIN - for Logic "1" = 4V, for Logic "0" = 0.8V. Unless Otherwise Specified (Continued) PARAMETER -2 -5, -9 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS 25 - 0.09 0.5 - 0.09 0.5 mA Full - - 1 - - 1 mA 25 - 0.01 10 - 0.01 100 A Full - - 100 - - - A 25 - 0.01 10 - 0.01 100 A Full - - 100 - - - A 25 - 0.01 10 - 0.01 100 A Full - - 100 - - - A POWER SUPPLY CHARACTERISTICS Current, I+ (Note 8) Current, I- (Note 8) Current, I+ (Note 9) Current, I- (Note 9) NOTES: 2. VS = 10V, IOUT = 3. VS = 14V, VD = 10mA. On resistance derived from the voltage measured across the switch under these conditions. 14V. 4. VS = VD = 14V. 5. The digital inputs are diode protected MOS gates and typical leakages of 1nA or less can be expected. 6. VS = 1VRMS , f = 500kHz, CL = 15pF, RL = 1K. 7. VS = 0V, CL = 10nF, Logic Drive = 5V pulse. Switches are symmetrical; S and D may be interchanged. Charge Injection = Q = CL x V. 8. VIN = 4V (one input, all other inputs = 0V). 9. VIN = 0.8V (all inputs). 10. To drive from DTL/TTL circuits, pullup resistors to +5V supply are recommended. Test Circuits and Waveforms 15V V+ S VO D VS = +3V RL 300 CL 33pF SWITCH OUTPUT LOGIC "1" = SWITCH ON LOGIC INPUT 0V VINH 50% 50% VS LOGIC INPUT GND V-15V 90% SWITCH TYPE VINH HI-301, HI-303 4V 0V SWITCH OUTPUT FIGURE 1A. TEST CIRCUIT tON FIGURE 1B. MEASUREMENT POINTS FIGURE 1. SWITCH tON AND tOFF 4 10% tOFF HI-301, HI-303 Test Circuits and Waveforms (Continued) +15V V+ RGEN = 0 VGEN S D RL 10k IN CL 10pF ) (V T U P N I IC G O L 6 4 2 0 LOGIC INPUT VGND VLOGIC -15V 0 FIGURE 2A. TEST CIRCUIT ) V ( E G A10 T L O5 V T 0 U P T U O 0.4 ) V ( E G A T L O V T U P T U O VGEN = 10V 0.8 1.2 1.6 5 0 VGEN = 5V 0 0.4 1.2 FIGURE 2B. TTL LOGIC INPUT (NOTE 11) 0 0.8 TIME (s) 0.4 1.6 TIME (s) 0.8 TIME (s) 1.2 1.6 FIGURE 2D. VANALOG = 5V FIGURE 2C. VANALOG = 10V ) V ( E G A 5 T L O 0 V T -5 U P T U O ) V ( E G A T 0 L O V -5 T U P T U O VGEN = 0V 0 0.4 0.8 TIME (s) 1.2 VGEN = -5V 1.6 0 0.4 0.8 1.2 TIME (s) FIGURE 2E. VANALOG = 0V FIGURE 2F. VANALOG = -5V 5 1.6 HI-301, HI-303 Test Circuits and Waveforms (Continued) ) V ( E G A 0 T L O -5 V T -10 U P T U O VGEN = -10V 0 0.4 0.8 1.2 1.6 TIME (s) FIGURE 2G. VANALOG = -10V NOTE: 11. If RGEN , RL or CL is increased, there will be proportional increases in rise and/or fall RC times. FIGURE 2. SWITCHING WAVEFORMS FOR VARIOUS ANALOG INPUT VOLTAGES 15V S1 VS1 = +3V VS2 = +3V V+ D1 OUT 1 D2 S2 LOGIC "1" = SWITCH ON OUT 2 RL2 CL2 RL1 CL1 LOGIC INPUT VINH RL1 = RL2 = 300 CL1 = CL2 = 33pF 0V LOGIC INPUT GND V-15V 50% SWITCH TYPE VINH HI-301, HI-303 5V 50% OUT 1 0V SWITCH OUTPUTS 50% 0V tOPEN FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMENT POINTS FIGURE 3. BREAK-BEFORE-MAKE DELAY (tOPEN) 6 OUT 2 50% tOPEN HI-301, HI-303 Typical Performance Curves 80 TA = 25oC ( E C N A 60 T IS S E R N O 40 E C R U O S O 20 A V+ = +15V, V- = -15V T B V+ = +10V, V- = -10V IN C V+ = +7.5V, V- = -7.5V A R D V+ = +5V, V- = -5V D 0 -15 -10 -5 ) 125oC 25oC -55oC 0 5 10 15 C B A 0 5 10 15 DRAIN VOLTAGE (V) DRAIN VOLTAGE (V) FIGURE 4. rDS(ON) vs VD FIGURE 5. rDS(ON) vs VD 100 100 V+ = +15V, V- = -15V V+ = +15V, V- = -15V CLOAD = 30pF, VS = 1VRMS TA = 25oC, VS = 15V, RL = 2K ) W m ( N 10 O I T A P I S S I D R 1.0 E W O P 80 ) B d ( N 60 O I T A L O IS 40 F F O RL = 100 RL = 1k 20 0 105 0.1 1 10 100 1K 10K 100K 1M 106 107 108 FREQUENCY (Hz) LOGIC SWITCHING FREQUENCY (50% DUTY CYCLE) (Hz) FIGURE 6. DEVICE POWER DISSIPATION vs SWITCHING FREQUENCY (SINGLE LOGIC INPUT) FIGURE 7. OFF ISOLATION vs FREQUENCY 10.0 10.0 V+ = +15V, V- = -15V F F O N I A R D R O E C R U O S D ) 80 V+ = +15V, V- = -15V ( E C N A 60 T S I S E R N O 40 E C R U O S O 20 T IN A R D 0 -15 -10 -5 V+ = +15V, V- = -15V | VD | = | VS | = 14V ) A n ( T 1.0 N E R R U C E G A0.1 K A E L 1.0 ) A n ( ) N O ( ID 0.1 0.01 25 75 125 TEMPERATURE (oC) FIGURE 8. IS(OFF) OR ID(OFF) vs TEMPERATURE 0.01 25 75 125 TEMPERATURE (oC) FIGURE 9. ID(ON) vs TEMPERATURE The net leakage into the source or drain is the N-Channel leakage minus the P-Channel leakage. This difference can be positive, negative or zero depending on the analog voltage and temperature, and will vary greatly from unit to unit. 7 HI-301, HI-303 Typical Performance Curves (Continued) 60 16 ) F p ( E 50 C N A T I C A P 40 A C N O T U P 30 T U O ) F p ( 12 E C N A T I C 8 A P A C T U P 4 N I TRANSITION (INDETERMINATE DUE TO ACTIVE INPUT) 20 0 2 4 6 8 10 12 14 16 0 2 4 6 DRAIN VOLTAGE (V) 8 FIGURE 10. OUTPUT ON CAPACITANCE vs DRAIN VOLTAGE V+ = +15V, V- = -15V VINH = 4.0V, VINL = 0V 300 ) s n ( E IM T G 200 N I H C T I W S 100 tON tOFF tON -35 -15 5 25 45 14 16 65 85 105 V+ = +15V, TA = 25oC VINH = 4V, VINL = 0V tOFF 0 -55 12 FIGURE 11. DIGITAL INPUT CAPACITANCE vs INPUT VOLTAGE 300 ) s (n 200 E M I T G IN H C T I 100 W S 10 INPUT VOLTAGE (V) 125 5 10 15 NEGATIVE SUPPLY (V) TEMPERATURE (oC) FIGURE 13. SWITCHING TIME vs NEGATIVE SUPPLY VOLTAGE FIGURE 12. SWITCHING TIME vs TEMPERATURE s ) ( 1.8 E M I 1.6 T E K 1.4 A M E 1.2 R O F E 1.0 B K 0.8 A E R B / 0.6 E M I 0.4 T G IN 0.2 H C IT 0 W 0 S V- = -15V, TA = 25oC VINH = 4.0V, VINL = 0V tON tOFF tOPEN ONLY 5 10 15 POSITIVE SUPPLY VOLTAGE (V) FIGURE 14. SWITCHING TIME AND BREAK-BEFORE-MAKE TIME vs POSITIVE SUPPLY VOLTAGE 8 7 V- = -15V, TA = 25oC ) V ( 6 D L O5 H S E R H4 T G IN 3 H C T I W2 S T U P 1 N I 0 0 5 10 15 POSITIVE SUPPLY VOLTAGE (V) FIGURE 15. INPUT SWITCHING THRESHOLD vs POSITIVE SUPPLY VOLTAGE HI-301, HI-303 Dual-In-Line Plastic Packages (PDIP) E14.3 (JEDEC MS-001-AA ISSUE D) 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE N E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AE D BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8 eA C 0.008 0.014 C D 0.735 0.775 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. e 0.100 BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. eB - L 0.115 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. N 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm). 9 0.204 14 0.355 18.66 19.68 5 2.54 BSC - 7.62 BSC 6 0.430 - 0.150 2.93 14 10.92 7 3.81 4 9 Rev. 0 12/93 HI-301, HI-303 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE LEAD FINISH c1 -D- -A- BASE METAL E M -Bbbb S C A-B S -C- S1 0.200 - 5.08 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.785 - 19.94 5 E 0.220 0.310 5.59 7.87 5 eA ccc M C A - B S e eA/2 c aaa M C A - B S D S D S NOTES - b2 b MAX 0.014 A A MIN b A L MAX A Q SEATING PLANE MILLIMETERS MIN M (b) D BASE PLANE SYMBOL b1 SECTION A-A D S INCHES (c) NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 105o 90o 105o - 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 90o aaa - 0.015 - 0.38 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 10 N 14 14 8 Rev. 0 4/94 HI-301, HI-303 Small Outline Plastic Packages (SOIC) M14.15 (JEDEC MS-012-AB ISSUE C) 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA 0.25(0.010) M H B M E INCHES -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3367 0.3444 8.55 8.75 3 E 0.1497 0.1574 3.80 4.00 4 e C 0.10(0.004) B S 0.050 BSC 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N NOTES: MILLIMETERS 14 0o 14 8o 0o 7 8o Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 11