1
®
FN3125.7
HI-301, HI-303
CMOS Analog Switches
The HI-301 and HI-303 series of switches are monolithic
dev i ces fabricated u s ing CMOS technology and the Inter sil
dielec tric isol atio n pr oc ess. Thes e sw it che s feature break
before-make switching, low and nearly constant ON
resistance over the full analog signal range, and low power
dissipation, (a few mW for the Hl-301 and HI-303).
The HI-3 01 and H I-303 a re TTL co mpati ble and have a l ogic
“0” condition with an input less than 0.8V and a logic “1”
condition with an input greater than 4V. (See pinouts for
switch conditions with a logic “1” input.)
Features
• Analog Sign al Range (±15V Supplies) . . . . . . . . . . ±15V
• Low Leakage at 25oC . . . . . . . . . . . . . . . . . . . . . . . 40pA
• Low Leakage at 125oC . . . . . . . . . . . . . . . . . . . . . . . 1nA
• Low On Re sistance at 25oC . . . . . . . . . . . . . . . . . . . 35Ω
• Break-Before-Make Delay . . . . . . . . . . . . . . . . . . . . 60ns
• Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . 30pC
• TTL, CMOS Compatible
• Symmetrical Switch Elements
• Low Operating Power (Typ) . . . . . . . . . . . . . . . . . . . . 1.0mW
Applications
• Sample and Hold (i.e., Low Leakage Switching)
• Op Amp Gain Switching (i.e., Low On Resistance)
• Portable, Battery Operated Circuits
• Low Level Switching Circuits
• Dual or Single Suppl y Sys tems
Functional Diagram
Pinouts Switch States Shown For A Logic “1” Input
SPST HI-301 (SOIC)
TOP VIEW DUAL SPDT HI-303 (PDIP, CERDIP, SOIC)
TOP VIE W
Ordering Information
PART
NUMBER TEMP.
RANGE (oC) PACKAGE PKG. NO.
HI9P0301-5 0 to 75 14 Ld SOIC M14.15
HI1-0303-2 -55 to 125 14 Ld CERDIP F14.3
HI1-0303-5 0 to 75 14 Ld CERDIP F14.3
HI3-0303-5 0 to 75 14 Ld PDIP E14.3
HI9P0303-5 0 to 75 14 Ld SOIC M14.15
HI9P0303-9 -40 to 85 14 Ld SOIC M14.15
S
N
IN P
D
LOGIC SW1 SW2
0OFFON
1ONOFF
NC
D1
NC
S1
NC
IN
GND
V+
D2
NC
S2
NC
NC
V-
1
2
3
4
5
6
7
14
13
12
11
10
9
8
LOGIC SW1, SW2 SW3, SW4
0OFFON
1ONOFF
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
S3
D3
D1
S1
IN1
GND
V+
S4
D4
D2
S2
IN2
V-
Data Sheet May 2002
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
2
Schem ati c Di agrams SWITCH CELL
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
MN2B
IN
MN3B
A
MP4B
MP3B MP2B
MN4B
MP5B
V+
MN6B
V-
OUT
MP1B
A
MN1B
MP3A
MN3A
MP4A
MN4A
MP2A
MN2A
MP1A
MN1A
D2A
200Ω
V+
LOGIC
GND
V-
IN
MP5A
MN5A
MP6A
MN6A
MP7A
MN7A
MP8A
MN8A
A
A
SWITCH CELL DRIVER
(ONE PER SWITCH CELL)
D1A
HI-301, HI-303
3
Absolute Maximum Ratings Thermal Information
Voltage Between Supplies (V+ to V-) . . . . . . . . . . . . . . .44V (±22V)
Digital Input Voltage. . . . . . . . . . . . . . . . . . . . . .(V+) +4V to (V-) -4V
Analog Input Voltage . . . . . . . . . . . . . . . . . .(V+) +1.5V to (V-) -1.5V
Typical De rating Factor . . . . . . . . . 1.5mA/M Hz Increase in ICCOP
ESD Classific atio n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1
Operating Conditions
Temperature Range
HI-3 0 X-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5 5oC to 125oC
HI-30X-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
HI-3 0 X-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
CERDIP Package. . . . . . . . . . . . . . . . . 80 24
PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A
SOIC Package . . . . . . . . . . . . . . . . . . . 120 N/A
Maximum Junction Temperature
Ceramic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Plasti c Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION : Stresses above those listed i n “Absolu te Maximum Rat ings” may cause perman ent damage to the device. Th is is a stress only rating and o peratio n of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Supplies = +15V, -15V; VIN = Logic Input. VIN - for Logic “1” = 4V, for Logic “0” = 0.8V.
Unless Otherwise Specified
PARAMETER TEMP
(oC)
-2 -5, -9
UNITSMIN TYP MAX MIN TYP MAX
DYNAMIC CHARACTERISTICS
Switch ON Time, tON 25 - 210 300 - 210 300 ns
Switch OFF Time , tOFF 25 - 160 250 - 160 250 ns
Break-Before-M ake Delay, tOPEN 25 -60- -60-ns
Charge Injection Voltage, ∆V (Note 7) 25 - 3 - - 3 - mV
OFF Isolation (Note 6) 25 - 60 - - 60 - dB
Input Switch Capacitance, CS(OFF) 25 -16- -16-pF
Output Switch Capacitance, CD(OFF) 25 -14- -14-pF
Output Switch Capacitance, CD(ON) 25 -35- -35-pF
Digital Input Capacitance, CIN 25 - 5 - - 5 - pF
DIGITAL INPUT CHARACTERISTICS
Input Low Level, VINL Full - - 0.8 - - 0.8 V
Input High Level, VINH (Note 10) Full 4 - - 4 - - V
Input Leakage Current (Low), IINL (Note 5) Full - - 1 - - 1 µA
Input Leakage Current (High), IINH (Note 5) Full - - 1 - - 1 µA
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range Full -15 - +15 -15 - +15 V
ON Resistance, rON (Note 2) 25 - 35 50 - 35 50 Ω
Full - 40 75 - 40 75 Ω
OFF Input Leakage Current, IS(OFF) (Note 3) 25 - 0.04 1 - 0.04 5 nA
Full - 1 100 - 0.2 100 nA
OFF Output Leakage Current, ID(OFF) (Note 3) 25 - 0.04 1 - 0.04 5 nA
Full - 1 100 - 0.2 100 nA
ON Leakage Current, ID(ON) (Note 4) 25 - 0.03 1 - 0.03 5 nA
Full - 0.5 100 - 0.2 100 nA
HI-301, HI-303
4
POWER SUPPLY CHARACTERISTICS
Curr e n t , I+ ( N o t e 8) 25 - 0 .0 9 0.5 - 0.09 0.5 mA
Full - - 1 - - 1 mA
Current, I- (Note 8) 25 - 0.01 10 - 0.01 100 µA
Full - - 100 - - - µA
Current, I+ (Note 9) 25 - 0.01 10 - 0 .01 100 µA
Full - - 100 - - - µA
Current, I- (Note 9) 25 - 0.01 10 - 0.01 100 µA
Full - - 100 - - - µA
NOTES:
2. VS = ±10V, IOUT = 10mA. On resistance derived from the voltage measured across the switch under these conditions.
3. VS = ±14V, VD = 14V.
4. VS = VD = ±14V.
5. The digital inputs are diode protected MOS gates and typical leakages of 1nA or less can be expected.
6. VS = 1VRMS, f = 500kHz, CL = 15pF, RL = 1K.
7. VS = 0V, CL = 10nF, Logic Drive = 5V pulse. Switches are symmetrical; S and D may be interchanged. Charge Injection = Q = CL x ∆V.
8. VIN = 4V (one input, all other inputs = 0V).
9. VIN = 0.8V (all inputs).
10. To drive from DTL/TTL circuits, pullup resistors to +5V supply are recommended.
Electrical Specifications Supplies = +15V, -15V; VIN = Logic Input. VIN - for Logic “1” = 4V, for Logic “0” = 0.8V.
Unless Otherwise Specified (Continued)
PARAMETER TEMP
(oC)
-2 -5, -9
UNITSMIN TYP MAX MIN TYP MAX
Test Circuits and Waveforms
FIGURE 1A. TEST CIRCUIT FIGURE 1B. MEASUREMENT POINTS
FIGURE 1. SWITCH tON AND tOFF
SWITCH TYPE VINH
HI-301, HI-303 4V
15V V+
D
RL
300ΩCL
33pF
V-
-15V
GND
LOGIC
VS = +3V S
INPUT
VOSWITCH
OUTPUT
LOGIC “1” = SWITCH ON
LOGIC
INPUT
0V
VS
0V
SWITCH
OUTPUT
VINH 50% 50%
10%
90%
tON
tOFF
HI-301, HI-303
5
FIGURE 2A. T EST CIRCUIT FIGURE 2B. TTL LOGIC INPUT
FIGURE 2C. VANALOG = 10V
FIGURE 2D. VANALOG = 5V
FIGURE 2E. VANALOG = 0V FIGURE 2F. VANALOG = -5 V
Test Circuits and Waveforms (Continued)
+15V V+
D
RL
10kΩCL
10pF
V-
-15V
GND
VLOGIC
VGEN
RGEN = 0 S
IN
TIME (µs)
6
4
2
0
0 0.4 0.8 1.2 1.6
L
O
G
I
C
I
N
P
U
T
(
V
)
LOGIC INPUT
TIME (µs)
10
5
0
00.40.81.21.6
O
U
T
P
U
T
V
O
L
T
A
G
E
(
V
)
VGEN = 10V
(NOTE 11)
TIME (µs)
5
0
0 0.4 0.8 1.2 1.6
O
U
T
P
U
T
V
O
L
T
A
G
E
(
V
)
VGEN = 5V
TIME (µs)
5
0
0 0.4 0.8 1.2 1.6
O
U
T
P
U
T
V
O
L
T
A
G
E
(
V
)
VGEN = 0V
-5
TIME (µs)
0
0 0.4 0.8 1.2 1.6
O
U
T
P
U
T
V
O
L
T
A
G
E
(
V
)
VGEN = -5V
-5
HI-301, HI-303
6
FIGURE 2G. VANALOG = -10V
NOTE:
11. If RGEN, RL or CL is increased, there will be proportional increases in rise and/or fall RC times.
FIGURE 2. SWITCHING WAVEFORMS FOR VARIOUS ANALOG INPUT VOLTAGES
FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE DELAY (tOPEN)
Test Circuits and Waveforms (Continued)
TIME (µs)
0
0 0.4 0.8 1.2 1.6
O
U
T
P
U
T
V
O
L
T
A
G
E
(
V
)
VGEN = -10V
-5
-10
SWITCH TYPE VINH
HI-301, HI-303 5V
V+
D2
RL2 CL2
V-
-15V
GND
LOGIC
VS2 = +3V S2
INPUT
OUT 1
OUT 2
D1
S1
VS1 = +3V
RL1 CL1
15V
LOGIC “1” = SWITCH ON
LOGIC
INPUT
0V
0V
SWITCH
OUTPUTS
VINH
50% 50%
tOPEN
50% 50%
0V
OUT 1
OUT 2
RL1 = RL2 = 300Ω
CL1 = CL2 = 33pF
tOPEN
HI-301, HI-303
7
Typical Performance Curves
FIGURE 4. rDS(ON) vs VDFIGURE 5. rDS(ON) vs VD
FIGURE 6. DEVICE POWER DISSIPATION vs SWITCHING
FREQUENCY (SINGLE LOGIC INPUT) FIGURE 7. OFF ISOLATION vs FREQUENCY
FIGURE 8. IS(OFF) OR ID(OFF) vs TEMPERATURE†FIGURE 9. ID(ON) vs TEMPERATURE†
† The net leakage into the source or drain is the N-Channel leakage m inus the P-Channel leakage. This difference can be pos itive, negative or
zero depending on the analog voltage and temperature, and will vary greatly from unit to unit.
DRAIN VOLTAGE (V)
D
R
A
I
N
T
O
S
O
U
R
C
E
O
N
R
E
S
I
S
T
A
N
C
E
(
Ω
)80
60
40
20
0-15 -10 -5 0 5 10 15
V+ = +15V, V- = -15V
125oC
25oC
-55oC
DRAIN VOLTAGE (V)
D
R
A
I
N
T
O
S
O
U
R
C
E
O
N
R
E
S
I
S
T
A
N
C
E
(
Ω
)80
60
40
20
0-15 -10 -5 0 5 10 15
TA = 25oC
A V+ = +15V, V- = -15V
B V+ = +10V, V- = -10V
C V+ = +7.5V, V- = -7.5V
D V+ = +5V, V- = -5V
A
B
C
D
V+ = +15V, V- = -15V
TA = 25oC, VS = 15V, RL = 2K
110
LOGIC SWITCHING FREQUENCY (50% DUTY CYCLE) (Hz)
100 1K 10K 100K 1M
0.1
1.0
10
100
P
O
W
E
R
D
I
S
S
I
P
A
T
I
O
N
(
m
W
)
RL = 100Ω
V+ = +15V, V- = -15V
CLOAD = 30pF, VS = 1VRMS
105
RL = 1kΩ
FREQUENCY (Hz)
106107108
100
80
60
40
20
0
O
F
F
I
S
O
L
A
T
I
O
N
(
d
B
)
TEMPERATURE (oC)
V+ = +15V, V- = -15V
10.0
1.0
0.1
0.0125 75 125
S
O
U
R
C
E
O
R
D
R
A
I
N
O
F
F
L
E
A
K
A
G
E
C
U
R
R
E
N
T
(
n
A
)
TEMPERATURE (oC)
V+ = +15V, V- = -15V
10.0
1.0
0.1
0.0125 75 125
ID
(
O
N
)
(
n
A
)
| VD | = | VS | = 14V
HI-301, HI-303
8
FIGURE 10. OUTPUT ON CAPACITANCE vs DRAIN VOLTAGE FIGURE 11. DIGITAL INPUT C APACITANCE vs INPUT VOLTAGE
FIGURE 12. SWITCHING TIME vs TEMPERATURE FIGURE 13. SWITCHING TIME vs NEGATIVE SUPPLY
VOLTAGE
FIGURE 14. SWITCHING TIME AND BREAK-BEFORE-MAKE
TIME vs POSITIVE SUPPLY VOLTAGE FIGURE 15. INPUT SWITCHING THRESHOLD vs POSITIVE
SUPPLY VOLTAGE
Typical Performance Curves (Continued)
DRAIN VOLTAGE (V)
10 12 14 1686420
60
50
40
30
20
O
U
T
P
U
T
O
N
C
A
P
A
C
I
T
A
N
C
E
(
p
F
)
INPUT VOLTAGE (V)
10 12 14 1686420
16
12
8
4
I
N
P
U
T
C
A
P
A
C
I
T
A
N
C
E
(
p
F
)
TRANSITION (INDETERMINATE
DUE TO ACTIVE INPUT)
TEMPERATURE (oC)
65 85 105 12545255-35-55
300
200
100
S
W
I
T
C
H
I
N
G
T
I
M
E
(
n
s
)
-15
tON
tOFF
V+ = +15V, V- = -15V
VINH = 4.0V, VINL = 0V
NEGATIVE SUPPLY (V)
10 1550
300
200
100
S
W
I
T
C
H
I
N
G
T
I
M
E
(
n
s
)
V+ = +15V, TA = 25oC
VINH = 4V, VINL = 0V
tON
tOFF
POSITIVE SUPPLY VOLTAGE (V)
10 1550
1.8
0.6
S
W
I
T
C
H
I
N
G
T
I
M
E
/
B
R
E
A
K
-
B
E
F
O
R
E
-
M
A
K
E
T
I
M
E
(
µ
s
)
V- = -15V, TA = 25oC
VINH = 4.0V, VINL = 0V
tON
tOFF
1.6
1.4
1.2
1.0
0.8
0.4
0.2
0
tOPEN
ONLY
POSITIVE SUPPL Y VOLTAGE (V)
10 1550
7
1
I
N
P
U
T
S
W
I
T
C
H
I
N
G
T
H
R
E
S
H
O
L
D
(
V
)6
5
4
3
2
0
V- = -15V, TA = 25oC
HI-301, HI-303
9
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of confli ct between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpen-
dicular to datum .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -
1.14mm).
eA-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMINMAXMINMAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N14 149
Rev. 0 12/93
HI-301, HI-303
10
HI-301, HI-303
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
bbb C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
-D-
-A-
-C-
-B-
α
D
E
S1
b2 b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
A
M
SS
ccc C A - B
MD
SSaaa CA - B
MD
SS
eA
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.200 - 5.08 -
b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 -
b3 0.023 0.045 0.58 1.14 4
c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3
D - 0.785 - 19.94 5
E 0.220 0.310 5.59 7.87 5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC -
eA/2 0.150 BSC 3.81 BSC -
L 0.125 0.200 3.18 5.08 -
Q 0.015 0.060 0.38 1.52 6
S1 0.005 - 0.13 - 7
α90o105o90o105o-
aaa -0.015-0.38 -
bbb -0.030-0.76 -
ccc - 0.010 - 0.25 -
M - 0.0015 - 0.038 2, 3
N14 148
Rev. 0 4/94
11
All Inters il semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
HI-301, HI-303
Small Outline Plast ic Pac ka g es (S OIC )
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) BM M
α
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMINMAXMINMAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.3367 0.3444 8.55 8.75 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N14 147
α0o8o0o8o-
Rev. 0 12/93