ASM1232LP/LPS
Alliance Semiconductor
2575 Augustine Drive . Santa Clara, CA 95054 . Tel: 408.855.4900 . Fax: 408.855.4999 . www.alsc.com
Notice: The information in this document is subject to change without notice
January 2005
rev 1.5 5V µP Power Supply Monitor and Reset Circuit
General Description
The ASM1232LP/LPS is a fully integrated microprocessor
supervisor. It can halt and restart a “hung-up” microprocessor,
restart a microprocessor after a power failure. It has a
watchdog timer and external reset override.
A precision temperature-compensated reference and
comparator circuits monitor the 5V, VCC input voltage status.
During power-up or when the VCC power supply falls outside
selectable tolerance limits, both RESET and RESET become
active. When VCC rises above the threshold voltage, the reset
signals remain active for an additional 250ms minimum,
allowing the power supply and system microprocessor to
stabilize. The trip point tolerance signal, TOL, selects the trip
level tolerance to be either 5% or 10%.
Each device has both a push-pull, active HIGH reset output
and an open drain active LOW reset output. A debounced
manual reset input, PBRST, activates the reset outputs for a
minimum period of 250ms.
There is a watchdog timer to stop and restart a microprocessor
that is “hung-up”. The watchdog timeouts periods are
selectable: 150ms, 610ms and 1200ms. If the ST input is not
strobed LOW before the time-out period expires, a reset is
generated.
Devices are available in 8-pin DIP, 16-pin SO and compact 8-
pin MicroSO packages.
Key Features
• 5V supply monitor
• Selectable watchdog period
• Debounce manual push-button reset input
• Precision temperature-compensated voltage reference
and comparator.
• Power-up, power-down and brown out detection
• 250ms minimum reset time
• Active LOW open drain reset output and active HIGH
push-pull output
• Selectable trip point tolerance: 5% or 10%
• Low-cost surface mount packages: 8-pin/16-pin SO, 8-pin
DIP and 8-pin Micro SO packages
• Wide operating temperature -40°C to +85°C (N suffixed
devices)
Applications
• Microprocessor Systems
• Computers
• Controllers
• Portable Equipment
• Intelligent Instuments
• Automotive Systems
Typical Operating Circuit
Block Diagram
ASM1232LP/LPS
ST
RESET
GND TD TOL
I/O
RESET
µP
10kΩ
+5V
Tolerance Selection
Reference
Push Button
Voltage Sense
Watchdog Transition
Reset &
Debounce
Comparators
Detector
Watchdog Timer
+
-RESET
RESET
PBRST
ST
TD
TOL
VCC
GND
40kΩ
VCC
ASM1232LP/LPS
ASM1232LP/LPS
2 of 10
Notice: The information in this document is subject to change without notice
5V µP Power Supply Monitor and Reset Circuit
January 2005
rev 1.5
Pin Configuration
Pin Description
Pin #
8-Pin Package
Pin #
16-Pin Package
Pin
Name Function
1 2 PBRST Debounced manual pushbutton RESET input.
24TD
Watchdog time delay selection. (tTD = 150ms for TD = GND, tTD = 610ms
for TD=Open, and tTD = 1200ms for TD = VCC).
36TOL
Selects 5% (TOL connected to GND) or 10% (TOL connected to VCC)
trip point tolerance.
4 8 GND Ground.
5 9 RESET
Active HIGH reset output. RESET is active:
1. If VCC falls below the reset voltage trip point.
2. If PBRST is LOW.
3. If ST is not strobed LOW before the timeout period set by TD expires.
4. During power-up.
6 11 RESET Active LOW reset output. (See RESET).
713ST
Strobe input.
815
VCC 5V power.
-1,3,5,7,
10,12,14,16 NC No internal connection.
1
2
3
45
6
7
8
PBRST
TD
TOL
GND
VCC
ST
RESET
RESET
1
2
3
4
5
6
7
8
PBRST
TD
TOL
GND
VCC
ST
RESET
RESET
ASM1232LPS
9
10
11
12
13
14
15
16
NC
NC
NC
NC NC
NC
NC
NC
ASM1232LPU
DIP/SO/MicroSO SO
ASM1232LP
ASM1232LPS-2
3 of 10
Notice: The information in this document is subject to change without notice
5V µP Power Supply Monitor and Reset Circuit
ASM1232LP/LPS
January 2005
rev 1.5
Detailed Description
The ASM1232LP/LPS monitors the microprocessor or
microcontroller power supply and generates reset signal,
both active HIGH and Active LOW, that halt processor
operation whenever the power supply voltage levels are
outside a predetermined tolerance.
RESET and RESET outputs
RESET is an active HIGH signal developed by a CMOS
push-pull output stage and is the logical opposite to RESET.
RESET is an active LOW signal. It is developed with an open
drain driver. A pull up resistor of typical value 10kΩ to 50kΩ is
required to connect with the output.
Trip Point Tolerance Selection
The TOL input is used to determine the level VCC can vary
below 5V without asserting a reset. With TOL conected to
VCC, RESET and RESET become active whenever VCC falls
below 4.5V. RESET and RESET become active when the
VCC falls below 4.75V if TOL is connected to ground.
After VCC has risen above the trip point set by TOL, RESET
and RESET remain active for a minimum time period of
250ms. On power-down, once VCC falls below the reset
threshold RESET stays LOW and is guaranteed to be 0.4V or
less until VCC drops below 1.2V. The active HIGH reset signal
is valid down to a VCC level of 1.2V also.
Application Information
Manual Reset Operation
Push-button switch input, PBRST, allows the user to override
the internal trip point detection circuits and issue reset
signals. The pushbutton input is debounced and is pulled
HIGH through an internal 40kΩ resistor.
Tolerance
Select Tolerance
TRIP Point Voltage
(V)
Min Nom Max
TOL = VCC 10% 4.25 4.37 4.49
TOL = GND 5% 4.5 4.62 4.74
~
~
~
~
~
~
VOH
VOL
tRPU
RESET
RESET
VCCTP(MIN)
VCCTP(MAX)
VCCTP
tR
VCC
Figure 1: Timing Diagram : Power Up
~
~
~
~
~
~
VOH
VOL
VCCTP (MAX)
VCCTP
VCCTP (MIN)
RESET
RESET
tF
VCC
tRPD
Figure 2: Timing Diagram : Power Down
4 of 10
Notice: The information in this document is subject to change without notice
5V µP Power Supply Monitor and Reset Circuit
ASM1232LP/LPS
January 2005
rev 1.5
When PBRST is held LOW for the minimum time tPB, both
resets become active and remain active for a minimum time
period of 250ms after PBRST returns HIGH.
The debounced input is guaranteed to recognize pulses
greater than 20ms. No external pull-up resistor is required,
since PBRST is pulled HIGH by an internal 40kΩ resistor.
The PBRST can be driven from a TTL or CMOS logic line or
shorted to ground with a mechanical switch.
Watchdog Timer and ST Input
A watchdog timer stops and restarts a microprocessor that is
“hung-up”. The µP must toggle the ST input within a set
period (as selectable through TD input) to verify proper
software execution. If the ST is not toggled low within the
minimum timeout period, reset signals become active. In
power-up after the supply voltage returns to an in-tolerance
condition, the reset signal remains active for 250ms
minimum, allowing the power supply and system
microprocessor to stabilize. ST pulses as short as 20ns can
be detected.
Timeouts periods of approximately 150ms, 610ms or
1,200ms are selected through the TD pin.
The watchdog timer can not be disabled. It must be strobed
with a high-to-low transition to avoid watchdog timeout and
reset.
TD Voltage level Watchdog Time-out Period
(ms)
Min Nom Max
GND 62.5 150 250
Floating 250 610 1000
VCC 500 1200 2000
~
~~
~~
~
V
OH
V
OL
RESET
RESET
PBRST t
PB
t
PDLY
V
IH
t
RST
Figure 3: Timing Diagram: Pushbutton Reset
PBRST
TD
TOL
GND
V
CC
ST
RESET
RESET
1
2
3
45
6
7
8
µP
RESET
5V
ASM1232LP/LPS
Figure 4: Application Circuit: Pushbutton Reset
~
~
Valid Valid Invalid
ST
RESET
tRST
tST
tTD (min) tTD (max)
Strobe Strobe Strobe
Figure 5: Timing Diagram: Strobe Input
Note: ST is ignored whenever a reset is active
PBRST
T
D
TOL
GND
V
CC
ST
RESET
1
2
3
45
6
7
8
µP
RESET
5V
ASM1232 LP/LPS
Figure 6: Application Circuit: Watchdog Timer
Decoder
Address
Bus
MREQ
10kΩ
V
IL
I/O
ASM1232LP/LPS
5 of 10
Notice: The information in this document is subject to change without notice
5V µP Power Supply Monitor and Reset Circuit
January 2005
rev 1.5
Absolute Maximum Ratings
DC Electrical Characteristics
Unless otherwise stated, 4.5V <= VCC<= 5.5V and over the operating temperature range of 0°C to 70°C (-40°C to +85°C. for N devices). All
voltages are referenced to ground.
Parameter Min Max Unit
Voltage on VCC -0.5 7 V
Voltage on ST, TD -0.5 VCC + 0.5 V
Voltage on PBRST, RESET, RESET -0.5 VCC + 0.5 V
Operating Temperature Range (N suffixed devices) -40 +85 °C
Operating Temperature Range (others) 0 70 °C
Soldering Temperature (for 10 sec) +260 °C
Storage Temperature -55 +125 °C
ESD rating
HBM
MM
2
200
KV
V
Note:
1. Voltages are measured with respect to ground
2. These are stress ratings only and functional implication is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.
Parameter Symbol Conditions Min Typ Max Unit
Supply Voltage VCC 4.5 5.5 V
ST and PBRST Input High Level VIH 2VCC + 0.3 V
ST and PBRST Input Low Level VIL -0.3 0.8 V
VCC Trip Point (TOL = GND) VCCTP 4.50 4.62 4.74 V
VCC Trip Point (TOL = VCC)V
CCTP 4.25 4.37 4.49 V
Watchdog Timeout Period tTD TD = GND 62.5 150 250 ms
Watchdog Timeout Period tTD TD = VCC 500 1200 2000 ms
Watchdog Timeout Period tTD TD Floating 250 610 1000 ms
Output Voltage VOH I=-500µA, Note 3 VCC - 0.5 VCC - 0.1 V
Output Current IOH Output = 2.4V, Note 2 -8 -10 mA
Output Current IOL Output = 0.4V 10 mA
ASM1232LP/LPS
6 of 10
Notice: The information in this document is subject to change without notice
5V µP Power Supply Monitor and Reset Circuit
January 2005
rev 1.5
Notes
1. PBRST is internally pulled HIGH to VCC through a nominal 40kΩ resistor.
2. RESET is an open drain output.
3. RESET remains within 0.5V of VCC on power-down until VCC falls below 2V. RESET remains within 0.5V of ground on power-down until VCC
falls below 2.0V.
4. Must not exceed the minimum watchdog time-out period (tTD). The watchdogcircuit cannot be disabled. To avoid a reset, ST must be strobed.
Input Leakage IIL Note 1 -1.0 1.0 µA
RESET Low Level VOL Note 3 0.4 V
Internal Pull-up Resistor Note 1 40 kΩ
Operating Current (CMOS) ICC1 30 µA
Input Capacitance CIN 5pF
Output Capacitance COUT 10 pF
PBRST Manual Reset
Minimum Low Time tPB PBRST = VIL 20 ms
Reset Active Time tRST 250 610 1000 ms
ST Pulse Width tST Note 4 20 ns
VCC Fail Detect to RESET or
RESET tRPD 58µs
VCC Slew Rate tF4.75V to 4.25V 300 µs
PBRST Stable LOW to RESET and
RESET Active tPDLY 20 ms
VCC Detect to RESET or RESET
inactive tRPU tRISE = 5µs 250 610 1000 ms
VCC Slew Rate tR4.25V to 4.75V 0 ns
Parameter Symbol Conditions Min Typ Max Unit
7 of 10
Notice: The information in this document is subject to change without notice
5V µP Power Supply Monitor and Reset Circuit
ASM1232LP/LPS
January 2005
rev 1.5
Package Information
MicroSO (8-Pin)
SO (8-Pin)
Plastic DIP (8-Pin)
Inches Millimeteres
Min Max Min Max
MicroSO (8-Pin)
A 0.032 0.044 0.81 1.10
A1 0.002 0.006 0.05 0.15
A2 0.030 0.038 0.76 0.97
b 0.012 BSC 0.30 BSC
C 0.004 0.008 0.10 0.20
D 0.114 0.122 2.90 3.10
e 0.0256 BSC 0.65 BSC
E 0.184 0.200 4.67 5.08
E1 0.114 0.122 2.90 3.10
L 0.016 0.026 0.41 0.66
S 0.0206 BSC 0.52 BSC
a0°6°0°6°
SO (8-Pin)
A 0.053 0.069 1.35 1.75
A1 0.004 0.010 0.10 0.25
A2 0.049 0.059 1.25 1.50
B 0.012 0.020 0.31 0.51
C 0.007 0.010 0.18 0.25
D 0.193 BSC 4.90 BSC
E 0.154 BSC 3.91 BSC
e 0.050 BSC 1.27 BSC
H 0.236 BSC 6.00 BSC
L 0.016 0.050 0.41 1.27
θ0° 8° 0° 8°
Plastic DIP (8-Pin)
A - 0.210 - 5.33
A1 0.015 - 0.38 -
A2 0.115 0.195 2.92 4.95
b 0.014 0.022 0.36 0.56
b2 0.045 0.070 1.14 1.78
C 0.008 0.014 0.20 0.36
D 0.355 0.400 9.02 10.16
E 0.300 0.325 7.62 8.26
E1 0.240 0.280 6.10 7.11
e 0.100 BSC 2.54 BSC
eB - 0.430 - 10.92
L 0.115 0.150 2.92 3.81
D
EH
D
A1
A2
A
θ
L
C
B
e
ASM1232LP/LPS
8 of 10
Notice: The information in this document is subject to change without notice
5V µP Power Supply Monitor and Reset Circuit
January 2005
rev 1.5
SO (16-Pin)
* JEDEC Drawing MS-013AA
SO (16-Pin)*
Inches Millimeter
Min Max Min Max
A 0.053 0.069 1.35 1.75
A1 0.004 0.010 0.10 0.25
A2 0.049 0.059 1.25 1.50
B 0.013 0.022 0.33 0.53
C 0.008 0.012 0.19 0.27
D 0.386 0.394 9.80 10.01
E 0.150 0.157 3.80 4.00
e 0.050 BSC 1.27 BSC
H 0.228 0.244 5.80 6.20
h 0.010 0.016 0.25 0.41
L 0.016 0.035 0.40 0.89
θ0° 8° 0° 8°
EH
A
A1
A2
D
e
B
θ
L
C
h
Seating Plane
D
0.004
PIN 1 ID
1
8
916
ASM1232LP/LPS
9 of 10
Notice: The information in this document is subject to change without notice
5V µP Power Supply Monitor and Reset Circuit
January 2005
rev 1.5
Ordering Information
Part Number Package
Operating
Temperature
Range
Maximum
Supply
Current (µA)
Voltage
Monitoring
Application
Package Marking
TIN-LEAD DEVICES
ASM1232LP 8L PDIP 0°C to +70°C 30 5V ASM1232LP
ASM1232LPN 8L PDIP -40° C to +85°C 30 5V ASM1232LPN
ASM1232LPS 16L SOIC 0°C to +70°C 30 5V ASM1232LPS
ASM1232LPS-2 8L SOIC 0°C to +70° C 30 5V ASM1232LPS-2
ASM1232LPSN 16L SOIC -40°C to +85°C 30 5V ASM1232LPSN
ASM1232LPSN-2 8L SOIC -40°C to +85°C 30 5V ASM1232LPSN-2
ASM1232LPU 8L MSOP 0°C to +70°C 30 5V ASM1232LP
ASM1232LPUN 8L MSOP -40°C to +85°C 30 5V ASM1232LPN
LEAD FREE DEVICES
ASM1232LPF 8L PDIP 0°C to +70°C 30 5V ASM1232LPF
ASM1232LPNF 8L PDIP -40°C to +85°C 30 5V ASM1232LPNF
ASM1232LPS-2F 8L SOIC 0°C to +70°C 30 5V ASM1232LPS-2F
ASM1232LPSF 16L SOIC 0°C to +70°C 30 5V ASM1232LPSF
ASM1232LPSN-2F 8L SOIC -40°C to +85°C 30 5V ASM1232LPSN-2F
ASM1232LPSNF 16L SOIC -40°C to +85°C 30 5V ASM1232LPSNF
ASM1232LPUF 8L MSOP 0°C to +70°C 30 5V ASM1232LPF
ASM1232LPUNF 8L MSOP -40°C to +85°C 30 5V ASM1232LPNF
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM1232LP/LPS
Document Version: 1.5
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or
registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the
right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear
in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to
change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and
users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any
responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related
to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement
of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All
sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does
not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third
parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may
reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the
manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
ASM1232LP/LPS
