Complete Quad, 16-Bit, High Accuracy,
Serial Input, ±5 V DAC
Data Sheet AD5765
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2009–2011 Analog Devices, Inc. All rights reserved.
FEATURES
Complete quad, 16-bit digital-to-analog converter (DAC)
Programmable output range: ±4.096 V, ±4.201 V, or ±4.311 V
±1 LSB maximum INL error, ±1 LSB maximum DNL error
Low noise: 70 nV/√Hz
Settling time: 10 μs maximum
Integrated reference buffers
On-chip die temperature sensor
Output control during power-up/brownout
Programmable short-circuit protection
Simultaneous updating via LDAC
Asynchronous CLR to zero code
Digital offset and gain adjustment
Logic output control pins
DSP-/microcontroller-compatible serial interface
Temperature range: −40°C to +105°C
iCMOS® process technology1
APPLICATIONS
Industrial automation
Open-/closed-loop servo control
Process control
Data acquisition systems
Automatic test equipment
Automotive test and measurement
High accuracy instrumentation
GENERAL DESCRIPTION
The AD5765 is a quad, 16-bit, serial input, bipolar voltage
output, digital-to-analog converter (DAC) that operates from
supply voltages of ±4.75 V to ±5.25 V. The nominal full-scale
output range is ±4.096 V. The AD5765 provides integrated
output amplifiers, reference buffers, and proprietary power-
up/power-down control circuitry. The part also features a
digital I/O port, which is programmed via the serial interface.
The part incorporates digital offset and gain adjustment
registers per channel.
The AD5765 is a high performance converter that offers
guaranteed monotonicity, integral nonlinearity (INL) of ±1 LSB,
low noise, and 10 μs settling time. During power-up (when the
supply voltages are changing), the outputs are clamped to 0 V
via a low impedance path.
The AD5765 uses a serial interface that operates at clock rates of
up to 30 MHz and is compatible with DSP and microcontroller
interface standards. Double buffering allows the simultaneous
updating of all DACs. The input coding is programmable to
either a twos complement or an offset binary format. The
asynchronous clear function clears all DAC registers to either
bipolar zero or zero scale, depending on the coding used. The
AD5765 is ideal for both closed-loop servo control and open-
loop control applications. The AD5765 is available in a 32-lead
TQFP and offers guaranteed specifications over the −40°C to
+105°C industrial temperature range. Figure 1 contains a
functional block diagram of the AD5765.
Table 1. Related Devices
Part No. Description
AD5764 Complete quad, 16-bit, high accuracy, serial input,
±10 V DAC
AD5763 Complete dual, 16-bit, high accuracy, serial input,
±5 V DAC
1 For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS is a technology
platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies, allowing dramatic reductions in power consumption and
package size and increased ac and dc performance.
AD5765 Data Sheet
Rev. C | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications ..................................................................................... 4
AC Performance Characteristics ................................................ 6
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings .......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 13
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
DAC Architecture ....................................................................... 17
Reference Buffers ........................................................................ 17
Serial Interface ............................................................................ 17
Simultaneous Updating via LDAC ........................................... 18
Transfer Function ....................................................................... 19
Asynchronous Clear (CLR) ....................................................... 19
Function Register ....................................................................... 20
Data Register ............................................................................... 20
Coarse Gain Register ................................................................. 20
Fine Gain Register ...................................................................... 21
Offset Register ............................................................................ 21
Offset and Gain Adjustment Worked Example ...................... 22
Design Features ............................................................................... 23
Analog Output Control ............................................................. 23
Digital Offset and Gain Control ............................................... 23
Programmable Short-Circuit Protection ................................ 23
Digital I/O Port ........................................................................... 23
Die Temperature Sensor ............................................................ 23
Local-Ground-Offset Adjustment ........................................... 23
Power-On Status ......................................................................... 24
Applications Information .............................................................. 25
Typical Operating Circuit ......................................................... 25
Precision Voltage Reference Selection ..................................... 25
Layout Guidelines ........................................................................... 26
Galvanically Isolated Interface ................................................. 26
Microprocessor Interfacing ....................................................... 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
10/11—Rev. B to Rev. C
Changed 50 MHz to 30 MHz ....................................... Throughout
Changes to t1, t2, and t3 Parameters, Table 4 .................................. 7
7/11—Rev. A to Rev. B
Changed 30 MHz to 50 MHz Throughout.................................... 1
Changes to t1, t2, and t3 Parameters, Table 4 .................................. 7
Changes to Table 21 ........................................................................ 25
Changes to Ordering Guide .......................................................... 27
10/09—Rev. 0 to Rev. A
Deleted Endnote 1, Table 2 .............................................................. 4
Deleted Endnote 1, Table 3 .............................................................. 6
Deleted Endnote 1, Table 4 .............................................................. 7
Changes to t6 Parameter, Table 4 .................................................... 7
1/09—Revision 0: Initial Version
Data Sheet AD5765
Rev. C | Page 3 of 28
FUNCTIONAL BLOCK DIAGRAM
DAC C
DAC D
DAC B
INPUT
REG A
INPUT
REG B
INPUT
REG C
INPUT
REG D
GAIN REG A
OFFSET REG A
GAIN REG B
OFFSET REG B
GAIN REG C
OFFSET REG C
GAIN REG D
OFFSET REG D
DAC
REG A
DAC
REG B
DAC
REG C
DAC
REG D
16
16
16
16
16 DAC A
LDAC REFCD
RSTINRSTOUT
REFABREFGND
AGNDD
07249-001
VOUTD
AGNDC
VOUTC
AGNDB
VOUTB
AGNDA
VOUTA
ISCC
REFERENCE
BUFFERS
SDIN
SCLK
SYNC
SDO
D0
D1
BIN/2sCOMP
CLR
PGND
DV
CC
DGND
G1
G2
G1
G2
G1
G2
G1
G2
AV
DD
AV
DD
AV
SS
AV
SS
INPUT
SHIFT
REGISTER
AND
CONTROL
LOGIC
VOLTAGE
MONITOR
AND
CONTROL
REFERENCE
BUFFERS
AD5765
TEMP
SENSOR
TEMP
Figure 1.
AD5765 Data Sheet
Rev. C | Page 4 of 28
SPECIFICATIONS
AVDD = 4.75 V to 5.25 V, AV SS = −4.75 V to −5.25 V, AGNDx = DGND = REFGND = PGND = 0 V, REFAB = REFCD = 2.048 V,
DVCC = 2.7 V to 5.25 V, RLOAD = 5 kΩ, CLOAD = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter B Grade1 C Grade1 Unit Test Conditions/Comments
ACCURACY
Outputs unloaded
Resolution 16 16 Bits
Relative Accuracy (INL) ±2 ±1 LSB max
Differential Nonlinearity (DNL) ±1 ±1 LSB max Guaranteed monotonic
Bipolar Zero Error ±2 ±2 mV max At 25°C
±3 ±3 mV max
Bipolar Zero Temperature
Coefficient (TC)2
±1 ±1 ppm FSR/°C typ
Zero-Scale Error ±2 ±2 mV max At 25°C
±3.5 ±3.5 mV max
Zero-Scale Temperature
Coefficient (TC)2
±1 ±1 ppm FSR/°C typ
Gain Error ±0.03 ±0.03 % FSR max At 25°C, coarse gain register = 0
±0.04 ±0.04 % FSR max Coarse gain register = 0
Gain TC2 ±1 ±1 ppm FSR/°C typ
DC Crosstalk2 0.5 0.5 LSB max
REFERENCE INPUT2
Reference Input Voltage 2.048 2.048 V nominal ±1% for specified performance
DC Input Impedance 1 1 MΩ min Typically, 100 MΩ
Input Current ±10 ±10 µA max Typically, ±30 nA
Reference Range 1 to 2.1 1 to 2.1 V min to V max
OUTPUT CHARACTERISTICS2
Output Voltage Range3 ±4.31158 ±4.31158 V min/V max Coarse gain register = 2
±4.20103 ±4.20103 V min/V max Coarse gain register = 1
±4.096 ±4.096 V min/V max Coarse gain register = 0
±4.42105 ±4.42105 V min/V max VREFIN = 2.1 V, coarse gain register = 2
Output Voltage Drift vs. Time ±32 ±32 ppm FSR/500 hours typ
±37 ±37 ppm FSR/1000 hours typ
Short-Circuit Current
10
10
mA typ
RI
SCC
= 6 kΩ; see Figure 23
Load Current ±1 ±1 mA max For specified performance
Capacitive Load Stability
RLOAD = ∞ 200 200 pF max
RLOAD = 10 kΩ 1000 1000 pF max
DC Output Impedance 0.3 0.3 Ω max
DIGITAL INPUTS2 DVCC = 2.7 V to 5.25 V, JEDEC
compliant
V
IH
, Input High Voltage
2
2
V min
VIL, Input Low Voltage 0.8 0.8 V max
Input Current ±1 ±1 µA max Per pin
Pin Capacitance 10 10 pF max Per pin
Data Sheet AD5765
Rev. C | Page 5 of 28
Parameter B Grade1 C Grade1 Unit Test Conditions/Comments
DIGITAL OUTPUTS (D0, D1, SDO)2
Output Low Voltage 0.4 0.4 V max DVCC = 5 V ± 5%, sinking 200 µA
Output High Voltage DVCC − 1 DVCC − 1 V min DVCC = 5 V ± 5%, sourcing 200 µA
Output Low Voltage 0.4 0.4 V max DVCC = 2.7 V to 3.6 V, sinking 200 µA
Output High Voltage
DV
CC
− 0.5
DV
CC
− 0.5
V min
DV
CC
= 2.7 V to 3.6 V, sourcing 200 µA
High Impedance Leakage Current ±1 ±1 µA max SDO only
High Impedance Output
Capacitance
5 5 pF typ SDO only
DIE TEMPERATURE SENSOR
Output Voltage at 25°C 1.44 1.44 V typ
Output Voltage Scale Factor 3 3 mV/°C typ
Output Voltage Range 1.175 to 1.9 1.175 to 1.9 V min to V max
Output Load Current 200 200 µA max
Power-On Time 10 10 ms typ
POWER REQUIREMENTS
AVDD/AVSS 4.75 to 5.25 4.75 to 5.25 V min to V max
DVCC 2.7 to 5.25 2.7 to 5.25 V min to V max
AIDD 2.25 2.25 mA/channel max Outputs unloaded
AISS 1.9 1.9 mA/channel max Outputs unloaded
DICC 1.2 1.2 mA max VIH = DVCC, VIL = DGND, 750 µA typ
Power Supply Sensitivity2
∆V
OUT
/∆ΑV
DD
−110
−110
dB typ
Power Dissipation 76 76 mW typ ±5 V operation output unloaded
1 Temperature range: −40°C to +105°C; typical at +25°C.
2 Guaranteed by design and characterization; not production tested.
3 Output amplifier headroom requirement is 0.5 V minimum.
AD5765 Data Sheet
Rev. C | Page 6 of 28
AC PERFORMANCE CHARACTERISTICS
AVDD = 4.75 V to 5.25 V, AV SS = −4.75 V to −5.25 V, AGNDx = DGND = REFGND = PGND = 0 V, REFAB = REFCD = 2.048 V,
DVCC = 2.7 V to 5.25 V, RLOAD = 5 kΩ, CLOAD = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter B Grade C Grade Unit Test Conditions/Comments
DYNAMIC PERFORMANCE1
Output Voltage Settling Time 8 8 µs typ Full-scale step to ±1 LSB
10 10 µs max
2 2 µs typ 512 LSB step settling
Slew Rate
5
5
V/µs typ
Digital-to-Analog Glitch Energy 20 20 nV-sec typ
Glitch Impulse Peak Amplitude 30 30 mV typ
Channel-to-Channel Isolation 60 60 dB typ
DAC-to-DAC Crosstalk 8 8 nV-sec typ
Digital Crosstalk 2 2 nV-sec typ
Digital Feedthrough
2
2
nV-sec typ
Effect of input bus activity on DAC outputs
Output Noise, 0.1 Hz to 10 Hz 0.1 0.1 LSB p-p typ
Output Noise, 0.1 Hz to 100 kHz 50 50 µV rms typ
1/f Corner Frequency 300 300 Hz typ
Output Noise Spectral Density 70 70 nV/√Hz typ Measured at 10 kHz
Complete System Output Noise Spectral Density2 80 80 nV/√Hz typ Measured at 10 kHz
1 Guaranteed by design and characterization; not production tested.
2 Includes noise contributions from integrated reference buffers, 16-bit DAC, and output amplifier.
Data Sheet AD5765
Rev. C | Page 7 of 28
TIMING CHARACTERISTICS
AVDD = 4.75 V to 5.25 V, AV SS = −4.75 V to −5.25 V, AGNDx = DGND = REFGND = PGND = 0 V, REFAB = REFCD = 2.048 V,
DVCC = 2.7 V to 5.25 V, RLOAD = 5 kΩ, CLOAD = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1, 2, 3 Limit at TMIN, TMAX Unit Description
t1 33 ns min SCLK cycle time
t2 13 ns min SCLK high time
t3 13 ns min SCLK low time
t4 13 ns min SYNC falling edge to SCLK falling edge setup time
t54 13 ns min 24th SCLK falling edge to SYNC rising edge
t6 90 ns min Minimum SYNC high time
t7 2 ns min Data setup time
t8 5 ns min Data hold time
t9 1.7 µs min SYNC rising edge to LDAC falling edge when all DACs are updated
480 ns min SYNC rising edge to LDAC falling edge when a single DAC is updated
t
10
10
ns min
LDAC pulse width low
t11 500 ns max LDAC falling edge to DAC output response time
t12 10 µs max DAC output settling time
t13 10 ns min CLR pulse width low
t14 2 µs max CLR pulse activation time
t155, 6 25 ns max SCLK rising edge to SDO valid
t16 13 ns min SYNC rising edge to SCLK falling edge
t17 2 µs max SYNC rising edge to DAC output response time (LDAC = 0)
t18 170 ns min LDAC falling edge to SYNC rising edge
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 Standalone mode only.
5 Measured with the load circuit of Figure 5.
6 Daisy-chain mode only.
AD5765 Data Sheet
Rev. C | Page 8 of 28
DB23
SCLK
SYNC
SDIN
LDAC
LDAC = 0
CLR
1 2 24
DB0
t1
VOUTx
VOUTx
VOUTx
t
4
t
6
t
3
t
2
t
5
t
8
t
7
t
10
t
9
t
10
t
11
t
12
t
12
t
17
t
18
t
13
t
14
07249-002
Figure 2. Serial Interface Timing Diagram
LDAC
SDO
SDIN
SYNC
SCLK 24 48
DB23 DB0 DB23 DB0
DB23
INP UT WORD F OR DAC NUNDEFINED
INP UT WORD F OR DAC N – 1INP UT WORD F OR DAC N
DB0
t
1
t
3
t
2
t
7
t
8
t
15
t
10
t
9
t
5
t
16
t
6
t
4
07249-003
Figure 3. Daisy-Chain Timing Diagram
Data Sheet AD5765
Rev. C | Page 9 of 28
SDO
SDIN
SYNC
SCLK 24 48
DB23 DB0 DB23 DB0
DB23
UNDEFINED
NOP CONDITION
DB0
INPUT WORD SPECIFIES
REG IST E R TO BE RE AD
SELECTED REGISTER DATA
CLOCKED O UT
07249-004
Figure 4. Readback Timing Diagram
200µA I
OL
200µA I
OH
V
OH
(MIN) OR
V
OL
(MAX)
TO OUTPUT
PIN C
L
50pF
07249-005
Figure 5. Load Circuit for SDO Timing Diagram
AD5765 Data Sheet
Rev. C | Page 10 of 28
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 5.
Parameter Rating
AV
DD
to AGNDx, DGND
−0.3 V to +7 V
AVSS to AGNDx, DGND +0.3 V to −7 V
DVCC to DGND −0.3 V to +7 V
DVCC to AVDD −DVCC to +0.25 V
Digital Inputs to DGND −0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
Digital Outputs to DGND −0.3 V to DVCC + 0.3 V
REFx to AGNDx, PGND −0.3 V to AVDD + 0.3 V
VOUTx to AGNDx AVSS to AVDD
AGNDx to DGND −0.3 V to +0.3 V
Operating Temperature Range (TA)
Industrial
−40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C
Power Dissipation (TJ max – TA)/θJA
Lead Temperature JEDEC industry standard
Soldering J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 6. Thermal Resistance
Package Type θJA θJC Unit
32-Lead TQFP 65 12 °C/W
ESD CAUTION
Data Sheet AD5765
Rev. C | Page 11 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
NC = NO CONNECT
AD5765
TOP VIEW
(No t t o Scal e)
07249-006
1
SYNC
2
SCLK
3
SDIN
4
SDO
5
CLR
6
LDAC
7
D0
8
D1
9
RSTOUT
10
RSTIN
11
DGND
12
DV
CC
13
AV
DD
14
PGND
15
AV
SS
16
ISCC
17
AGNDD
18
VOUTD
19
VOUTC
20
AGNDC
21
AGNDB
22
VOUTB
23
VOUTA
24
AGNDA
25
REFAB
26
REFCD
27
NC
28
REFGND
29
TEMP
30
AV
SS
31
AV
DD
32
BIN/2sCOMP
Figure 6. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1 SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred in on the falling edge of SCLK.
2
SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds
of up to 30 MHz.
3 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK.
4 SDO Serial Data Output. This is used to clock data from the serial register in daisy-chain or readback mode.
51 CLR Negative Edge Triggered Input. Asserting this pin sets the DAC registers to 0x0000.
6 LDAC Load DAC. Logic input. This is used to update the DAC registers and consequently the analog outputs. When tied
permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high during
the write cycle, the DAC input register is updated but the output update is held off until the falling edge of LDAC.
In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC pin must
not be left unconnected.
7, 8 D0, D1 D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs that are configurable and
readable over the serial interface. When configured as inputs, these pins have weak internal pull-ups to DVCC. When
programmed as outputs, D0 and D1 are referenced by DVCC and DGND.
9 RSTOUT Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If desired, it can
be used to control other system components.
10 RSTIN Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to this input
clamps the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1. Register values remain
unchanged.
11 DGND Digital Ground Pin.
12 DVCC Digital Supply Pin. Voltage ranges from 2.7 V to 5.25 V.
13, 31 AVDD Positive Analog Supply Pins. Voltage ranges from 4.75 V to 5.25 V.
14 PGND Ground Reference Point for Analog Circuitry.
15, 30 AVSS Negative Analog Supply Pins. Voltage ranges from –4.75 V to –5.25 V.
16 ISCC This pin is used in association with an optional external resistor to AGND to program the short-circuit current of
the output amplifiers. See the Design Features section for additional details.
17 AGNDD Ground Reference Pin for the DAC D Output Amplifier.
18 VOUTD Analog Output Voltage of DAC D. This provides buffered output with a nominal full-scale output range of ±4.096 V. The
output amplifier is capable of directly driving a 5 kΩ, 200 pF load.
AD5765 Data Sheet
Rev. C | Page 12 of 28
Pin No. Mnemonic Description
19 VOUTC Analog Output Voltage of DAC C. This provides buffered output with a nominal full-scale output range of ±4.096 V. The
output amplifier is capable of directly driving a 5 kΩ, 200 pF load.
20 AGNDC Ground Reference Pin for the DAC C Output Amplifier.
21 AGNDB Ground Reference Pin for the DAC B Output Amplifier.
22 VOUTB Analog Output Voltage of DAC B. This provides buffered output with a nominal full-scale output range of ±4.096 V. The
output amplifier is capable of directly driving a 5 kΩ, 200 pF load.
23 VOUTA Analog Output Voltage of DAC A. This provides buffered output with a nominal full-scale output range of ±4.096 V. The
output amplifier is capable of directly driving a 5 kΩ, 200 pF load.
24 AGNDA Ground Reference Pin for the DAC A Output Amplifier.
25 REFAB External Reference Voltage Input for Channel A and Channel B. The reference input range is 1 V to 2.1 V; this
programs the full-scale output voltage. VREFIN = 2.048 V for specified performance.
26 REFCD External Reference Voltage Input for Channel C and Channel D. The reference input range is 1 V to 2.1 V; this
programs the full-scale output voltage. VREFIN = 2.048 V for specified performance.
27 NC No Connect.
28 REFGND Reference Ground Return for the Reference Generator and Buffers.
29 TEMP This pin provides an output voltage proportional to temperature. The output voltage is 1.4 V, typical, at 25°C die
temperature; variation with temperature is 5 mV/°C.
32 BIN/2sCOMP Determines the DAC Coding. This pin should be hardwired to either DVCC or DGND. When hardwired to DVCC, input
coding is offset binary. When hardwired to DGND, input coding is twos complement
(see Table 8).
1 Internal pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high condition.
Data Sheet AD5765
Rev. C | Page 13 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
010,000 20,000 30,000
CODE 40,000 50,000 60,000
INL ERRO R ( LSBs)
T
A
= 25° C
07249-007
Figure 7. Integral Nonlinearity Error vs. Code
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
010,000 20,000 30,000
CODE 40,000 50,000 60,000
DNL E RROR (L S Bs)
T
A
= 25° C
07249-008
Figure 8. Differential Nonlinearity Error vs. Code
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
–40 –20 020 40 60 80 100
INL ERRO R ( LSBs)
TEMPERATURE (°C)
07249-009
Figure 9. Integral Nonlinearity Error vs. Temperature
–0.25
–0.20
–0.15
0.10
0
0.10
0.20
0.30
0.05
0.05
0.15
0.25
–40 –20 020 40 60 80 100
DNL E RROR (L S Bs)
TEMPERATURE (°C)
07249-010
Figure 10. Differential Nonlinearity Error vs. Temperature
7.7
7.8
7.9
8.0
8.1
8.2
8.3
8.4
8.5
8.6
8.7
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
AI
DD
/AI
SS
(mA)
AV
DD
/AV
SS
(V)
AI
SS
AI
DD
T
A
= 25° C
07249-016
Figure 11. AIDD/AISS vs. AVDD/AVSS
0.50
0.55
0.60
0.65
0.70
0.75
0.80
–40 –20 020 40 60 80 100
ZE RO-SCALE E RROR (mV)
TEMPERATURE (°C)
07249-017
Figure 12. Zero-Scale Error vs. Temperature
AD5765 Data Sheet
Rev. C | Page 14 of 28
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
–40 –20 020 40 60 80 100
BIP OLAR ZERO ERRO R ( mV )
TEMPERATURE (°C)
07249-018
Figure 13. Bipolar Zero Error vs. Temperature
–0.016
–0.015
–0.014
–0.013
–0.012
–0.011
–0.010
–0.009
–0.008
–40 –20 020 40 60 80 100
GAIN ERRO R ( %FSR)
TEMPERATURE (°C)
07249-019
Figure 14. Gain Error vs. Temperature
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
012345
LOGIC INPUT VOLTAGE (V)
DI
CC
(mA)
07249-020
T
A
= 25° C
Figure 15. DICC vs. Logic Input Voltage
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
–8 –6 –4 –2 0246810
OUTPUT VOLTAGE DELTA (mV)
SO URCE /SI NK CURRE NT (mA)
AV
DD
= +5V
AV
SS = –5V
TA = 25° C
07249-021
Figure 16. Source and Sink Capability of Output Amplifier with Positive
Full-Scale Loaded
–4
–3
–2
–1
0
1
2
3
4
–10 –8 –6 –4 –2 0246810
OUTPUT VOLTAGE DELTA (mV)
SO URCE /SI NK CURRE NT (mA)
AVDD = +5V
AVSS = –5V
TA = 25° C
07249-022
Figure 17. Source and Sink Capability of Output Amplifier with Negative Full-
Scale Loaded
07249-023
CH1 1.25V M1.00µs CH1 –175mV
1
Figure 18. Positive Full-Scale Step
Data Sheet AD5765
Rev. C | Page 15 of 28
07249-024
CH1 1.25V M1.00µs CH1 175mV
1
Figure 19. Negative Full-Scale Step
–40
–30
–20
–10
0
10
20
30
40
–1.0 –0.5 00.5 1.0 1.5 2.0 2.5 3.0
OUTPUT VOLTAGE (mV)
TIME (µs)
0x7FFF TO 0x8000
0x8000 TO 0x7FFF
07249-026
T
A
= 25° C
Figure 20. Major Code Transition Glitch Energy
07249-027
CH4 50µV M1.00µs CH4 26µV
4
Figure 21. Peak-to-Peak Noise (100 kHz Bandwidth)
07249-024
CH1 5.00V CH2 5.00V
CH3 50.0mV M25.0ms CH1 4.1V
3
2
1
Figure 22. VOUT vs. AVDD/AVSS on Power-Up
0
1
2
3
4
5
6
7
8
9
10
12345678910
SHO RT-CI RCUIT CURRE NT (mA)
RISCC (kΩ)
07249-029
TA = 25° C
Figure 23. Short-Circuit Current vs. RISCC
1.2
1.3
1.4
1.5
1.6
1.7
1.8
–40 –20 020 40 60 80 100
TEMP OUTPUT VO L T AGE (V)
TEMPERATURE (°C)
AV
DD
= +5V
AV
SS
= –5V
07249-030
Figure 24. TEMP Output Voltage vs. Temperature
AD5765 Data Sheet
Rev. C | Page 16 of 28
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 7.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic. A
typical DNL vs. code plot can be seen in Figure 8.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5765 is
monotonic over its full operating temperature range.
Bipolar Zero Error
Bipolar zero error is the deviation of the analog output from the
ideal half-scale output of 0 V when the DAC register is loaded
with 0x8000 (offset binary coding) or 0x0000 (twos complement
coding). A plot of bipolar zero error vs. temperature can be seen
in Figure 13.
Bipolar Zero Temperature Coefficient (TC)
Bipolar zero temperature coefficient is the measure of the
change in the bipolar zero error with a change in temperature. It
is expressed as (ppm FSR)/°C.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code is loaded to the DAC register. Ideally, the output voltage
should be 2 × VREF − 1 LSB. Full-scale error is expressed as a
percentage of the full-scale range.
Negative Full-Scale Error/Zero Scale Error
Negative full-scale error is the error in the DAC output voltage
when 0x0000 (offset binary coding) or 0x8000 (twos complement
coding) is loaded to the DAC register. Ideally, the output voltage
is −2 × VREF. A plot of zero-scale error vs. temperature can be
seen in Figure 12.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for the
output to settle to a specified level for a full-scale input change.
Slew Rate
The slew rate of a device is a limitation in the rate of change of
the output voltage. The output slewing speed of a voltage-
output DAC is usually limited by the slew rate of the amplifier
used at its output. Slew rate is measured from 10% to 90% of the
output signal and is given in V/µs.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range. A plot of
gain error vs. temperature can be seen in Figure 14.
Total Unadjusted Error (TUE)
Total unadjusted error (TUE) is a measure of the output error
considering all the various errors.
Zero-Scale Error Temperature Coefficient
Zero-scale error temperature coefficient is a measure of the
change in zero-scale error with a change in temperature. Zero-
scale error TC is expressed as (ppm FSR)/°C.
Gain Error Temperature Coefficient
Gain error temperature coefficient is a measure of the change in
gain error with changes in temperature. Gain error temperature
coefficient is expressed as (ppm of FSR)/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by 1 LSB at
the major carry transition, 0x7FFF to 0x8000 (see Figure 20).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the DAC
but is measured when the DAC output is not updated. It is spec-
ified in nV-sec and is measured with a full-scale code change on
the data bus, that is, from all 0s to all 1s and vice versa.
Power Supply Sensitivity
Power supply sensitivity indicates how the output of the DAC is
affected by changes in the power supply voltage.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC while
monitoring another DAC and is expressed in LSBs.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s and vice versa) with
LDAC low and monitoring the output of another DAC. The
energy of the glitch is expressed in nV-sec.
Channel-to-Channel Isolation
Channel-to-channel isolation is the ratio of the amplitude of the
signal at the output of one DAC to a sine wave on the reference
input of another DAC. It is measured in decibels.
Digital Crosstalk
Digital crosstalk is a measure of the impulse injected into the
analog output of one DAC from the digital inputs of another
DAC but is measured when the DAC output is not updated. It is
specified in nV-sec and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Data Sheet AD5765
Rev. C | Page 17 of 28
THEORY OF OPERATION
The AD5765 is a quad, 16-bit, serial input, bipolar voltage output
DAC that operates from supply voltages of ±4.75 V to ±5.25 V and
has a buffered output voltage of up to ±4.311 V. Data is written to
the AD5765 in a 24-bit word format, via a 3-wire serial interface.
The device also offers an SDO pin, which is available for daisy-
chaining or readback.
The AD5765 incorporates a power-on reset circuit, which
ensures that the DAC registers power up loaded with 0x0000.
The AD5765 features a digital I/O port that can be programmed
via the serial interface, on-chip reference buffers and per
channel digital gain, and offset registers.
DAC ARCHITECTURE
The DAC architecture of the AD5765 consists of a 16-bit
current mode segmented R-2R DAC. The simplified circuit
diagram for the DAC section is shown in Figure 25.
The four MSBs of the 16-bit data-word are decoded to drive 15
switches, E1 to E15. Each of these switches connects one of the
15 matched resistors to either AGNDx or IOUT. The remaining
12 bits of the data-word drive switches S0 to S11 of the 12-bit
R-2R ladder network.
2R
E15
VREF
2R
E14 E1
2R
S11
R R R
2R
S10
2R
12-BIT, R- 2R LADDER4 MSBs DECODED INTO
15 EQUAL SE GMENTS
VOUTx
2R
S0
2R
AGNDx
R/8
IOUT
07249-060
Figure 25. DAC Ladder Structure
REFERENCE BUFFERS
The AD5765 operates with an external reference. The reference
inputs (REFAB and REFCD) have an input range up to 2.1 V.
This input voltage is then used to provide a buffered positive
and negative reference for the DAC cores. The positive
reference is given by
+VREF = 2 VREF
The negative reference to the DAC cores is given by
−VREF = −2 VREF
These positive and negative reference voltages (along with the
gain register values) define the output ranges of the DACs.
SERIAL INTERFACE
The AD5765 is controlled over a versatile 3-wire serial interface
that operates at clock rates of up to 30 MHz and is compatible
with SPI, QSPI™, MICROWIRE™, and DSP standards.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. The input register consists of a read/write
bit, three register select bits, three DAC address bits, and 16 data
bits as shown in Table 9. The timing diagram for this operation
is shown in Figure 2.
At power-up, the DAC registers are loaded with zero code
(0x0000), and the outputs are clamped to 0 V via a low impedance
path. The outputs can be updated with the zero code value at
this time by asserting either LDAC or CLR. The corresponding
output voltage depends on the state of the BIN/2sCOMP pin.
If the BIN/2sCOMP pin is tied to DGND, the data coding is
twos complement, and the outputs update to 0 V. If the
BIN/2sCOMP pin is tied to DVCC, the data coding is offset
binary, and the outputs update to negative full scale. To have the
outputs power up with zero code loaded to the outputs, the CLR
pin should be held low during power-up.
Standalone Operation
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous SCLK source can be used
only if SYNC is held low for the correct number of clock cycles.
In gated clock mode, a burst clock containing the exact number
of clock cycles must be used, and SYNC must be taken high
after the final clock to latch the data. The first falling edge of
SYNC starts the write cycle. Exactly 24 falling clock edges must
be applied to SCLK before SYNC is brought high again. If
SYNC is brought high before the 24th falling SCLK edge, the data
written is invalid. If more than 24 falling SCLK edges are applied
before SYNC is brought high, the input data is also invalid. The
input register addressed is updated on the rising edge of SYNC.
In order for another serial transfer to take place, SYNC must be
brought low again. After the end of the serial data transfer, data
is automatically transferred from the input shift register to the
addressed register.
When the data has been transferred into the chosen register of
the addressed DAC, all DAC registers and outputs can be
updated by taking LDAC low.
AD5765 Data Sheet
Rev. C | Page 18 of 28
68HC111
MISO
SYNC
SDIN
SCLK
MOSI
SCK
PC7
PC6 LDAC
SDO
SYNC
SCLK
LDAC
SDO
SYNC
SCLK
LDAC
SDO
SDIN
SDIN
1ADDITIONAL PINS OMITTED FOR CLARITY.
AD5765
1
AD5765
1
AD5765
1
07249-061
Figure 26. Daisy-Chaining the AD5765
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy-chain several devices together. This daisy-chain
mode can be useful in system diagnostics and in reducing the
number of serial interface lines. The first falling edge of SYNC
starts the write cycle. The SCLK is continuously applied to the
input shift register when SYNC is low. If more than 24 clock
pulses are applied, the data ripples out of the shift register and
appears on the SDO line. This data is clocked out on the rising
edge of SCLK and is valid on the falling edge. By connecting the
SDO of the first device to the SDIN input of the next device in
the chain, a multidevice interface is constructed. Each device in
the system requires 24 clock pulses. Therefore, the total number
of clock cycles must equal 24 N, where N is the total number of
AD5765 devices in the chain. When the serial transfer to all
devices is complete, SYNC is taken high. This latches the input
data in each device in the daisy chain and prevents additional
data from being clocked into the input shift register. The serial
clock can be a continuous or a gated clock.
A continuous SCLK source can be used only if SYNC is held
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
be used, and SYNC must be taken high after the final clock to
latch the data.
Readback Operation
Before a readback operation is initiated, the SDO pin must be
enabled by writing to the function register and clearing the
SDO disable bit; this bit is cleared by default. Readback mode is
invoked by setting the R/W bit to 1 in the serial input register
write. With R/W = 1, Bit A2 to Bit A0, in association with Bit
REG2, Bit REG1, and Bit REG0, select the register to be read.
The remaining data bits in the write sequence are don’t care.
During the next SPI write, the data appearing on the SDO
output is the data from the previously addressed register. For a
read of a single register, the NOP command can be used in
clocking out the data from the selected register on SDO. The
readback diagram in Figure 4 shows the readback sequence. For
example, to read back the fine gain register of Channel A on the
AD5765, implement the following sequence:
1. Write 0xA0XXXX to the AD5765 input register. This
configures the AD5765 for read mode with the fine gain
register of Channel A selected. Note that all the data bits,
DB15 to DB0, are don’t cares.
2. Follow this with a second write, an NOP condition,
0x00XXXX. During this write, the data from the fine gain
register is clocked out on the SDO line; that is, data clocked
out contains the data from the fine gain register in Bit DB5
to Bit DB0.
SIMULTANEOUS UPDATING VIA LDAC
Depending on the status of both SYNC and LDAC, and after
data has been transferred into the input register of the DACs,
there are two ways in which the DAC registers and DAC
outputs can be updated: individually and simultaneously
Individual DAC Updating
In this mode, LDAC is held low while data is clocked into the
input shift register. The addressed DAC output is updated on
the rising edge of SYNC.
Simultaneous Updating of All DACs
In this mode, LDAC is held high while data is clocked into the
input shift register. All DAC outputs are updated by taking
LDAC low any time after SYNC has been taken high. The
update now occurs on the falling edge of LDAC.
VOUTx
DAC
REGISTER
INTERFACE
LOGIC
OUTPUT
I/V AMPLIFIER
LDAC
SDO
SDIN
16-BIT
DAC
V
REFIN
SYNC
INPUT
REGISTER
SCLK
07249-062
Figure 27. Simplified Serial Interface of Input Loading Circuitry
for One DAC Channel
Data Sheet AD5765
Rev. C | Page 19 of 28
TRANSFER FUNCTION
Table 8 shows the ideal input-code-to-output-voltage rela-
tionship for the AD5765 for both offset binary and twos
complement data coding.
Table 8. Ideal Output Voltage to Input Code Relationship
Digital Input Analog Output
Offset Binary Data Coding
MSB LSB VOUTx
1111 1111 1111 1111 2 VREF × (32,767/32,768)
1000 0000 0000 0001 2 VREF × (1/32,768)
1000 0000 0000 0000 0 V
0111 1111 1111 1111 −2 VREF × (1/32,768)
0000 0000 0000 0000 −2 VREF × (32,767/32,768)
Twos Complement Data Coding
MSB LSB VOUTx
0111 1111 1111 1111 2 VREF × (32,767/32,768)
0000 0000 0000 0001 2 VREF × (1/32,768)
0000 0000 0000 0000 0 V
1111 1111 1111 1111 −2 VREF × (1/32,768)
1000 0000 0000 0000 −2 VREF × (32,767/32,768)
The output voltage expression for the AD5765 is given by
×+×−= 536,65
42
D
VV
V
REFINREFINOUT
where:
D is the decimal equivalent of the code loaded to the DAC.
VREFIN is the reference voltage applied at the REFAB and
REFCD pins.
ASYNCHRONOUS CLEAR (CLR)
CLR is a negative edge triggered clear that allows the outputs to
be cleared to either 0 V (twos complement coding) or negative
full scale (offset binary coding). It is necessary to maintain CLR
low for a minimum amount of time (see Figure 2) for the
operation to complete. When the CLR signal is returned high,
the output remains at the cleared value until a new value is
programmed. If, at power-on, CLR is at 0 V, then all DAC
outputs are updated with the clear value. A clear can also be
initiated through software by writing the command 0x04XXXX
to the AD5765.
Table 9. AD5765 Input Register Format
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15:DB0
R/W 0 REG2 REG1 REG0 A2 A1 A0 Data
Table 10. Input Register Bit Functions
Bit Description
R/W
Indicates a read from or a write to the addressed register
REG2, REG1, REG0 Used in association with the address bits to determine if a read or write operation is to the data register, offset
register, gain register, or function register
REG2 REG1 REG0 Function
0 0 0 Function register
0 1 0 Data register
0 1 1 Coarse gain register
1 0 0 Fine gain register
1 0 1 Offset register
A2, A1, A0 Used to decode the DAC channels
A2 A1 A0 Channel Address
0 0 0 DAC A
0 0 1 DAC B
0 1 0 DAC C
0 1 1 DAC D
1
0
0
All DACs
D15:D0 Data bits
AD5765 Data Sheet
Rev. C | Page 20 of 28
FUNCTION REGISTER
The function register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine
the function addressed. The functions available via the function register are outlined in Table 11 and Table 12.
Table 11. Function Register Options
REG2 REG1 REG0 A2 A1 A0 DB15:DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 No operation, data = don’t care
0
0
0
0
0
1
Don’t care
Local ground
offset adjustment
D1
direction
D1
value
D0
direction
D0
value
SDO
disable
0 0 0 1 0 0 Clear, data = don’t care
0 0 0 1 0 1 Load, data = don’t care
Table 12. Explanation of Function Register Options
Option Description
NOP No operation instruction used in readback operations.
Local Ground
Offset Adjustment
Set by the user to enable the local ground offset adjustment function. Cleared by the user to disable the local ground
offset adjustment function (default). See the Design Features section for additional details.
D0/D1 Direction Set by the user to enable D0/D1 as outputs. Cleared by the user to enable D0/D1 as inputs (default). See the Design
Features section for additional details.
D0/D1 Value I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when
configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input.
When enabled as inputs, these bits are don’t cares during a write operation.
SDO Disable Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).
Clear Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode.
Load Addressing this function updates the DAC registers and, consequently, the analog outputs.
DATA REGISTER
The data register is addressed by setting the three REG bits to 010. The DAC address bits select the DAC channel with which the data
transfer is to take place (see Table 10). The data bits are in the DB15 to DB0 positions, as shown in Table 13.
Table 13. Programming the AD5765 Data Register
REG2 REG1 REG0 A2 A1 A0 DB15:DB0
0 1 0 DAC address 16-bit DAC data
COARSE GAIN REGISTER
The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select the DAC channel with which the
data transfer is to take place (see Table 10). The coarse gain register is a 2-bit register and allows the user to select the output range of each
DAC, as shown in Table 14 and Table 15.
Table 14. Programming the AD5765 Coarse Gain Register
REG2
REG1
REG0
A2
A1
A0
DB15:DB2
DB1
DB0
0 1 1 DAC address Don’t care CG1 CG0
Table 15. Output Range Selection
Output Range CG1 CG0
±4.096 V (default)
0
0
±4.20103 V 0 1
±4.31158 V 1 0
Data Sheet AD5765
Rev. C | Page 21 of 28
FINE GAIN REGISTER
The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select the DAC channel with which the data
transfer is to take place (see Table 10). The fine gain register is a 6-bit register and allows the user to adjust the gain of each DAC channel
by −32 LSBs to +31 LSBs in 1 LSB increments as shown in Table 16 and Table 17. The adjustment is made to both the positive full-scale
and negative full-scale points simultaneously, each point being adjusted by ½ of one step. The fine gain register coding is twos complement.
Table 16. Programming AD5765 Fine Gain Register
REG2 REG1 REG0 A2 A1 A0 DB15:DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 0 0 DAC address Don’t care FG5 FG4 FG3 FG2 FG1 FG0
Table 17. AD5765 Fine Gain Register Options
Gain Adjustment FG5 FG4 FG3 FG2 FG1 FG0
+31 LSBs 0 1 1 1 1 1
+30 LSBs 0 1 1 1 1 0
…
…
…
…
...
…
…
No Adjustment (Default) 0 0 0 0 0 0
… … … … … … …
−31 LSBs 1 0 0 0 0 1
−32 LSBs 1 0 0 0 0 0
OFFSET REGISTER
The offset register is addressed by setting the three REG bits to 101. The DAC address bits select the DAC channel with which the data
transfer is to take place (see Table 10). The AD5765 offset register is an 8-bit register and allows the user to adjust the offset of each channel
by −16 LSBs to +15.875 LSBs in increments of ⅛ LSB as shown in Table 18 and Table 19. The offset register coding is twos complement.
Table 18. Programming the AD5765 Offset Register
REG2 REG1 REG0 A2 A1 A0 DB15:DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 0 1 DAC address Don’t care OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0
Table 19. AD5765 Offset Register Options
Offset Adjustment OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0
+15.875 LSBs
0
1
1
1
1
1
1
1
+15.75 LSBs 0 1 1 1 1 1 1 0
… … … … … … … … …
No Adjustment (Default) 0 0 0 0 0 0 0 0
… … … … … … … … …
−15.875 LSBs 1 0 0 0 0 0 0 1
−16 LSBs
1
0
0
0
0
0
0
0
AD5765 Data Sheet
Rev. C | Page 22 of 28
OFFSET AND GAIN ADJUSTMENT WORKED
EXAMPLE
Using the information provided in the Theory of Operation
section, the following worked example demonstrates how the
AD5765 functions can be used to eliminate both offset and gain
errors. Because the AD5765 is factory calibrated, offset and gain
errors should be negligible. However, errors can be introduced
by the system that the AD5765 is operating within; for example,
a voltage reference value that is not equal to 2.048 V introduces
a gain error. An output range of ±4.096 V and twos complement
data coding are assumed.
Removing Offset Error
The AD5765 can eliminate an offset error in the range of −2 mV to
+1.98 mV with a step size of ⅛ of a 16-bit LSB.
1. Calculate the step size of the offset adjustment.
μV625.15
82 192.816 =
×
=SizeStepAdjustOffset
2. Measure the offset error by programming 0x0000 to the
data register and measuring the resulting output voltage;
for this example, the measured value is 614 µV.
3. Calculate the number of offset adjustment steps that this
value represents.
Steps13
μV625.15
μV614 === SizeStepOffset ValueOffsetMeasured
StepsofNumber
The offset error measured is positive; therefore, a negative
adjustment of 40 steps is required. The offset register is 8-bits
wide and the coding is twos complement.
The required offset register value can be calculated as follows:
1. Convert the adjustment value to binary: 00101000.
2. Convert the binary number to a negative twos complement
number by inverting all bits and adding 1: 11011000.
11011000 is the value that should be programmed to the
offset register.
Note that this twos complement conversion is not
necessary in the case of a positive offset adjustment. The
value to be programmed to the offset register is simply the
binary representation of the adjustment value.
Removing Gain Error
The AD5765 can eliminate a gain error at negative full-scale
output in the range of −2 mV to +1.94 mV with a step size of ½
of a 16-bit LSB.
1. Calculate the step size of the gain adjustment.
μV5.62
22 192.816 =
×
=SizeStepAdjustGain
2. Measure the gain error by programming 0x8000 to the data
register and measuring the resulting output voltage. The
gain error is the difference between this value and −4.096 V;
for this example, the gain error is −0.8 m V.
3. Calculate how many gain adjustment steps this value
represents.
Steps13
μV5.62 mV8.0 === SizeStepGain ValueGainMeasured
StepsofNumber
The gain error measured is negative (in terms of magnitude);
therefore, a positive adjustment of 13 steps is required. The gain
register is six bits wide and the coding is twos complement.
The required gain register value can be determined as follows:
1. Convert the adjustment value to binary: 001101.
The value to be programmed to the gain register is simply
this binary number.
Data Sheet AD5765
Rev. C | Page 23 of 28
DESIGN FEATURES
ANALOG OUTPUT CONTROL
In many industrial process control applications, it is vital that
the output voltage be controlled during power-up and during
brownout conditions. When the supply voltages are changing,
the output pins are clamped to 0 V via a low impedance path.
To prevent the output amp being shorted to 0 V during this
time, transmission gate G1 is also opened (see Figure 28). These
conditions are maintained until the power supplies stabilize and
a valid word is written to the DAC register. At this time, G2
opens and G1 closes.
Both transmission gates are also externally controllable via the
reset logic (RSTIN) control input. For instance, if RSTIN is
driven from a battery supervisor chip, the RSTIN input is
driven low to open G1 and close G2 on power-down or during a
brownout. Conversely, the on-chip voltage detector output
(RSTOUT) is also available to the user to control other parts of
the system. The basic transmission gate functionality is shown
in Figure 28.
G1
G2
RSTOUT RSTIN
VOUTA
AGNDA
VOLTAGE
MONITOR
AND
CONTROL
07249-063
Figure 28. Analog Output Control Circuitry
DIGITAL OFFSET AND GAIN CONTROL
The AD5765 incorporates a digital offset adjustment function
with a ±16 LSB adjustment range and 0.125 LSB resolution. The
gain register allows the user to adjust the AD5765 full-scale
output range. The full-scale output can be programmed to
achieve full-scale ranges of ±4.096 V, ±4.201 V, and ±4.311 V. A
fine gain trim is also provided.
PROGRAMMABLE SHORT-CIRCUIT PROTECTION
The short-circuit current of the output amplifiers can be pro-
grammed by inserting an external resistor between the ISCC
pin and PGND. The programmable range for the current is
500 µA to 10 mA, corresponding to a resistor range of 120 kΩ
to 6 kΩ. The resistor value is calculated as follows:
SC
I
R60
≈
If the ISCC pin is left unconnected, the short-circuit current
limit defaults to 5 mA. It should be noted that limiting the
short-circuit current to a small value can affect the slew rate of
the output when driving into a capacitive load; therefore, the
value of the short-circuit current programmed should take into
account the size of the capacitive load being driven.
DIGITAL I/O PORT
The AD5765 contains a 2-bit digital I/O port (D1 and D0).
These bits can be configured as inputs or outputs independently
and can be driven or have their values read back via the serial
interface. The I/O port signals are referenced to DVCC and DGND.
When configured as outputs, they can be used as control signals
to multiplexers or can be used to control calibration circuitry
elsewhere in the system. When configured as inputs, the logic
signals from limit switches, for example, can be applied to D0
and D1 and can be read back via the digital interface.
DIE TEMPERATURE SENSOR
The on-chip die temperature sensor provides a voltage output
that is linearly proportional to the centigrade temperature scale.
Its nominal output voltage is 1.44 V at +25°C die temperature,
varying at 3 mV/°C and resulting in a typical output range of
1.175 V to 1.9 V over the full temperature range. Its low output
impedance and linear output simplify interfacing to temperature
control circuitry and ADCs. The temperature sensor is provided
as more of a convenience than a precise feature; it is intended to
indicate a die temperature change for recalibration purposes.
LOCAL-GROUND-OFFSET ADJUSTMENT
The AD5765 incorporates a local-ground-offset adjustment
feature that, when enabled in the function register, adjusts the
DAC outputs for voltage differences between the individual
DAC ground pins and the REFGND pin, ensuring that the DAC
output voltages are always referenced with respect to the local
DAC ground pin. For instance, if Pin AGNDA is at +5 mV with
respect to the REFGND pin and VOUTA is measured with
respect to AGNDA, a −5 mV error results, enabling the local-
ground-offset adjustment feature to adjust VO U TA b y + 5 m V,
thereby eliminating the error.
AD5765 Data Sheet
Rev. C | Page 24 of 28
POWER-ON STATUS
The AD5765 has multiple power supply and digital input pins.
It is important to consider the sequence in which the pins are
powered up to ensure that the AD5765 powers on in the
required state. The outputs power on either clamped to
AGNDx, driving 0 V, or driving negative full-scale output
(−4.096 V), depending on how the BIN/2sCOMP, CLR, and
LDAC pins are configured during power-up.
The CLR pin, if connected to DGND, causes the DAC registers
to be loaded with 0x0000 and the outputs to be updated;
consequently, the outputs are loaded with 0 V if BIN/2sCOMP
is connected to DGND or with negative full-scale (−4.096 V) if
BIN/2sCOMP is connected to DVCC, corresponding respectively
to the twos complement and binary voltages for the digital code
0x0000. During power-up, the state of the LDAC pin has an
identical effect to that of the CLR pin. If both the CLR and
LDAC pins are connected to DVCC during power-up, the
outputs power on clamped to AGNDx and remain so until a
valid write is made to the device. Table 20 outlines the possible
output power-on states.
Table 20. Output Power-On States
BIN/2sCOMP CLR LDAC VOUT at Power-On
DGND DGND DGND 0 V
DGND
DGND
DV
CC
0 V
DGND DVCC DGND 0 V
DGND DVCC DVCC Clamped to AGNDx
DVCC DGND DGND −4.096 V
DVCC DGND DVCC −4.096 V
DVCC DVCC DGND −4.096 V
DVCC DVCC DVCC Clamped to AGNDx
Data Sheet AD5765
Rev. C | Page 25 of 28
APPLICATIONS INFORMATION
TYPICAL OPERATING CIRCUIT
Figure 29 shows the typical operating circuit for the AD5765.
The only external components needed for this precision 16-bit
DAC are a reference voltage source, decoupling capacitors on
the supply pins and reference inputs, and an optional short-
circuit current setting resistor. Because the device incorporates
reference buffers, it eliminates the need for an external bipolar
reference and associated buffers. This leads to an overall savings
in both cost and board space.
In Figure 29, AVDD is connected to +5 V and AVSS is connected
to −5 V. In Figure 29, AGNDx is connected to REFGND.
1
2
3
4
5
6
7
8
23
22
21
18
19
20
24
17
910 11 12 13 14 15 16
32 31 30 29 28 27 26 25
AD5765
SYNC
SCLK
SDIN
SDO
D0
LDAC
CLR
D1
VOUTA
VOUTB
AGNDB
VOUTD
VOUTC
AGNDC
AGNDA
AGNDD
RSTOUT
RSTIN
DGND
DV
CC
AV
DD
PGND
AV
SS
ISCC
BIN/2sCOMP
AV
DD
AV
SS
TEMP
REFGND
NC
REFCD
REFAB
SYNC
SCLK
SDIN
SDO
LDAC
D0
D1
RSTOUT
RSTIN
BIN/2sCOMP
+5V
+5V
+5V –5V
NC = NO CONNECT
+5V –5V
VOUTA
VOUTB
VOUTC
VOUTD
100nF
100nF
100nF
10µF
100nF 100nF
100nF
10µF
10µF
10µF
10µF
ADR420
4
GND
26
VOUTVIN
+5V
100nF
10µF
07249-035
Figure 29. Typical Operating Circuit
PRECISION VOLTAGE REFERENCE SELECTION
To achieve the optimum performance from the AD5765 over its
full operating temperature range, a precision voltage reference
must be used. Thought should be given to the selection of a
precision voltage reference. The AD5765 has two reference
inputs, REFAB and REFCD. The voltages applied to the
reference inputs are used to provide a buffered positive and
negative reference for the DAC cores. Therefore, any error in
the voltage reference is reflected in the outputs of the device.
There are four possible sources of error to consider when
choosing a voltage reference for high accuracy applications:
initial accuracy, temperature coefficient of the output voltage,
long-term drift, and output voltage noise.
Initial accuracy error on the output voltage of an external refer-
ence may lead to a full-scale error in the DAC. Therefore, to
minimize these errors, a reference with low initial accuracy
error specification is preferred. Choosing a reference with an
output trim adjustment, such as the ADR430, allows a system
designer to trim system errors out by setting the reference
voltage to a voltage other than the nominal. The trim adjust-
ment can also be used at temperature to trim out any error.
Long-term drift is a measure of how much the reference output
voltage drifts over time. A reference with a tight long-term drift
specification ensures that the overall solution remains relatively
stable over its entire lifetime.
The temperature coefficient of a reference output voltage affects
INL, DNL, and TUE. A reference with a tight temperature
coefficient specification should be chosen to reduce the
dependence of the DAC output voltage on ambient conditions.
In high accuracy applications (which have a relatively low noise
budget), reference output voltage noise needs to be considered.
Choosing a reference with as low an output noise voltage as
practical for the system resolution required is important.
Precision voltage references such as the ADR420 (XFET® design)
produce low output noise in the 0.1 Hz to 10 Hz region.
However, as the circuit bandwidth increases, filtering the output
of the reference may be required to minimize the output noise.
Table 21. Some Precision References Recommended for Use with the AD5765
Part No. Initial Accuracy (mV Max) Long-Term Drift (ppm Typ) Temp Drift (ppm/°C Max) 0.1 Hz to 10 Hz Noise (µV p-p Typ)
ADR430 ±1 40 3 3.5
ADR420 ±1 50 3 1.75
AD5765 Data Sheet
Rev. C | Page 26 of 28
LAYOUT GUIDELINES
For any circuit in which accuracy is important, careful consid-
eration of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5765 is mounted should be designed so that the
analog and digital sections are separated and confined to
certain areas of the board. If the AD5765 is in a system in which
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
The AD5765 should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on each supply located as close to the
package as possible, ideally right up against the device. The
10 µF capacitors are the tantalum bead type. The 0.1 µF capa-
citor should have low effective series resistance (ESR) and low
effective series inductance (ESI) such as the common ceramic
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
The power supply lines of the AD5765 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching
signals, such as clocks, should be shielded with digital ground
to avoid radiating noise to other parts of the board and should
never be run near the reference inputs. A ground line routed
between the SDIN and SCLK lines helps reduce crosstalk
between them (this is not required on a multilayer board, which
has a separate ground plane; however, it is helpful to separate
the lines). It is essential to minimize noise on the reference
inputs because such noise couples through to the DAC output.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough on the board. A
microstrip technique is recommended but not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to the ground plane, and signal
traces are placed on the solder side.
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur.
Isocouplers provide voltage isolation in excess of 2.5 kV. The
serial loading structure of the AD5765 makes it ideal for
isolated interfaces because the number of interface lines is kept
to a minimum. Figure 30 shows a 4-channel isolated interface to
the AD5765 using an ADuM1400. For more information, go to
www.analog.com.
V
IA
SERIAL CLO CK
OUT TO SCLK
V
OA
ENCODE DECODE
V
IB
SERIAL DATA
OUT TO SDIN
V
OB
ENCODE DECODE
V
IC
SYNC OUT V
OC
ENCODE DECODE
V
ID
CONTROL OUT V
OD
ENCODE DECODE
MICRO-
CONTROLLER
ADuM1400
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
TO SYNC
TO LDAC
07249-065
Figure 30. Isolated Interface
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5765 is via a serial bus
that uses a standard protocol that is compatible with micro-
controllers and DSP processors. The communications channel
is a 3-wire (minimum) interface consisting of a clock signal, a
data signal, and a synchronization signal. The AD5765 requires
a 24-bit data-word with data valid on the falling edge of SCLK.
For all the interfaces, the DAC output update can be done
automatically when all the data is clocked in, or it can be done
under the control of LDAC. The contents of the DAC register
can be read using the readback function.
AD5765 to Blackfin DSP Interface
Figure 31 shows how the AD5765 can be interfaced to an Analog
Devices, Inc., Blackfin® DSP. The Blackfin has an integrated SPI
port that can be connected directly to the SPI pins of the AD5765
and programmable I/O pins that can be used to set the state of a
digital input such as the LDAC pin.
SPISELx
MOSI
SCK
PF10
ADSP-BF531
AD5765
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
SCLK
SDIN
SYNC
LDAC
07249-037
Figure 31. AD5765 to Blackfin Interface
Data Sheet AD5765
Rev. C | Page 27 of 28
OUTLINE DIMENSIONS
COMPLIANT TO JEDE C S TANDARDS MS-026-ABA
0.45
0.37
0.30
0.80
BSC
LEAD PITCH
7.00
BSC SQ
9.00 BS C S Q
124
25
32
8
9
17
16
1.20
MAX
0.75
0.60
0.45
1.05
1.00
0.95
0.20
0.09
0.08 M AX
COPLANARITY
SEATING
PLANE
0° M IN
7°
3.5°
0°
0.15
0.05
VIEW A
ROTAT E D 90° CCW
VIEW A
PIN 1
TOP VIEW
(PINS DOW N)
020607-A
Figure 32. 32-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 INL Temperature Range Package Description Package Option
AD5765BSUZ ± 2 LSB −40°C to +105°C 32-Lead TQFP SU-32-2
AD5765BSUZ-REEL7 ± 2 LSB −40°C to +105°C 32-Lead TQFP SU-32-2
AD5765CSUZ ± 1 LSB −40°C to +105°C 32-Lead TQFP SU-32-2
AD5765CSUZ-REEL7 ± 1 LSB −40°C to +105°C 32-Lead TQFP SU-32-2
EVAL-AD5765EBZ Evaluation Board
1 Z = RoHS Compliant Part.
