DC1051A - Linear Technology

LTC4217

4217fg

For more information www.linear.com/LTC4217

Typical applicaTion

FeaTures

applicaTions

DescripTion

2A Integrated Hot

Swap Controller

The LT C

4217 is an integrated solution for Hot Swap

applications that allows a board to be safely inserted and

removed from a live backplane. The part integrates a Hot

Swap controller, power MOSFET and current sense resistor

in a single package for small form factor applications. A

dedicated 12V version (LTC4217-12) contains preset 12V

specific thresholds, while the standard LTC4217 allows

adjustable thresholds.

The LTC4217 provides separate inrush current control and a

5% accurate 2A current limit with foldback current limiting.

The current limit threshold can be adjusted dynamically

using an external pin. Additional features include a current

monitor output that amplifies the sense resistor voltage

for ground referenced current sensing and a MOSFET

temperature monitor output. Thermal limit, overvoltage,

undervoltage and power good monitoring are also provided.

For a 5A pin compatible version, see LTC4232.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

12V, 1.5A Card Resident Application with Auto-Retry

n Small Footprint

n 33mΩ MOSFET with RSENSE

n Wide Operating Voltage Range: 2.9V to 26.5V

n Adjustable, 5% Accurate Current Limit

n Current and Temperature Monitor Outputs

n Overtemperature Protection

n Adjustable Current Limit Timer Before Fault

n Power Good and Fault Outputs

n Adjustable Inrush Current Control

n 2% Accurate Undervoltage and Overvoltage Protection

n Pin Compatible with LTC4232 (DFN Package Only)

n Available in 20-Lead TSSOP and 16-Lead

5mm × 3mm DFN Packages

n RAID Systems, Solid State Drives

n Server I/O Cards

n Industrial

Power-Up Waveforms

ADC

1µF

12V VOUT

12V

1.5A

20k

4217 TA01a

10k 330µF

VDD

OUT

ISET

GATE

GND

IMON

LTC4217DHC-12

INTVCC

TIMER

F LT

AUTO

RETRY

* TVS: DIODES INC. SMAJ17A

*VIN

10V/DIV

CONTACT

BOUNCE

IIN

0.1A/DIV

VOUT

10V/DIV

25ms/DIV 4217 TA01b

LTC4217

4217fg

For more information www.linear.com/LTC4217

LTC4217

LTC4217-12

LTC4217

SENSE

VDD

ISET

IMON

F LT

GATE

OUT

VDD

TIMER

INTVCC

GND

OUT

TOP VIEW

DHC PACKAGE

16-LEAD (5mm × 3mm) PLASTIC DFN

TJMAX = 125°C, θJA = 43°C/W

EXPOSED PAD (PIN 17) IS SENSE,

θJA = 43°C/W SOLDERED, OTHERWISE θJA = 140°C/W

FE PACKAGE

20-LEAD PLASTIC TSSOP

TOP VIEW

SENSE

VDD

TIMER

INTVCC

GND

OUT

SENSE

VDD

ISET

IMON

F LT

GATE

OUT

SENSE

TJMAX = 125°C, θJA = 38°C/W

EXPOSED PAD (PIN 21) IS SENSE,

θJA = 38°C/W SOLDERED, OTHERWISE θJA = 130°C/W

pin conFiguraTion

absoluTe MaxiMuM raTings

Supply Voltage (VDD) ................................. –0.3V to 28V

Input Voltages

FB, OV, UV ..............................................–0.3V to 12V

TIMER ................................................... –0.3V to 3.5V

SENSE .............................VDD – 10V or – 0.3V to VDD

Output Voltages

ISET, IMON ................................................. –0.3V to 3V

PG, FLT .................................................. –0.3V to 35V

OUT ............................................ –0.3V to VDD + 0.3V

INTVCC .................................................. –0.3V to 3.5V

GATE (Note 3) ........................................ –0.3V to 33V

(Notes 1, 2)

Operating Ambient Temperature Range

LTC4217C ................................................ 0°C to 70°C

LTC4217I .............................................–40°C to 85°C

LTC4217H .......................................... –40°C to 125°C

Junction Temperature (Notes 4, 5) ........................ 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

FE Package Only ............................................... 300°C

LTC4217

4217fg

For more information www.linear.com/LTC4217

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

DC Characteristics

VDD Input Supply Range l2.9 26.5 V

IDD Input Supply Current MOSFET On, No Load l1.6 3 mA

VDD(UVL) Input Supply Undervoltage Lockout VDD Rising l2.65 2.73 2.85 V

VDD(UVTH) Input Supply Undervoltage Threshold LTC4217-12, VDD Rising l9.6 9.88 10.2 V

∆VDD(UVHYST) Input Supply Undervoltage Hysteresis LTC4217-12 l520 640 760 mV

VDD(OVTH) Input Supply Overvoltage Threshold LTC4217-12, VDD Rising l14.7 15.05 15.4 V

∆VDD(OVHYST) Input Supply Overvoltage Hysteresis LTC4217-12 l183 244 305 mV

VOUT(PGTH) Output Power Good Threshold LTC4217-12, VOUT Rising l10.2 10.5 10.8 V

∆VOUT(PGHYST) Output Power Good Hysteresis LTC4217-12 l127 170 213 mV

IOUT OUT Leakage Current VOUT = VGATE = 0V, VDD = 26.5V

VOUT = VGATE = 12V, LTC4217

VOUT = VGATE = 12V, LTC4217-12

VOUT = VGATE = 12V, LTC4217H

±150

µA

dVGATE /dt GATE Pin Turn-On Ramp Rate l0.15 0.3 0.55 V/ms

RON MOSFET + Sense Resistor On-Resistance C-Grade, I-Grade

H-Grade

mΩ

ILIM(TH) Current Limit Threshold VFB = 1.23V 1.9 2 2.1 A

VFB = 1.23V l1.85 2 2.15 A

VFB = 0V l0.35 0.5 0.7 A

VFB = 1.23V, RSET = 20kΩ l0.85 1 1.17 A

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4217CDHC-12#PBF LTC4217CDHC-12#TRPBF 421712 16-Lead (5mm × 3mm) Plastic DFN 0°C to 70°C

LTC4217IDHC-12#PBF LTC4217IDHC-12#TRPBF 421712 16-Lead (5mm × 3mm) Plastic DFN –40°C to 85°C

LTC4217CDHC#PBF LTC4217CDHC#TRPBF 4217 16-Lead (5mm × 3mm) Plastic DFN 0°C to 70°C

LTC4217IDHC#PBF LTC4217IDHC#TRPBF 4217 16-Lead (5mm × 3mm) Plastic DFN –40°C to 85°C

LTC4217CFE#PBF LTC4217CFE#TRPBF LTC4217FE 20-Lead Plastic TSSOP 0°C to 70°C

LTC4217IFE#PBF LTC4217IFE#TRPBF LTC4217FE 20-Lead Plastic TSSOP –40°C to 85°C

LTC4217HFE#PBF LTC4217HFE#TRPBF LTC4217FE 20-Lead Plastic TSSOP –40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

(http://www.linear.com/product/LTC4217#orderinfo)

LTC4217

4217fg

For more information www.linear.com/LTC4217

elecTrical characTerisTics

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into pins are positive, all voltages are referenced to

GND unless otherwise specified.

Note 3: An internal clamp limits the GATE pin to a maximum of 6.5V above

OUT. Driving this pin to voltages beyond the clamp may damage the device.

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Inputs

IIN OV, UV, FB Input Current V = 1.2V, LTC4217 l0 ±1 µA

RIN OV, UV, FB Input Resistance LTC4217-12 l13 18 23 kΩ

VTH OV, UV, FB Threshold Voltage VPIN Rising l1.21 1.235 1.26 V

∆VOV(HYST) OV Hysteresis l10 20 30 mV

∆VUV(HYST) UV Hysteresis l50 80 110 mV

VUV(RTH) UV Reset Threshold Voltage VUV Falling l0.55 0.62 0.7 V

∆VFB(HYST) FB Power Good Hysteresis l10 20 30 mV

RISET ISET Internal Resistor l19 20 21 kΩ

Outputs

VOL PG, F LT Pin Output Low Voltage ISINK = 2mA

C-Grade, I-Grade

H-Grade

0.4

0.8

0.92

IOH PG, F LT Pin Input Leakage Current 30V l0 ±10 µA

VTIMER(H) TIMER Pin High Threshold VTIMER Rising l1.2 1.235 1.28 V

VTIMER(L) TIMER Pin Low Threshold VTIMER Falling l0.1 0.21 0.3 V

ITIMER(UP) TIMER Pin Pull-Up Current VTIMER = 0V l–80 –100 –120 µA

ITIMER(DN) TIMER Pin Pull-Down Current VTIMER = 1.2V l1.4 2 2.6 µA

ITIMER(RATIO) TIMER Pin Current Ratio ITIMER(DN)/ITIMER(UP) l1.6 2 2.7 %

AIMON IMON Pin Current Gain IOUT = 2A l47.5 50 52.5 µA/A

BWIMON IMON Bandwidth 250 kHz

IOFF(IMON) IMON Pin Offset Current IOUT = 132mA l0 ±7.5 µA

IGATE(UP) Gate Pull-Up Current Gate Drive On, VGATE = VOUT = 12V l–19 –24 –29 µA

IGATE(DN) Gate Pull-Down Current Gate Drive Off, VGATE = 18V, VOUT = 12V

C-Grade, I-Grade

H-Grade

190

164

250

140

400

500

µA

IGATE(FST) Gate Fast Pull-Down Current Fast Turn Off, VGATE = 18V, VOUT = 12V 140 mA

AC Characteristics

tPHL(GATE) Input High (OV), Input Low (UV) to Gate Low

Propagation Delay

VGATE < 16.5V Falling l8 10 µs

tPHL(ILIM) Short-Circuit to Gate Low VFB = 0, Step ISENSE to 1.2A,

VGATE < 16.5V Falling

l1 5 µs

tD(ON) Turn-On Delay Step VUV to 2V, VGATE > 13V l50 100 150 ms

tD(FAULT) UV Low to Clear Fault Latch Delay 1 µs

tD(CB) Circuit Breaker Filter Delay Time (Internal) VFB = 0V, Step ISENSE to 1.2A

C-Grade, I-Grade

H-Grade

1.5

1.4

2.7

tD(AUTO-RETRY) Auto-Retry Turn-On Delay (Internal) l50 100 150 ms

Note 4: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 5: TJ is calculated from the ambient temperature, TA, and power

dissipation, PD, according to the formula:

LTC4217DHC, LTC4217DHC-12: TJ = TA + (PD • 43°C/W)

LTC4217FE: TJ = TA + (PD • 38°C/W)

LTC4217

4217fg

For more information www.linear.com/LTC4217

TEMPERATURE (°C)

–50

ISET RESISTOR (kΩ)

–25 0 25

4217 G09

50 75 100

FB VOLTAGE (V)

CURRENT LIMIT VALUE (A)

0.5

1.0

1.5

2.0

2.5

0.2 0.4 0.6 0.8

4217 G07

1.0 1.2

SET

(Ω)

CURRENT LIMIT THRESHOLD VALUE (A)

0.5

1.0

1.5

2.0

2.5

10k 100k 1M

4217 G08

10M

TEMPERATURE (°C)

–50

UV HYSTERESIS (V)

0.10

0.08

0.06

0.04

–25 0 25

4217 G04

50 75 100

TEMPERATURE (°C)

–50

TIMER PULL-UP CURRENT (µA)

–110

–105

–100

–95

–90

–25 0 25

4217 G05

50 75 100

TEMPERATURE (°C)

–50

UV LOW-HIGH HRESHOLD (V)

1.234

1.232

1.230

1.228

1.226

–25 0 25

4217 G03

50 75 100

VDD (V)

1.0

(mA)

1.2

1.4

1.6

1.8

2.0

5 10 15 20

4217 G01

25 30

–40°C

25°C

85°C

ILOAD (mA)

0.5

1.5

1.0

INTVCC (V)

3.5

2.0

2.5

3.0

4217 G02

–14–12–10–8–6–4–2

VDD = 5V

VDD = 3.3V

Typical perForMance characTerisTics

IDD vs VDD

INTVCC Load Regulation

UV Low-High Threshold

vs Temperature

UV Hysteresis vs Temperature

Timer Pull-Up Current

vs Temperature

Current Limit Delay

(tPHL(ILIM) vs Overdrive)

Current Limit Threshold Foldback

Current Limit Adjustment

(IOUT vs RSET)

Internal ISET Resistor (RISET)

TA = 25°C, VDD = 12V unless otherwise noted.

OUTPUT CURRENT (A)

CURRENT LIMIT PROPAGATION DELAY (µs)

1000

100

0.1

0 10

4217 G06

2468

LTC4217

4217fg

For more information www.linear.com/LTC4217

TEMPERATURE (°C)

–50

0.9

0.8

0.7

0.6

0.5

0.4

0.3

–25 0 25

4217 G18

50 75 150125100

ISET

(V)

TEMPERATURE (°C)

–50

105

100

–25 0 25

4217 G13

50 75 100

IMON (µA)

VDD = 3.3V, 12V, 24V

ILOAD = 2A

TEMPERATURE (°C)

–50

IGATE PULL-UP (µA)

–26.0

–25.5

–25.0

–24.5

–24.0

–25 0 25

4217 G14

50 75 100

IGATE (µA)

∆VGATE (VGATE – VOUT) (V)

–5 –10 –15 –20

4217 G15

–25 –30

VDD = 12V

VDD = 3.3V

VDD (V)

6.2

6.0

5.8

5.6

5.4

5.2

5 10 15

4217 G16

20 25 30

∆VGATE (VGATE – VOUT) (V)

TEMPERATURE (°C)

–50

6.15

6.14

6.13

6.12

6.11

6.10

–25 0 25

4217 G17

50 75 100

∆VGATE (VGATE – VOUT) (V)

ILOAD (mA)

PG, FLT V

OUT

LOW (V)

2468

4217 G12

10 12

FLT

TEMPERATURE (°C)

–50

–25 0 25

4217 G10

50 75 100

RON (mΩ)

VDD = 3.3V, 12V, 24V

VDS (V)

0.1

0.01

ID (A)

0.1

1 10 100

4217 G11

TA = 25°C

MULTIPLE PULSE

DUTY CYCLE = 0.2

10s

100ms

10ms

1ms

Typical perForMance characTerisTics

RON vs VDD and Temperature

MOSFET SOA Curve

IMON vs Temperature and VDD

Gate Drive vs

Gate Pull-Up Current

PG, F LT VOUT Low vs ILOAD

TA = 25°C, VDD = 12V unless otherwise noted.

GATE Pull-Up Current

vs Temperature

Gate Drive vs VDD

Gate Drive vs Temperature

VISET vs Temperature

LTC4217

4217fg

For more information www.linear.com/LTC4217

pin FuncTions

FB: Foldback and Power Good Input. Connect this pin to

an external resistive divider from OUT for the LTC4217

(adjustable) version. The LTC4217-12 version uses a fixed

internal divider with optional external adjustment. Open the

pin if the LTC4217-12 thresholds for 12V operation are

desired. If the voltage falls below 0.6V, the current limit is

reduced using a foldback profile (see the Typical Perfor-

mance Characteristics section). If the voltage falls below

1.21V, the PG pin will pull low to indicate the power is bad.

F LT : Overcurrent Fault Indicator. Open-drain output pulls

low when an overcurrent fault has occurred and the circuit

breaker trips. For overcurrent auto-retry tie to UV pin (see

the Applications Information section for details).

GATE: Gate Drive for Internal N-channel MOSFET. An

internal 24µA current source charges the gate of the

N-channel MOSFET. At start-up the GATE pin ramps up at

a 0.3V/ms rate determined by internal circuitry. During an

undervoltage or overvoltage condition a 250µA pull-down

current turns the MOSFET off. During a short-circuit or

undervoltage lockout condition, a 140mA pull-down cur-

rent source between GATE and OUT is activated.

GND: Device Ground.

IMON: Current Monitor Output. The current in the internal

MOSFET switch is divided by 20,000 and sourced from this

pin. Placing a 20k resistor from this pin to GND creates a

0V to 2V voltage swing when current ranges from 0A to 2A.

INTVCC: Internal 3.1V Supply Decoupling Output. This pin

must have a 1µF or larger bypass capacitor. Overloading

this pin can disrupt internal operation.

ISET: Current Limit Adjustment Pin. For a 2A current limit

value open this pin. This pin is driven by a 20k resistor

in series with a voltage source. The pin voltage is used

to generate the current limit threshold. The internal 20k

resistor (RISET)) and an external resistor (RSET) between

ISET and ground create an attenuator that lowers the cur-

rent limit value. Due to circuit tolerance RSET should not be

less than 2k. In order to match the temperature variation

of the sense resistor, the voltage on this pin increases at

the same rate as the sense resistance increases. Therefore

the voltage at ISET pin is made proportional to temperature

of the MOSFET switch.

OUT: Output of Internal MOSFET Switch. Connect this pin

directly to the load. In the LTC4217-12 version, the PG

comparator monitors an internal resistive divider between

the OUT pin and GND.

OV: Overvoltage Comparator Input. Connect this pin to an

external resistive divider from VDD for the LTC4217 (adjust-

able) version. The LTC4217-12 version uses a fixed internal

divider with optional external adjustment for 12V operation.

Open the pin if the LTC4217-12 thresholds are desired. If

the voltage at this pin rises above 1.235V, an overvoltage

is detected and the switch turns off. Tie to GND if unused.

PG: Power Good Indicator. Open-drain output pulls low

when the FB pin drops below 1.21V indicating the power is

bad. If the FB pin rises above 1.23V and the GATE to OUT

voltage exceeds 4.2V, the open-drain pull-down releases

the PG pin to go high.

SENSE: Current Sense Node and MOSFET Drain. The

current limit circuit controls the GATE pin to limit the

sense voltage between the VDD and SENSE pins to 15mV

(2A) or less depending on the voltage at the FB pin. The

exposed pad on DHC and FE packages are connected to

SENSE and must be soldered to an electrically isolated

printed circuit board trace to properly transfer the heat

out of the package.

TIMER: Timer Input. Connect a capacitor between this pin

and ground to set a 12ms/µF duration for current limit

before the switch is turned off. If the UV pin is toggled

low while the MOSFET switch is off, the switch will turn

on again following a cooldown time of 518ms/µF duration.

Tie this pin to INTVCC for a fixed 2ms overcurrent delay

and 100ms auto-retry time.

UV: Undervoltage Comparator Input. Tie high if unused.

Connect this pin to an external resistive divider from VDD

for the LTC4217 (adjustable) version. The LTC4217-12

version drives the UV pin with an internal resistive divider

from VDD. Open the pin if the preset LTC4217-12 thresholds

for 12V operation are desired. If the UV pin voltage falls

below 1.15V, an undervoltage is detected and the switch

turns off. Pulling this pin below 0.62V resets the overcur-

rent fault and allows the switch to turn back on (see the

Applications Information section for details). If overcurrent

auto-retry is desired then tie this pin to the F LT pin.

VDD: Supply Voltage and Current Sense Input. This pin

has an undervoltage lockout threshold of 2.73V.

LTC4217

4217fg

For more information www.linear.com/LTC4217

FuncTional DiagraM

4217 BD

RISET

20k

VDD

OUT

GND

IMON

INTVCC

100µA

TIMER

F LT

–ISET

GATE

SENSE

(EXPOSED PAD)

CLAMP

0.6V POSITIVE

TEMPERATURE

COEFFICIENT

REFERENCE

INTERNAL 25mΩ

MOSFET

INTERNAL 7.5mΩ

SENSE RESISTOR

CHARGE

PUMP

AND GATE

DRIVER

f = 2MHz

OUT

3.1V

GEN

LOGIC

INRUSHCS

0.3V/ms

FOLDBACK

0.6V

2.65V

1.235V

+–

–

1.235V

–

0.2V

–

TM1

1.235V –

TM2

0.62V

–

RST

VDD

2.73V +

–

UVLO1

1.235V –

2µA

–

UVLO2

VDD

OUT

150k

20k

*LTC4217-12 (DFN) ONLY

140k

20k

224k

20k

6.15V

LTC4217

4217fg

For more information www.linear.com/LTC4217

operaTion

The Functional Diagram displays the main circuits of the

device. The LTC4217 is designed to turn a board’s supply

voltage on and off in a controlled manner allowing the board

to be safely inserted and removed from a live backplane.

The LTC4217 includes a 25mΩ MOSFET and a 7.5mΩ

current sense resistor. During normal operation, the charge

pump and gate driver turn on the pass MOSFET’s gate to

provide power to the load. The inrush current control is

accomplished by the INRUSH circuit. This circuit limits

the GATE ramp rate to 0.3V/ms and hence controls the

voltage ramp rate of the output capacitor.

The current sense (CS) amplifier monitors the load current

using the voltage sensed across the current sense resistor.

The CS amplifier limits the current in the load by reduc-

ing the GATE-to-OUT voltage in an active control loop. It

is simple to adjust the current limit threshold using the

current limit adjustment (ISET) pin. This allows a different

threshold during other times such as start-up.

A short circuit on the output to ground causes significant

power dissipation during active current limiting. To limit

this power, the foldback amplifier reduces the current limit

value from 2A to 0.5A in a linear manner as the FB pin

drops below 0.6V (see the Typical Performance Charac-

teristics section).

If an overcurrent condition persists, the TIMER pin ramps

up with a 100µA current source until the pin voltage exceeds

1.235V (comparator TM2). This indicates to the logic that

it is time to turn off the pass MOSFET to prevent overheat-

ing. At this point the TIMER pin ramps down using the

2µA current source until the voltage drops below 0.21V

(Comparator TM1) which tells the logic to start an internal

100ms timer. At this point, the pass transistor has cooled

and it is safe to turn it on again. It is suitable for many

applications to use an internal 2ms overcurrent timer with

a 100ms cooldown period. Tying the TIMER pin to INTVCC

sets this default timing. Latchoff is the normal operating

condition following overcurrent turnoff. Retry is initiated

by pulling the UV pin low for a minimum of 1µs then high.

Auto retry is implemented by tying the F LT to the UV pin.

The fixed 12V version, LTC4217-12, uses two separate

internal dividers from VDD to drive the UV and OV pins.

This version also features a divider from OUT to drive the

FB pin. The LTC4217-12 is available in a DFN package

while the LTC4217 (adjustable version) is in a DFN and

TSSOP packages.

The output voltage is monitored using the FB pin and the

PG comparator to determine if the power is available for

the load. The power good condition is signaled by the PG

pin using an open-drain pull-down transistor.

The Functional Diagram also shows the monitoring blocks

of the LTC4217. The two comparators on the left side

include the UV and OV comparators. These comparators

determine if the external conditions are valid prior to turning

on the MOSFET. But first the undervoltage lockout circuits

UVLO1 and UVLO2 must validate the input supply and

the internally generated 3.1V supply (INTVCC) and gener-

ate the power up initialization to the logic circuits. If the

external conditions remain valid for 100ms the MOSFET

is allowed to turn on.

Other features include MOSFET current and temperature

monitoring. The current monitor (CM) outputs a current

proportional to the sense resistor current. This current can

drive an external resistor or other circuits for monitoring

purposes. A voltage proportional to the MOSFET tempera-

ture is output to the ISET pin. The MOSFET is protected by

a thermal shutdown circuit.

LTC4217

4217fg

For more information www.linear.com/LTC4217

INRUSH circuit that maintains a constant slope of GATE

voltage versus time (Figure 2). The voltage at the GATE

pin rises with a slope of 0.3[V/ms] and the supply inrush

current is set at:

IINRUSH = CL • 0.3[V/ms]

Figure 2. Supply Turn-On

Figure 1. 0.8A, 12V Card Resident Application

Turn-On Sequence

Several conditions must be present before the internal

pass MOSFET can be turned on. First the supply VDD must

exceed its undervoltage lockout level. Next the internally

generated supply INTVCC must cross its 2.65V undervolt-

age threshold. This generates a 25µs power-on-reset pulse

which clears the fault register and initializes internal latches.

After the power-on-reset pulse, the LTC4217 will go

through the following sequence. First, the UV and OV pins

must indicate that the input voltage is within the accept-

able range. All of these conditions must be satisfied for

the duration of 100ms to ensure that any contact bounce

during the insertion has ended.

The MOSFET is turned on by charging up the GATE with

a charge pump generated 24µA current source whose

value is adjusted by shunting a portion of the pull-up cur-

rent to ground. The charging current is controlled by the

t1 t2

SLOPE = 0.3[V/ms]

GATE

OUT

VDD + 6.15V

VDD

4217 F02

150k

20k

ADC

226k

1µF

20k

12V

4217 F01

10k

0.1µF

330µF

VOUT

12V

0.8A

VDD

OUT

GND

IMON

RSET

20k

RMON

20k

ISET

CGATE

0.1µF

RGATE

100k

GATE

LTC4217FE

INTVCC

TIMER

F LT

140k

20k

Z1* CCOMP

3.3nF

* TVS Z1: DIODES INC. SMAJ17A

UV = 9.88V

OV = 15.2V

PG = 10.5V

applicaTions inForMaTion

The typical LTC4217 application is in a high availability

system that uses a positive voltage supply to distribute

power to individual cards. A complete application circuit

is shown in Figure 1. External component selection is

discussed in detail in the following sections.

This gate slope is designed to charge up a 1000µF capaci-

tor to 12V in 40ms, with an inrush current of 300mA. This

allows the inrush current to stay under the current limit

threshold (500mA) for capacitors less than 1000µF. In-

cluded in the Typical Performance Characteristics section

is a graph of the Safe Operating Area for the MOSFET. It

is evident from this graph that the power dissipation at

12V, 300mA for 40ms is in the safe region.

Adding the RGATE, CGATE, and CCOMP network on the GATE

pin will lower the inrush current below the default value

set by the INRUSH circuit. The GATE is charged with an

24µA current source (when INRUSH circuit is not driving

the GATE). The voltage at the GATE pin rises with a slope

equal to 24µA/CGATE and the supply inrush current is set at:

IINRUSH =

GATE

•24µA

When the GATE voltage reaches the MOSFET threshold

voltage, the switch begins to turn on and the OUT volt-

age follows the GATE voltage as it increases. Once OUT

reaches VDD, the GATE will ramp up until clamped by the

6.15V Zener between GATE and OUT.

LTC4217

4217fg

For more information www.linear.com/LTC4217

applicaTions inForMaTion

As the OUT voltage rises, so will the FB pin which is moni-

toring it. Once the FB pin crosses its 1.235V threshold

and the GATE to OUT voltage exceeds 4.2V, the PG pin

will cease to pull low and indicate that the power is good.

Parasitic MOSFET Oscillation

When the N-channel MOSFET ramps up the output dur-

ing power-up it operates as a source follower. The source

follower configuration may self-oscillate in the range of

25kHz to 300kHz when the load capacitance is less than

10µF, especially if the wiring inductance from the supply

to the VDD pin is greater than 3µH. The possibility of oscil-

lation will increase as the load current (during power-up)

increases. There are two ways to prevent this type of

oscillation. The simplest way is to avoid load capacitances

below 10µF. For wiring inductance larger than 20µH, the

minimum load capacitance may extend to 100µF. A second

choice is to connect an external gate capacitor CP >1.5nF

as shown in Figure 3.

Figure 3. Compensation for Small CLOAD

4217 F03

LTC4217

OPTIONAL

RC TO LOWER

INRUSH CURRENT

GATE

2.2nF

Turn-Off Sequence

The switch can be turned off by a variety of conditions. A

normal turn-off is initiated by the UV pin going below its

1.235V threshold. Additionally, several fault conditions

will turn off the switch. These include an input overvolt-

age (OV pin), overcurrent circuit breaker (SENSE pin) or

over temperature. Normally the switch is turned off with

a 250µA current pulling down the GATE pin to ground.

With the switch turned off, the OUT voltage drops which

pulls the FB pin below its threshold. PG then pulls low to

indicate output power is no longer good.

If VDD drops below 2.65V for greater than 5µs or INTVCC

drops below 2.5V for greater than 1µs, a fast shutdown

of the switch is initiated. The GATE is pulled down with a

170mA current to the OUT pin.

Overcurrent Fault

The LTC4217 features an adjustable current limit with

foldback that protects against short-circuits and excessive

load current. To prevent excessive power dissipation in the

switch during active current limit, the available current is

reduced as a function of the output voltage sensed by the

FB pin. A graph in the Typical Performance Characteristics

curves shows the Current Limit Threshold Foldback.

An overcurrent fault occurs when the current limit circuitry

has been engaged for longer than the timeout delay set

by the TIMER. Current limiting begins when the MOSFET

current reaches 0.5A to 2A (depending on the foldback).

The GATE pin is then brought down with a 140mA GATE-

to-OUT current. The voltage on the GATE is regulated in

order to limit the current to less than 2A. At this point, a

circuit breaker time delay starts by charging the external

timing capacitor with a 100µA pull-up current from the

TIMER pin. If the TIMER pin reaches its 1.235V threshold,

the internal switch turns off (with a 250µA current from

GATE to ground). Included in the Typical Performance

Characteristics curves is a graph of the Safe Operating

Area for the MOSFET. From this graph one can determine

the MOSFET’s maximum time in current limit for a given

output power.

Tying the TIMER pin to INTVCC will force the part to use

the internally generated (circuit breaker) delay of 2ms.

In either case the F LT pin is pulled low to indicate an

overcurrent fault has turned off the pass MOSFET. For a

given circuit breaker time delay, the equation for setting

the timing capacitor’s value is as follows:

CT = tCB • 0.083[µF/ms]

After the switch is turned off, the TIMER pin begins dis-

charging the timing capacitor with a 2µA pull-down current.

LTC4217

4217fg

For more information www.linear.com/LTC4217

applicaTions inForMaTion

When the TIMER pin reaches its 0.21V threshold, an in-

ternal 100ms timer is started. After the 100ms delay, the

switch is allowed to turn on again if the overcurrent fault

latch has been cleared. Bringing the UV pin below 0.6V

for a minimum of 1µs and then high will clear the fault

latch. If the TIMER pin is tied to INTVCC then the switch is

allowed to turn on again (after an internal 100ms delay),

if the overcurrent fault latch is cleared.

Tying the F LT pin to the UV pin allows the part to self-clear

the fault and turn the MOSFET on as soon as TIMER pin

has ramped below 0.21V. In this auto-retry mode the

LTC4217 repeatedly tries to turn on after an overcurrent

at a period determined by the capacitor on the TIMER pin.

The auto-retry mode also functions when the TIMER pin

is tied to INTVCC.

The waveform in Figure 4 shows how the output latches

off following a short-circuit. The current in the MOSFET

is 0.5A as the timer ramps up.

Figure 4. Short-Circuit Waveform

IOUT

1A/DIV

VOUT

10V/DIV

∆VGATE

10V/DIV

TIMER

2V/DIV

1ms/DIV 4217 F04

An external RSET resistor placed between the ISET pin and

ground forms a resistive divider with the internal 20k RISET

sourcing resistor. The divider acts to lower the voltage at

the ISET pin and therefore lower the current limit threshold.

The overall current limit threshold precision is reduced to

±16% when using a 20k resistor to halve the threshold.

Using a switch (connected to ground) in series with RSET

allows the active current limit to change only when the

switch is closed. This feature can be used to program a

reduced running current while the maximum current limit

is used at start-up.

Monitor MOSFET Temperature

The voltage at the ISET pin increases linearly with increas-

ing temperature. The temperature profile of the ISET pin is

shown in the Typical Performance Characteristics section.

Using a comparator or ADC to measure the ISET voltage

provides an indicator of the MOSFET temperature.

The ISET voltage follows the formula:

ISET =

SET

RSET +RISET

•(T +273°C) •2.093[mV/°C]

The MOSFET temperature is calculated using RISET of 20k.

SET +

20k) •V

ISET

SET

•2.093[mV/°C] −273°C

when RSET is not present, T becomes:

ISET

2.093[mV/°C]

−273°C

There is an overtemperature circuit in the LTC4217 that

monitors an internal voltage similar to the ISET pin voltage.

When the die temperature exceeds 145°C the circuit turns

off the MOSFET until the temperature drops to 125°C.

Monitor MOSFET Current

The current in the MOSFET passes through an internal

7.5mΩ sense resistor. The voltage on the sense resistor is

converted to a current that is sourced out of the IMON pin.

The gain of ISENSE amplifier is 50µA/A from IMON for 1A of

MOSFET current. This output current can be converted to

a voltage using an external resistor to drive a comparator

Current Limit Adjustment

The default value of the active current limit is 2A. The

current limit threshold can be adjusted lower by placing

a resistor between the ISET pin and ground. As shown in

the Functional Block Diagram the voltage at the ISET pin

(via the clamp circuit) sets the CS amplifier’s built-in offset

voltage. This offset voltage directly determines the active

current limit value. With the ISET pin open, the voltage at

the ISET pin is determined by a positive temperature co-

efficient reference. This voltage is set to 0.618V at room

temperature which corresponds to a 2A current limit at

room temperature.

LTC4217

4217fg

For more information www.linear.com/LTC4217

Once the PG comparator is high the GATE pin voltage is

monitored with respect to the OUT pin. Once the GATE

minus OUT voltage exceeds 4.2V the PG pin goes high.

This indicates to the system that it is safe to load the OUT

pin while the MOSFET is completely turned “on”. The PG

pin goes low when the GATE is commanded off (using

the UV, OV or SENSE pins) or when the PG comparator

drives low.

12V Fixed Version

In the LTC4217-12 the UV, OV and FB pins are driven by

internal dividers which may need to be filtered to prevent

false faults. By placing a bypass capacitor on these pins

the faults are delayed by the RC time constant. Use the

RIN value from the electrical characteristics table for this

calculation.

In cases where the fixed thresholds need a slight adjust-

ment, placing a resistor from the UV or OV pins to VDD

or GND will adjust the threshold up or down. Likewise

placing a resistor between FB pin to OUT or GND adjusts

the threshold. Again use the RIN value from the electrical

characteristics table for this calculation.

An example in Figure 5 raises the UV turn-on voltage from

9.88V to 10.5V. Increasing the UV level requires adding a

resistor between UV and ground. The resistor, RSHUNT1, can

be calculated using electrical table parameters as follows:

RSHUNT1 =

( )

•V

OLD

VNEW – VOLD

( )

=18k •9.88V

10.5V – 9.88V

( )

=287k

applicaTions inForMaTion

or ADC. The voltage compliance for the IMON pin is from

0V to INTVCC – 0.7V.

A microcontroller with a built-in comparator can build a

simple integrating single-slope ADC by resetting a capaci-

tor that is charged with this current. When the capacitor

voltage trips the comparator and the capacitor is reset, a

timer is started. The time between resets will indicate the

MOSFET current.

Monitor OV and UV Faults

Protecting the load from an overvoltage condition is the

main function of the OV pin. In the LTC4217-12, an in-

ternal resistive divider (driving the OV pin) connects to a

comparator to turn off the MOSFET when the VDD voltage

exceeds 15.05V. If the VDD pin subsequently falls back

below 14.8V, the switch will be allowed to turn on im-

mediately. In the LTC4217 the OV pin threshold is 1.235V

when rising, and 1.215V when falling out of overvoltage.

The UV pin functions as an undervoltage protection pin or

as an “ON” pin. In the LTC4217-12 the MOSFET turns off

when VDD falls below 9.23V. If the VDD pin subsequently

rises above 9.88V for 100ms, the switch will be allowed

to turn on again. The LTC4217 UV turn-on/off thresholds

are 1.235V (rising) and 1.115V (falling).

In the cases of an undervoltage or overvoltage the MOSFET

turns off and there is indication on the PG status pin. When

the overvoltage is removed the MOSFET’s gate ramps up

immediately at the rate determined by the INRUSH block.

Power Good Indication

In addition to setting the foldback current limit threshold,

the FB pin is used to determine a power good condition.

The LTC4217-12 uses an internal resistive divider on the

OUT pin to drive the FB pin. The PG comparator indicates

logic high when OUT pin rises above 10.5V. If the OUT pin

subsequently falls below 10.3V the comparator toggles

low. On the LTC4217 the PG comparator drives high when

the FB pin rises above 1.235V and low when falls below

1.215V. Figure 5. Adjusting LTC4217-12 Thresholds

4217 F05

LTC4217-12

RSHUNT1

RSHUNT2

VDD

LTC4217

4217fg

For more information www.linear.com/LTC4217

applicaTions inForMaTion

In this same figure the OV threshold is lowered from

15.05V to 13.5V. Decreasing the OV threshold requires

adding a resistor between VDD and OV. This resistor can

be calculated as follows:

RSHUNT2 =RIN

( )

•VOLD

VTH

( )

VNEW – VOV TH

( )

VOLD – V

NEW

( )

⎛

⎝

⎜

⎞

⎠

⎟

⎟=

18k•15.05V

1.235V

13.5V–1.235V

( )

15.05V–13.5V

( )

⎛

⎝

⎜

⎞

⎠

⎟

⎟=1.736M

Use the equation for RSHUNT1 for increasing the OV and

FB thresholds. Likewise use the equation for RSHUNT2 for

decreasing the UV and FB thresholds.

Design Example

Consider the following design example (Figure 6): VIN =

12V, IMAX = 2A. IINRUSH = 100mA, CL = 330µF, VUVON =

9.88V, VOVOFF = 15.05V, VPGTHRESHOLD = 10.5V. A current

limit fault triggers an automatic restart of the power-up

sequence.

The inrush current is defined by the current required to

charge the output capacitor using the fixed 0.3V/ms GATE

charge-up rate. The inrush current is defined as:

IINRUSH = CL • 0.3[V/ms] = 330µF • 0.3[V/ms] = 100mA

As mentioned previously the charge-up time is the out-

put voltage (12V) divided by the output rate of 0.3V/ms

resulting in 40ms. The peak power dissipation of 12V at

100mA (or 1.2W) is within the SOA of the pass MOSFET

for 40ms (see MOSFET SOA curve in the Typical Perfor-

mance Characteristics section).

Next the power dissipated in the MOSFET during overcur-

rent must be limited. The active current limit uses a timer

to prevent excessive energy dissipation in the MOSFET

The worst-case power dissipation occurs when the volt-

age versus current profile of the foldback current limit is

at the maximum. This occurs when the current is 2A and

the voltage is one half of the VIN or 6V. See the Current

Limit Threshold Foldback in the Typical Performance Char-

acteristics section to view this profile. In order to survive

12W, the MOSFET SOA dictates a maximum time of 10ms

(see SOA graph). Use the internal 2ms timer invoked by

tying the TIMER pin to INTVCC. After the 2ms timeout the

F LT pin needs to pull-down on the UV pin to restart the

power-up sequence.

Since the default values for overvoltage, undervoltage and

power good thresholds for the 12V fixed version match

the requirements, no external components are required

for the UV, OV and FB pins.

The final schematic in Figure 6 results in very few external

components. The pull-up resistor, R7, connects to the PG

pin while the 20k (RMON) converts the IMON current to a

voltage at a ratio:

VIMON = 50[µA/A] • 20k • IOUT = 1[V/A] • IOUT

In addition there is a 1µF bypass (C1) on the INTVCC pin.

Figure 6. 1.5A, 12V Card Resident Application

12V VOUT

12V

1.5A

RMON

20k

4217 F06

330µF

VDD

OUT

GATE

ISET

GND

IMON

LTC4217-12DHC

INTVCC

TIMER

F LT

10k

Z1*

1µF

*TVS Z1: DIODES INC. SMAJ17A

ADC

UV = 9.88V

OV = 15.05V

PG = 10.5V

LTC4217

4217fg

For more information www.linear.com/LTC4217

applicaTions inForMaTion

Layout Considerations

In Hot Swap applications where load currents can be 2A,

narrow PCB tracks exhibit more resistance than wider tracks

and operate at elevated temperatures. The minimum trace

width for 1oz copper foil is 0.02" per amp to make sure

Figure 8. 3.3V, 1.5A Card Resident Application

4217 F07

HEAT SINK

VIA TO

SINK

GND

OUTVDD

Figure 7. Recommended Layout

the trace stays at a reasonable temperature. Using 0.03"

per amp or wider is recommended. Note that 1oz copper

exhibits a sheet resistance of about 0.5mΩ/square. Small

resistances add up quickly in high current applications.

There are two VDD pins on opposite sides of the package

that connect to the sense resistor and MOSFET. The PCB

layout should be balanced and symmetrical to each VDD

pin to balance current in the MOSFET bond wires. Figure 7

shows a recommended layout for the LTC4217.

Although the MOSFET is self protected from overtem-

perature, it is recommended to solder the backside of the

package to a copper trace to provide a good heat sink. Note

that the backside is connected to the SENSE pin and can-

not be soldered to the ground plane. During normal loads

the power dissipated in the MOSFET is as high as 0.23W.

A 10mm × 10mm area of 1oz copper should be sufficient.

This area of copper can be divided in many layers.

It is also important to put C1, the bypass capacitor for

the INTVCC pin as close as possible between the INTVCC

and GND.

Additional Applications

The LTC4217 has a wide operating range from 2.9V to

26.5V. The UV, OV and PG thresholds are set with few

resistors. All other functions are independent of supply

voltage.

Figure 8 shows a 3.3V application with a UV threshold of

2.87V, an OV threshold of 3.77V and a PG threshold of

3.05V. The last page includes a 24V application with a UV

threshold of 19.9V, an OV threshold of 26.3V and a PG

threshold of 20.75V.

In addition to Hot Swap

applications, the LTC4217 also

functions as a backplane resident switch for removable

cards (see Figure 9).

14.7k

10k

17.4k

ADC

3.16k

10k

3.3V

RMON

20k

4217 F08

10k

100µF

VDD

OUT

GND

IMON

LTC4217FE

INTVCC

TIMER

F LT

VOUT

3.3V

1.5A

Z1*

1µF

*TVS Z1: DIODES INC. SMAJ17A

GATE

ISET

UV = 2.87V

OV = 3.77V

PG = 3.05V

LTC4217

4217fg

For more information www.linear.com/LTC4217

applicaTions inForMaTion

150k

20k

ADC

1µF RMON

20k

4217 F09

VDD

OUT

GND

IMON

ISET

GATE

LTC4217DHC

INTVCC

TIMER

F LT

VOUT

12V

10k

226k

20k

12V

20k R3

140k

LOAD

*TVS Z1: DIODES INC. SMAJ17A

Z1*

UV = 9.88V

OV = 15.2V

PG = 10.5V

Figure 9. 12V, 2A Backplane Resident Application with Insertion Activated Turn-On

LTC4217

4217fg

For more information www.linear.com/LTC4217

3.00 ±0.10

(2 SIDES)

5.00 ±0.10

(2 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC

PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 ±0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ±0.10

(2 SIDES)

0.75 ±0.05

R = 0.115

TYP

R = 0.20

TYP

4.40 ±0.10

(2 SIDES)

169

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DHC16) DFN 1103

0.25 ±0.05

PIN 1

NOTCH

0.50 BSC

4.40 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65 ±0.05

(2 SIDES)2.20 ±0.05

0.50 BSC

0.65 ±0.05

3.50 ±0.05

PACKAGE

OUTLINE

0.25 ± 0.05

DHC Package

16-Lead Plastic DFN (5mm × 3mm)

(Reference LTC DWG # 05-08-1706 Rev Ø)

package DescripTion

Please refer to http://www.linear.com/product/LTC4217#packaging for the most recent package drawings.

LTC4217

4217fg

For more information www.linear.com/LTC4217

FE20 (CA) TSSOP REV K 0913

0.09 – 0.20

(.0035 – .0079)

0° – 8°

0.25

REF

RECOMMENDED SOLDER PAD LAYOUT

0.50 – 0.75

(.020 – .030)

4.30 – 4.50*

(.169 – .177)

1 3 4 5678 9 10

DETAIL A

111214 13

6.40 – 6.60*

(.252 – .260)

4.95

(.195)

2.74

(.108)

20 1918 17 16 15

1.20

(.047)

MAX

0.05 – 0.15

(.002 – .006)

0.65

(.0256)

BSC 0.195 – 0.30

(.0077 – .0118)

TYP

2.74

(.108)

0.45 ±0.05

0.65 BSC

4.50 ±0.10

6.60 ±0.10

1.05 ±0.10

6.07

(.239)

6.07

(.239)

4.95

(.195)

MILLIMETERS

(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

SEE NOTE 4

4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

6.40

(.252)

BSC

1.98

(.078)

REF

FE Package

20-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663 Rev K)

Exposed Pad Variation CA

0.56

(.022)

REF

DETAIL A IS THE PART OF

THE LEAD FRAME FEATURE

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

package DescripTion

Please refer to http://www.linear.com/product/LTC4217#packaging for the most recent package drawings.

LTC4217

4217fg

For more information www.linear.com/LTC4217

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER

C 12/09 Revise Features, Description and Typical Application

Revise Absolute Maximum Ratings Storage Temperature Range and Pin Configuration

Revise Electrical Characteristics

Revise Graph G11

Update Pin Functions

Update Functional Diagram

Update Operation Section

Revise Figure 1 and Update Values and Equation in Applications Information Section

3, 4

10-12, 14

D 1/11 Added H-grade to Absolute Maximum Ratings, Order Information, and Electrical Characteristics sections. 2-4

E 6/11 Revised RISET in the Electrical Characteristics section. 4

F 02/16 Typical Application: Added SMAJ22A; increased INTVCC capacitor to 1µF

Raised IGATE(DN) maxima from 340µA to 400µA (C-, I-grade) and from 355µA to 500µA (H-grade)

Updated TPCs G08, G11

Increased bypass capacitance on INTVCC to 1µF from 0.1µF

ISET Pin Function: Recommended minimum resistor value to be 2k

Figure 1: Added Z1, CCOMP; updated C1, R1, RGATE

Figures 6, 8: Added Z1; updated C1 to 1µF

Added Figure 9

5, 6

Multiple

14, 15

G 04/16 Changed TVS to SMAJ17A in application circuits

Clarified that operating temperature range refers to ambient

Added BWIMON and tD(FAULT) specifications

Updated INTVCC and ISET pin functions

Added equations to calculate MOSFET temperature

1, 10, 14, 15, 16

(Revision history begins at Rev C)

LTC4217

4217fg

For more information www.linear.com/LTC4217

LT 0416 REV G • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC4217

relaTeD parTs

Typical applicaTion

24V, 1.5A Card Resident Application with Auto-Retry

PART NUMBER DESCRIPTION COMMENTS

LTC4210 Single Channel, Hot Swap Controller Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6

LTC4211 Single Channel, Hot Swap Controller Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10

LTC4212 Single Channel, Hot Swap Controller Operates from 2.5V to 16.5V, Power-Up Timeout, MSOP-10

LTC4214 Negative Voltage, Hot Swap Controller Operates from 0V to –16V, MSOP-10

LTC4215 Hot Swap Controller with I2C Compatible

Monitoring

Operates from 2.9V to 15V, 8-Bit ADC Monitors Current and Voltage

LTC4218 Single Channel, Hot Swap Controller Operates from 2.9V to 26.5V, Adjustable Current Limit, SSOP-16, and DFN-16

LT4220 Positive and Negative Voltage, Dual

Channels, Hot Swap Controller

Operates from ±2.7V to ±16.5V, SSOP-16

LTC4221 Dual Hot Swap Controller/Sequencer Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16

LTC4230 Triple Channels, Hot Swap Controller Operates from 1.7V to 16.5V, Multifunction Current Control, SSOP-20

LTC4232 5A Integrated Hot Swap Controller Operates from 2.9V to 15V, Adjustable 10% Current Limit

LTC4233 10A Guaranteed SOA Hot Swap Controller Operates from 2.9V to 15V, Adjustable 11% Current Limit

LTC4234 20A Guaranteed SOA Hot Swap Controller Operates from 2.9V to 15V, Adjustable 11% Current Limit

158k

10k

200k

ADC

3.24k

10k

24V

VOUT

24V

1.5A

20k

*TVS: DIODES INC. SMAJ24A 4217 TA02

10k

100µF

VDD

OUT

GND

IMON

LTC4217FE

INTVCC

TIMER

F LT

1µF

GATE

ISET

UV = 19.9V

OV = 26.3V

PG = 20.75V