Description
The A8582 is an adjustable frequency, high output current,
PWM regulator that integrates a low resistance, high-side,
N-channel MOSFET. The A8582 incorporates current-mode
control to provide simple compensation, excellent loop
stability, and fast transient response. The A8582 utilizes
external compensation to accommodate a wide range of power
components to optimize transient response without sacrificing
stability.
The A8582 regulates input voltages from 4.7 to 36 V, down to
output voltages as low as 0.8 V, and is able to supply at least
2.0 A of load current. The A8582 features include an externally
adjustable switching frequency, an externally set soft start
time to minimize inrush currents, an EN/SYNC input to either
enable VOUT and/or synchronize the PWM switching
frequency, and a Power OK (POK) output to indicate when
VOUT is within regulation. The A8582 only turns on the
lower FET to charge the boot capacitor when needed, not at
A8582-DS, Rev. 12
Features and Benefits
Wide operating voltage range: 4.7 to 36 V
UVLO stop threshold is at 3.8 V (typ)
Supports 40 V input for surge and load dump testing
Capable of at least 2.0 A steady-state output current
Adjustable output voltage as low as 0.8 V
Internal 70 m high-side switching MOSFET
Adjustable switching frequency, fSW: 0.25 to 2.4 MHz
Synchronization to external clock: 1.2 × fSW to 1.5 × fSW
Sleep mode supply current less then 3 A
Soft start time externally set via the SS pin
Very low no-load current, typically 3.5 mA
Pre-bias startup compatible
Power OK (POK) output
Pulse-by-pulse current limiting (OCP)
Hiccup mode short-circuit protection (HIC)
Overtemperature protection (TSD)
Overvoltage protection (OVP)
Missing asynchronous diode (D1) protection
Open-circuit and adjacent pin short-circuit tolerant
Short-to-ground tolerant at every pin
Externally adjustable compensation
Stable with ceramic output capacitors
W ide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
Package: 16-pin TSSOP (suffix LP) Applications:
Typical Application
Not to scale
Figure 1. Application schematic, at VIN 5 to 16 V, 3.3 VOUT , at 2 MHz
A8582
Continued on the next page…
GPS/infotainment
Automobile audio
Home audio
Network and telecom
RFB2
5.23 k
RFB1
16.5 k
CSS
22 nF
CIN1
3.3 F
50 V
A8582
VIN
2
SS
4
EN/SY NC
7
FSET
8
VIN
1
VIN
3
GND
5
POK 6
FB 9
FBX 10
COMP
PAD
11
GND
12 BOOT 14
SW 15
SW 16
RFSET
11.5 k
V
IN
POK
D1
3 A
/40 V
SMA
RZ
15.4 k
RS2
5.23 k
CBOOT
100 nF
CP
10 pF
CZ
820 pF
CIN2
Empty
50 V
L
O
2.2 H
RPU
2 k
RS1
16.5 k
CO1
10 F
16 V
3.3V
VOU
T
CFBX
120 pF
W ide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
A8582
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Absolute Maximum Ratings1
Characteristic Symbol Notes Rating Unit
VIN Pin to GND VIN –0.3 to 40 V
SW Pin to GND2VSW
Continuous –0.3 to VIN + 0.3 V
Single pulse, tW < 50 ns –1.0 to VIN + 5.0 V
BOOT Pin Above SW Pin VBOOT
VSW – 0.3 to
VSW + 7.0 V
SS Pin VSS –0.3 to VIN + 0.3 V
All Other Pins VI–0.3 to 5.5 V
Operating Ambient Temperature TAK temperature range for automotive –40 to 125 ºC
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
1Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical
Characteristics table is not implied. Exposure to absolute-maximum–rated conditions for extended periods may affect device reliability.
2SW has internal clamp diodes to GND and VIN. Applications that forward bias these diodes should take care not to exceed the IC
package power dissipation limits.
Selection Guide
Part Number Packing
A8582KLPTR-T 4000 pieces per 13-in. reel
Thermal Characteristics
Characteristic Symbol Test Conditions* Value Unit
Package Thermal Resistance RJA On 4-layer PCB based on JEDEC standard 34 ºC/W
*Additional thermal information available on the Allegro website
every PWM cycle. This improves light load efficiency and provides
no-load currents as low as 4 mA at 2 MHz. The sleep mode current
of the A8582 control circuitry is less than 3 A.
Protection features include VIN undervoltage lockout (UVLO),
pulse-by-pulse overcurrent protection (OCP), hiccup mode short-
circuit protection (HIC), overvoltage protection (OVP), and thermal
shutdown (TSD). In addition, the A8582 provides unique missing
diode (D1) protection, open-circuit, adjacent pin short-circuit,
and short-to-ground protection at every pin to satisfy the most
demanding applications.
The A8582 device is available in a 16-pin TSSOP package with
exposed pad for enhanced thermal dissipation. It is lead (Pb) free,
with 100% matte tin leadframe plating.
Description (continued)
Table of Contents
Specifications 2
Functional Block Diagram 3
Pin-out Diagram and Terminal List 4
Typical Characteristic Performance 8
Functional Description 10
Overview 10
Protection Features 14
Application Information 16
Design and Component Selection 16
Package Outline Drawing 30
W ide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
A8582
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Block Diagram
FSET
VREF 0.8 V
VREF
tOFF(MIN)
70
m
10
90%×VREF
86%×VREF
Current Sense
Amp
OCP
VREG
POR
VREG
BS UVLO
FBOK
BOOT
– SW
VSS
400 mV
PWM
Comp
Adj
Adj Reset
DOM
PWM
Ramp
Offset
300 mV
PWM Clk
fSW
SYNC
Regulator
EN
FBOK
Sleep
EN/SYNC
Comp
Error
Amp
OVP
Comp
EN/SYNC >1.2 × fSW
VIN
VIN
VIN
FBX
FB
150 nA
10 A 20 A
POK
SW
BOOT
SW
OSC
3.5 k
0.85 V
Typ
1.25 V Typ
1.65 V Typ
2.9 V
+
+
+
+
+
+
+
OVP
S
R
Q
Q
Slope
Compensation
EN/SYNC
SS
GND
PAD
GND
FAULT = 1, if:
EN = 0, or
UVLO = 1, or
OVP = 1, or
Diode Missing = 1
HICCUP = 1, if Hiccup protection enabled (VFB < 625 mV) and
a net count of > 7 OCP events occur
1500
125 ns
COMP
UVLO
(VIN)
Diode
Missing
HICCUP
Latched
Hiccup
Protection
Hiccup reset VSS = 235 mV Typ
Clamp 1.7 V Typ
40 k Typ
Rising
Digital
OFF
OFF
TSD
POR
FAULT
Fault
Logic
UVLO (VIN)
OCP
Latch reset
EN/SYNC
toggle
OVP
Diode Missing
A
A
B
B114%×VREF
W ide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
A8582
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Terminal List Table
1, 2, 3 VIN
Power input for the control circuits and the drain of the internal high-side N-channel
MOSFET. Connect this pin to a power supply of 4.7 to 36 V. A high quality ceramic capacitor
should be placed very close to this pin.
4SS
Soft-start pin. Connect a capacitor, CSS, from this pin to GND to set the soft-start time. This
capacitor also determines the hiccup period during an overcurrent event.
5, 12 GND Ground.
6 POK Power OK output signal. This pin is an open drain output that transitions from low impedance
to high impedance when the output is within the final regulation voltage.
7 EN/SYNC
Enable and synchronization input. This pin is a logic input that turns the converter on or
off. Set this pin to logic high to turn the converter on or set this pin to logic low to turn the
converter off. This pin also functions as a synchronization input to allow the PWM frequency
to be set by an external clock.
8 FSET Frequency setting pin. A resistor, RFSET, from this pin to GND sets the PWM switching
frequency. See figure 10 and/or equation 2 to determine the value of RFSET.
9FB
Feedback (negative) input to the Error amplifier. Connect a resistive divider from the
converter output node, VOUT , to this pin to program the output voltage.
10 FBX
Remote sense input for the overvoltage protection (OVP) comparator. Connect a resistive
divider from the converter output node, VOUT , to this pin to set the OVP trip threshold. If
OVP protection is not required, this pin should be grounded.
11 COMP
Output of the error amplifier and compensation node for the current-mode control loop.
Connect a series RC network from this pin to GND for loop compensation. See the Design
and Component Selection section of this datasheet for further details.
13 NC No connect.
14 BOOT High-side gate drive boost input. This pin supplies the drive for the high-side N-channel
MOSFET. Connect a 100 nF ceramic capacitor from BOOT to SW.
15, 16 SW
The source of the internal high-side N-channel MOSFET. The external free-wheeling diode
(D1) and output inductor (LO) should be connected to this pin. Both D1 and LO should be
placed close to this pin and connected with relatively wide traces.
–PAD
Exposed pad of the package providing enhanced thermal dissipation. This pad must be
connected to the ground plane(s) of the PCB with at least 6 vias, directly in the pad.
VIN
VIN
VIN
SS
GND
POK
EN/SYNC
FSET
SW
SW
BOOT
NC
GND
COMP
FBX
FB
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PAD
Pin-out Diagram
W ide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
A8582
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS1 Valid at VIN = 12 V, TA = 25°C , indicates specifications guaranteed through
–40°C TJ 125°C ; unless otherwise specified
Characteristics Symbol Test Conditions Min. Typ.2Max. Unit
Input Voltage Specifications
Operating Input Voltage Range VIN 4.7 36 V
UVLO Start Threshold VINSTART VIN rising 4.2 4.6 V
UVLO Stop Threshold VINSTOP VIN falling 3.8 4.2 V
UVLO Hysteresis VUVLOHYS 280 400 520 mV
Input Currents
Input Quiescent Current IQ
VEN/SYNC = 5 V, VFB = 1.5 V,
no PWM switching 3.0 5.0 mA
Input Sleep Supply Current3IQSLEEP
VIN = 16 V, VEN/SYNC 0.4 V,
TA = TJ between –40°C and 85°C 3.0 A
VIN = 16 V, VEN/SYNC 0.4 V, TA = TJ = 125°C 515A
Reference Voltage
Feedback Voltage VFB 4.7 V < VIN < 36 V, VFB = VCOMP 792 800 808 mV
Error Amplifier
Feedback Input Bias Current IFB
VCOMP = 1.5 V, VFB regulated so that
ICOMP = 0 A –150 –300 nA
Open Loop Voltage Gain AVOL –56–dB
Transconductance gm
ICOMP = 0 A, VSS > 700 mV 550 750 1000 A/V
0 V < VSS < 700 mV 225 A/V
Source Current IEA(SRC) VFB < 0.8 V, VCOMP = 1.5 V –50 A
Sink Current IEA(SINK) VFB > 0.8 V, VCOMP = 1.5 V +50 A
Maximum Output Voltage VEAVO(max) 1.3 1.7 2.1 V
COMP Pull-Down Resistance RCOMP FAULT = 1 1500 
Pulse Width Modulation (PWM)
PWM Ramp Offset VPWMOFFSET VCOMP for 0% duty cycle 300 mV
Minimum Controllable On-Time tON(MIN) 65 100 ns
Minimum Switch Off-Time tOFF(MIN) 65 130 ns
COMP to SW Current Gain gmPOWER 2.85 A/V
Slope Compensation SE
fSW = 250 kHz 0.19 A/s
fSW = 2.0 MHz 1.5 A/s
MOSFET Parameters
Hi-Side MOSFET On Resistance RDS(on)HS IDS = 400 mA, VBOOT VSW = 6 V 70 m
High-Side MOSFET Leakage Current3ILEAK
VIN = 16 V, VEN/SYNC 0.4 V, VSW = 0 V
TA = TJ between –40°C and 85°C 10 A
VIN = 16 V, VEN/SYNC 0.4 V, VSW = 0 V,
TA = TJ = 125°C 50 150 A
Low-Side MOSFET On Resistance RDS(on)LS IDS = 10 mA, (VBOOT – VSW) < 4 V 10 12
Continued on the next page…
W ide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
A8582
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Oscillator Frequency
Oscillator Frequency fSW
RFSET = 9.09 k2.20 2.45 2.70 MHz
RFSET = 24.9 k0.90 1.00 1.10 MHz
RFSET = 105 k250 kHz
Synchronization Timing
Synchronization Frequency Range fSW_MULT 1.2 × fSW 1.5 × fSW MHz
Synchronized PWM Frequency fSW_SYNC 2.9 MHz
Synchronization Input Duty Cycle DSYNC 80 %
Synchronization Input Pulse Width tWSYNC 200 ns
Synchronization Input Edge Rise Time trSYNC 10 15 ns
Synchronization Input Edge Fall Time tfSYNC 10 15 ns
Enable/Synchronization Input
EN/SYNC High Threshold VENIH VEN/SYNC rising 1.65 1.80 V
EN/SYNC Low Threshold VENIL VEN/SYNC falling 1.25 V
EN/SYNC Low Threshold (Sleep) VENILSLEEP VEN/SYNC falling 0.40 0.85 V
EN/SYNC Hysteresis VENHYS VENIH – VENIL 400 mV
EN/SYNC Digital Delay tSLEEP VEN/SYNC transitioning high or low cycles 32 PWM
cycles
EN/SYNC Input Resistance REN/SYNC 20 40 k
Overcurrent Protection (OCP) and Hiccup Mode
Pulse-by-Pulse Current Limit ILIM
Duty cycle = 5%, EN/SYNC = High (no sync) 2.80 3.25 3.70 A
Duty cycle = 90%, EN/SYNC = High (no sync) 2.30 2.70 3.15 A
Hiccup Disable Threshold VHICDIS VFB rising 750 mV
Hiccup Enable Threshold VHICEN VFB falling 625 mV
OCP / HICCUP Count Limit OCPLIMIT Hiccup enabled, OCP pulses 7counts
Overvoltage Protection (OVP)
OVP Comparator Threshold VOVPTRIP VFBX rising, as a percentage of VREF 112 114 116 %
FBX Time Constant (Filtering)4FBX 125 ns
Soft Start (SS)
SS COMP Release Voltage VSSRELEASE VSS rising due to ISSSU 255 330 mV
SS Fault/Hiccup Reset Voltage VSSRESET VSS falling due to ISSHIC 235 310 mV
SS Maximum Charge Voltage VSSCHRG 3.1 V
SS Startup (Source) Current ISSSU VSS = 1 V, HICCUP = FAULT = 0 10 –20 30 A
SS Hiccup (Sink) Current ISSHIC VSS = 0.5 V, HICCUP = 1 51020A
Continued on the next page…
ELECTRICAL CHARACTERISTICS1 (continued) Valid at VIN = 12 V, TA = 25°C , indicates specifications guaranteed through
–40°C TJ 125°C ; unless otherwise specified
Characteristics Symbol Test Conditions Min. Typ.2Max. Unit
W ide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
A8582
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Soft Start (SS) (continued)
SS Input Resistance RSS FAULT = 1 3.5 k
SS to VOUT Delay Time tSSDELAY CSS = 22 nF 363 s
VOUT Soft Start Ramp Time tSS CSS = 22 nF 880 s
SS Switching Frequency fSS
VFB = 0 V fSW / 3 MHz
VFB 600 mV fSW MHz
Power OK (POK) Output
POK Output Voltage VPOK IPOK = 4 mA 0.4 V
POK Leakage IPOKLEAK VPOK = 5 V 1A
POK Comparator Threshold VPOKTHRESH VFB rising, as a percentage of VREF 87 90 93 %
POK Hysteresis VPOKHYS VFB falling, as a percentage of VREF 256%
POK Digital Delay tdPOK VFB rising only 7PWM
cycles
Thermal Protection (TSD)
Thermal Shutdown Threshold4TTSD Temperature rising 150 165 °C
Thermal Shutdown Hysteresis4TTSDHYS 20 °C
1For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as
going into the node or pin (sinking).
2Typical specifications are at TA = 25ºC.
3For TA = TJ between –40°C and 85°C, ensured by design and characterization, not production tested.
4Ensured by design and characterization, not production tested.
ELECTRICAL CHARACTERISTICS1 (continued) Valid at VIN = 12 V, TA = 25°C , indicates specifications guaranteed through
–40°C TJ 125°C ; unless otherwise specified
Characteristics Symbol Test Conditions Min. Typ.2Max. Unit
W ide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
A8582
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Ambient Temperature, TA (°C)
VIN = 4.7 V
58
57
56
55
54
53
52
Open Loop Voltage Gain, AVOL (dB)
-50 -25 0 25 50 75 100 150125 175
Error Amplifier Voltage Gain versus Temperature
800
750
700
650
600
Ambient Temperature, TA (°C)
Transconductance, gm (A/V)
-50 -25 0 25 50 75 100 150125 175
Error Amplifier Transconductance versus Temperature
Ambient Temperature, TA (°C)
SS Hiccup (Sink) Current, ISSHIC (A)
10.0
9.9
9.8
9.7
9.6
9.5
-50 -25 0 25 50 75 100 150125 175
Soft Start Hiccup (Sink) Current versus Temperature
Ambient Temperature, TA (°C)
SS Startup (Source) Current, ISSSU (A)
–16
–17
–18
–19
–20
-50 -25 0 25 50 75 100 150125 175
Soft Start (Source) Current versus Temperature
1.02
1.01
1.00
0.99
0.98
0.97
0.96
Ambient Temperature, TA (°C)
Switching Frequency, fSW (MHz)
-50 -25 0 25 50 75 100 150125 175
Switching Frequency versus Temperature
804
803
802
801
800
799
798
797
796
-50 -25 0 25 50 75 100 150125 175
Ambient Temperature, TA (°C)
Reference Voltage versus Temperature
Reference Voltage, VREF (mV)
Typical Characteristic Performance
W ide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
A8582
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Ambient Temperature, TA (°C)
VIN = 16 V, EN/SYNC = Low
High-Side MOSFET Leakage,
ILEAK (A)
60
50
40
30
20
10
0
–10
-50-250 255075100 150125 175
SW Leakage Output Current versus Temperature
Ambient Temperature, TA (°C)
VIN = 16 V, EN/SYNC = Low
Input Quiescent Current, IQ (A)
5
4
3
2
1
0
–1
-50 -25 0 25 50 75 100 150125 175
Sleep Input Current versus Temperature
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
Ambient Temperature, TA (°C)
EN/SYNC Threshold, VENx (V)
-50 -25 0 25 50 75 100 150125 175
VENIH (Run: VEN/SYNC rising)
VENILSLEEP (Sleep: VEN/SYNC falling)
Enable Threshold Voltage versus Temperature
4.3
4.2
4.1
4.0
3.9
3.8
3.7
-50 -25 0 25 50 75 100 150125 175
Ambient Temperature, TA (°C)
UVLO Threshold Voltage versus Temperature
UVLO Threshold, VINx (V)
VINSTART (VIN rising)
VINSTOP (VIN falling)
W ide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
A8582
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Description
Overview
The A8582 is an asynchronous PWM regulator that incorporates
all the control and protection circuitry necessary to satisfy a wide
range of applications. The A8582 employs current mode control
to provide fast transient response, simple compensation, and
excellent stability. The features of the A8582 include a precision
reference, an adjustable switching frequency, a transconductance
error amplifier, an enable/synchronization input, an integrated
high-side N-channel MOSFET, adjustable soft-start time, pre-bias
startup, low current sleep mode, and a Power OK (POK) out-
put. The protection features of the A8582 include undervoltage
lockout (UVLO), pulse-by-pulse over current protection (OCP),
hiccup mode short-circuit protection (HIC), overvoltage protec-
tion (OVP), and thermal shutdown (TSD). In addition, the A8582
provides open-circuit, adjacent pin short-circuit, and pin-to-
ground short circuit protection.
Reference Voltage
The A8582 incorporates an internal reference that allows output
voltages as low as 0.8 V. The accuracy of the internal reference
is ±1% through the operating temperature range. The output volt-
age of the regulator is adjusted by connecting a resistor divider
(RFB1 and RFB2 in figure 1) from VOUT to the FB pin of
the A8582.
Oscillator/Switching Frequency
The PWM switching frequency of the A8582 is adjustable from
250 kHz to 2.4 MHz and has an accuracy of ±12% through
the operating temperature range. Connecting a resistor from
the FSET pin to GND, as shown in figure 1, sets the switching
frequency. An FSET resistor with 1% tolerance is recommended.
A graph of switching frequency versus FSET resistor value is
shown in the Design and Component Selection section of this
datasheet.
Transconductance Error Amplifier
The primary function of the transconductance error amplifier
is to regulate the converter output voltage. The error amplifier
is shown in figure 2. It is shown as a 3-terminal input device
with two positive and one negative inputs. The negative input is
simply connected to the FB pin and is used to sense the feedback
voltage for regulation. The two positive inputs are used for soft
start and regulation. The error amplifier performs an “analog OR”
selection between the two positive inputs. The error amplifier
regulates to either the soft start pin voltage (minus 400 mV) or
the A8582 internal reference, whichever is lower.
To stabilize the regulator, a series RC compensation network
(RZ and CZ) must be connected from the error amplifier output
(COMP pin) to GND as shown in figure 1. In some applications,
an additional, a low value capacitor (CP) may be connected in
parallel with the RC compensation network to reduce the loop
gain at higher frequencies. However, if the CP capacitor is too
large, the phase margin of the converter may be reduced. If the
regulator is disabled or a fault occurs, the COMP pin is imme-
diately pulled to GND via approximately 1500 , and PWM
switching is inhibited.
Slope Compensation
The A8582 incorporates internal slope compensation to allow
PWM duty cycles above 50% for a wide range of input/output
voltages, switching frequencies, and inductor values. As shown in
the Functional Block Diagram, the slope compensation signal is
added to the sum of the current sense and PWM ramp offset. The
amount of slope compensation is scaled directly with the switch-
ing frequency.
+
-
+
Error Amplifier
COMP
SS
FB
VREF
800 mV
400 mV A8582
Figure 2. The A8582 transconductance error amplifier
W ide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
A8582
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Sleep Mode
If the voltage at the EN/SYNC pin is pulled below 400 mV
(VENILSLEEP ) the A8582 will enter a sleep mode where the inter-
nal control circuits will be shut off and draw less than 3 A from
VIN . However, the total current drawn by the VIN pin will be the
sum of the current drawn by the control circuitry (<3 A) plus
any leakage due to the high-side MOSFET (<10 A at 25°C).
Enable/Synchronization (EN/SYNC) Input
The enable/synchronization (EN/SYNC) input provides three
functions:
A control input that commands the sleep mode of the A8582.
When EN/SYNC is very low (VEN/SYNC< VENILSLEEP ), most
of the internal circuits are de-biased to provide the sleep mode
current of less than 3 A.
A simple logic input. If EN/SYNC is a logic low (VEN/SYNC <
VENIL ), then the A8582 and VOUT will be off. If EN/SYNC is
a logic high (VEN/SYNC > VENIH ), the A8582 will turn on and,
provided there are no fault conditions, soft start will be initiated
and VOUT will ramp to its final voltage in a time set by the soft
start capacitor (CSS). (The operating modes of the A8582 based
on EN/SYNC voltage are summarized in figure 3.)
A synchronization input that accepts an external clock to turn on
the A8582 and (after soft starting) will scale the PWM switch-
ing frequency from 1.2X to 1.5X above the base frequency set
by the FSET resistor.
Note that, when used as a synchronization input, soft start is at
the base frequency set by the FSET resistor. Synchronization
to the external clock occurs after soft start is completed (when
VFB > VPOKTHRESH). When being used as a synchronization
input, the applied clock pulses must satisfy the pulse width, duty-
cycle, and rise/fall time requirements shown in the Electrical
Characteristics table in this datasheet.
To automatically enable the A8582, the EN/SYNC input pin may
be connected to a voltage rail, such as VIN
, via a resistor and a
Zener diode as shown in figure 4.
There is a short delay between when EN/SYNC transitions low
and when PWM switching stops. This is necessary because the
enable circuitry must distinguish between a constant logic level
and synchronization pulses at the lowest switching frequency.
The nominal delay from when EN/SYNC transitions low and
PWM switching stopping is 32 PWM clock cycles. The shut-
Figure 3. EN/SYNC voltage and A8582 operating modes
Figure 4. Automatically enabling the A8582 from VIN or some other
power rail
R
EN/SYNC A8582
V
IN
2.2 V < V
Z
< 4.7 V
SLEEP WAKE
(iIN < 3 A
PWM = Off
)
(iIN
2 mA
PWM = Off
)
RUN
(iIN
3 mA
PWM = On
)
VEN > 1.15 V
VEN > 1.15 V
VEN < 0.85 V
for 32 cycles
VSS < 0.2 V
Timer expired
Discharge
Soft-start capacitor
(PWM = Off)
Wait up to
32 cycles
(PWM = On)
VEN < 0.85 V
VEN > 1.65 V
W ide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
A8582
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
down transition delay from switching to sleep mode is shown in
figure 5.
Power MOSFETs
The A8582 includes a low RDS(on)
, high-side N-channel
MOSFET capable of delivering up to 2.0 A of current at high
duty cycles. The A8582 also includes a 10 , low-side MOSFET
to insure the boot capacitor (CBOOT) is always charged.
Unlike other typical asynchronous regulators, the A8582 only
turns on the lower MOSFET when the boot capacitor must be
charged. This minimizes negative currents in the output inductor
and improves the light load efficiency. When the EN/SYNC input
is low or a fault occurs, the A8582 is disabled and the regula-
tor output stage is tristated by turning off both the upper and
lower MOSFETs.
Pulse Width Modulation (PWM)
A high-speed PWM comparator, capable of pulse widths less
than 100 ns, is included in the A8582. The inverting input of
the comparator is connected to the output of the error amplifier.
The noninverting input is connected to the sum of the current
sense signal, the slope compensation, and a PWM Ramp Offset
(VPWMOFFSET, nominally 300 mV). At the beginning of each
PWM cycle, the CLK signal sets the PWM flip-flop and the
upper MOSFET is turned on. When the summation of the DC
offset, the slope compensation, and the current sense signal rises
above the error amplifier voltage, the comparator will reset the
PWM flip-flop and the upper MOSFET will be turned off. If the
output voltage of the error amplifier drops below the PWM Ramp
Offset (VPWMOFFSET) then zero PWM duty-cycle (pulse skipping)
operation is achieved.
Current Sense Amplifier
A high-bandwidth current sense amplifier monitors the current in
the upper MOSFET. The PWM comparator, the pulse-by-pulse
current limiter, and the hiccup mode up/down counter require the
current signal.
Soft Start (Startup) and Inrush Current Control
Inrush currents to the converter are controlled by the soft start
function of the A8582. When the A8582 is enabled and all faults
are cleared, the soft start (SS) pin will source approximately
20 A (ISSSU) and the voltage on the soft start capacitor (CSS)
will ramp upward from 0 V. When the voltage on the soft start
pin exceeds the Soft Start COMP Release Voltage threshold
(VSSRELEASE
, 330 mV typical, measured at the soft start pin) the
output of the error amplifier is released, and shortly thereafter the
upper and lower MOSFETs will begin switching. As shown in
figure 6, there is a short delay (tSSDELAY) to initiate PWM switch-
ing, between when the EN/SYNC pin transitions high and when
the soft start voltage reaches 330 mV.
Figure 5. PWM switching stops and sleep mode begins approximately
32 cycles after EN/SYNC transitions low; shows VOUT (ch1, 1 V/div.),
VCOMP (ch2, 1 V/div.), VEN/SYNC (ch3, 2 V/div.), t = 50 s/div.
t
VOUT
VCOMP
32 cycles delay
VEN/SYNC
C1
C3
C2
W ide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
A8582
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
When the A8582 begins PWM switching, the error amplifier
regulates the voltage at the FB pin to the soft start pin voltage
minus the Soft Start PWM Threshold voltage (VSSPWM). When
PWM switching starts, the voltage at the soft start pin rises from
330 mV to 1.13 V (a difference of 800 mV), the voltage at the FB
pin rises from 0 V to 800 mV, and the regulator output voltage
rises from 0 V to the required set-point determined by the feed-
back resistor divider (RFB1 and RFB2).
When the voltage at the soft start pin reaches approximately
1.13 V, the error amplifier will “switch over” and begin regulat-
ing to the A8582 internal reference, 800 mV. The voltage at the
soft start pin will continue to rise to about 3.3 V. The soft start
functionality is shown in figure 6.
If the A8582 is disabled or a fault occurs, the internal fault latch
is set and the soft start pin is pulled to GND via approximately
3.5 k. The A8582 will clear the internal fault latch when the
voltage at the soft start pin decays to approximately 235 mV
(VSSRESET).
If the A8582 enters hiccup mode, the capacitor on the soft start
pin is discharged by a 10 A current sink (ISSHIC
). Therefore, the
soft start pin capacitor value (CSS) controls the time between soft
start attempts. Hiccup mode operation is discussed in more detail
in the Output Short Circuit (Hiccup Mode) Protection section of
this datasheet. During startup, the PWM switching frequency is
scaled linearly from fSW / 3 to fSW as the voltage at the FB pin
ramps from 0 V to 600 mV. This is done to minimize the peak
current in the output inductor when the input voltage is high and
the output of the regulator is either shorted, or soft starting a
relatively high output capacitance.
Pre-Biased Startup
If the output capacitors are pre-biased to some voltage, the A8582
will modify the normal startup routine to prevent discharging
the output capacitors. Normally, the COMP pin is released and
PWM switching starts when the voltage at the soft start pin
reaches 330 mV. In the case with pre-bias at the output, the pre-
bias voltage will be sensed at the FB pin. The A8582 will not
start switching until the voltage at the soft-start pin increases to
approximately VFB + 330 mV. At this soft start pin voltage, the
error amplifier output is released, the voltage at the COMP pin
rises, PWM switching starts, and VOUT will ramp upward starting
from the pre-bias level. Figure 7 shows startup when the output
voltage is pre-biased to 2.0 V.
Power OK (POK) Output
The Power OK (POK) output is an open drain output, so an
external pull-up resistor must be connected. An internal compara-
tor monitors the voltage at the FB pin and controls the open drain
device at the POK pin. POK remains low until the voltage at the
FB pin is within 10% of the final regulation voltage. The POK
output is pulled low if: (1) the EN/SYNC pin transitions low for
more than 32 PWM cycles, (2) UVLO occurs, (3) TSD occurs, or
(4) OVP occurs.
Figure 7. Startup to VOUT = 5 V, with VOUT pre-biased to 2 V; shows
VEN/SYNC (ch1, 2 V/div.), VOUT (ch2, 2 V/div.), VCOMP (ch3, 500 mV/div.),
VSS (ch4, 500 mV/div.), IL (ch5, 2 A /div.), t = 200 s/div.
Figure 6. Startup to VOUT = 5 V, 2.0 A, with CSS = 22 nF; shows VEN/SYNC
(ch1, 2 V/div.), VOUT (ch2, 2 V/div.), VCOMP (ch3, 500 mV/div.), VSS (ch4,
500 mV/div.), IL (ch5, 2 A /div.), t = 200 s/div.
t
VOUT
VSS 0.330 V
1.13 V
5 V
IL
VCOMP
VEN/SYNC
tSSDELAY
tSS
C1
C3
C4
C5
C2
VOUT
VOUT increases
monotonically
Switching delayed until
VSS = VFB + 0.330 V
COMP pin
released
VSS 0.330 V
5 V
2 V
IL
VCOMP
VEN/SYNC
C1
C3
C4
C5
C2
t
W ide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
A8582
14
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
If the A8582 is running and EN/SYNC transitions low, then after
32 PWM cycles, POK will transition low and remain low only as
long as the internal rail is able to enhance the open drain output
device. After the internal rail collapses, POK will return to the
high impedance state. The POK comparator incorporates hyster-
esis to prevent chattering due to voltage ripple at the FB pin.
Protection Features
Undervoltage Lockout (UVLO)
An Undervoltage Lockout (UVLO) comparator monitors the volt-
age at the VIN pin and keeps the regulator disabled if the voltage
is below the lockout threshold (VINSTART). The UVLO compara-
tor incorporates enough hysteresis (VUVLOHYS) to prevent on/off
cycling of the regulator due to IR drops in the VIN path during
heavy loading or during startup.
Thermal Shutdown (TSD)
The A8582 protects itself from over-heating, with an internal
thermal monitoring circuit. If the junction temperature exceeds
the upper thermal shutdown threshold (TTSD
, nominally 165°C)
the voltages at the soft start and COMP pins will be pulled to
GND and both the upper and lower MOSFETs will be shut off.
The A8582 will stop PWM switching and stay in WAKE state
(see figure 3). It will automatically restart when the junction
temperature decreases more than the thermal shutdown hysteresis
(TTSDHYS
, nominally 20°C).
Overvoltage Protection (OVP)
The A8582 provides a remote sense input pin (FBX) to protect
the system from an overvoltage condition. An overvoltage condi-
tion will occur if the FB pin is inadvertently grounded, the series
feedback resistor (RFB1 in figure 1) is missing, the FB pin is not
soldered, the FB trace is broken, or the COMP pin is shorted to
a voltage higher than approximately 1.6 V. When an overvoltage
condition is detected: (1) the fault is latched, (2) PWM switching
stops, and (3) POK, SS, and COMP are pulled low. An OVP fault
may be cleared by either toggling the EN/SYNC input or cycling
power to the VIN pin.
The FBX pin should be connected to VOUT using a feedback
resistor divider as shown in figure 1. To prevent nuisance trips it
is recommended that a capacitor (CFBX) be included from FBX
to ground to place a pole at approximately 2X to 5X the system
crossover frequency, fC (see the Compensation Components
section of this datasheet). For optimal protection the trace that
connects the FBX resistor divider should be separate from the
trace that connects the FB resistor divider. If the OVP function is
not required, the FBX pin can be grounded to essentially disable
the OVP comparator.
Usually, the FBX resistor divider will be identical to the FB
resistor divider and the OVP threshold will be equal to VOVPTRIP
shown in the Electrical Characteristics table (nominally 114% of
VREF). However, if nuisance trips occur during transient situ-
ations, the OVP trip threshold can be scaled slightly higher by
using a resistor divider that provides less voltage at the FBX pin.
Reducing the signal at the FBX pin essentially desensitizes the
OVP circuit, so care should be taken not to increase the OVP trip
threshold beyond a reasonable amount.
Table 1. Pulse-by-Pulse Current Limit
versus Duty Cycle
D
(%)
ILIM
(A)
Min. Typ. Max.
5 2.80 3.20 3.70
20 2.69 3.09 3.49
40 2.58 2.98 3.38
60 2.47 2.87 3.27
80 2.36 2.76 3.16
90 2.30 2.70 3.10
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
5 101520253035 4540 50
Duty Cycle, D (%)
Pulse-by-Pulse Current LImit
ILIM, D (%)
55 60 65 70 75 80 85 90
Maximum
Typical
Minimum
Figure 8. Pulse-by-pulse current limit versus duty cycle
W ide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
A8582
15
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Pulse-by-Pulse Overcurrent Protection (OCP)
The A8582 monitors the current in the upper MOSFET and if the
current exceeds the pulse-by-pulse overcurrent threshold (ILIM)
then the upper MOSFET is turned off. Normal PWM operation
resumes on the next clock pulse from the oscillator. The A8582
includes leading edge blanking to prevent falsely triggering the
pulse-by-pulse current limit when the upper MOSFET is turned
on. Pulse-by-pulse current limiting is always active.
The A8582 is conservatively rated to deliver 2.0 A for most
applications. However, the exact current it can support is heavily
dependent on duty cycle, ambient temperature, thermal resis-
tance of the PCB, airflow, component selection, and nearby heat
sources. The A8582 is designed to deliver more current at lower
duty cycles and slightly less current at higher duty cycles. For
example, the pulse-by-pulse limit at 20% duty cycle is 2.69 A
but at 80% duty cycle the pulse limit is 2.36 A. Use table 1 and
figure 8 to determine the real current limit, given the duty cycle
required for each application. Take care to do a careful thermal
solution or thermal shutdown will occur.
Output Short Circuit (Hiccup Mode) Protection
Hiccup mode protects the A8582 when the load is either too high
or when the output of the converter is shorted to ground. When
the voltage at the FB pin is below the Hiccup Enable Thresh-
old (VHICEN
, nominally 625 mV), Hiccup mode protection is
enabled. When the voltage at the FB pin is above the Hiccup
Disable Threshold (VHICDIS , nominally 750 mV), Hiccup mode
protection is disabled.
Hiccup Mode overcurrent protection monitors the number of
overcurrent events using an up/down counter: an overcurrent
pulse increases the count by one, and a PWM cycle without an
overcurrent pulse decreases the count by one. If the total count
reaches more than 7 (while Hiccup mode is enabled) then the
Hiccup latch is set and PWM switching is stopped. The Hiccup
signal causes the COMP pin to be pulled low with a relatively
low resistance (1500 ). Hiccup mode also enables a current sink
connected to the soft start pin (nominally 10 A) so, when Hic-
cup first occurs, the voltage at the soft start pin ramps downward.
Hiccup mode operation is shown in figure 9.
When the voltage at the soft start pin decays to a low level (VSS-
RESET
, 235 mV typical), the Hiccup latch is cleared and the 10 A
soft start pin current sink is turned off. The soft start pin will
resume charging the soft start capacitor with 20 A and the volt-
age at the soft start pin will ramp upward. When the voltage at the
soft start pin exceeds the COMP release threshold (VSSRELEASE
,
330 mV typical), the low resistance pull-down at the COMP pin
will be turned off and the Error amplifier will force the voltage
at the COMP pin to ramp up quickly, and PWM switching will
begin. If the short circuit at the converter output remains, another
Hiccup cycle will occur. Hiccups will repeat until the short circuit
is removed or the converter is disabled. If the short circuit is
removed, the A8582 will soft start normally and the output volt-
age will be ramped to the required level as shown in figure 9.
Figure 9. Hiccup mode operation and recovery ; shows VSS (ch1, 200 mV/div.),
VOUT (ch2, 2 V/div.), VCOMP (ch3, 1 V/div.), IL (ch4, 5 A/div.), t = 500 s/div.
t
VSS
Short removed
330 mV
235 mV
6.5 A
VOUT
VCOMP
IL
C1
C3
C4
C2
W ide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
A8582
16
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Design and Component Selection
Setting the Output Voltage (VOUT, RFB1, RFB2)
The output voltage of the A8582 is determined by connecting
a resistor divider from the output node (VOUT) to the FB pin,
as shown in figure 10. There are trade-offs when choosing the
value of the feedback resisters. If the series combination (RFB1
+ RFB2) is relatively low, the light load efficiency of the regula-
tor will be reduced. So to maximize the efficiency, it is best to
choose high values for the resistors. On the other hand, if the par-
allel combination (RFB1 // RFB2) is too high, then the regulator
may be susceptible to noise coupling into the FB pin. In general,
the feedback resisters must satisfy the ratio shown in equation 1
to produce a required output voltage.
1
=
R
FB1
R
FB2
V
OUT
0.8 V
(1)
Table 2 shows the most common output voltages and recom-
mended feedback resistor values, assuming less than 0.2% effi-
ciency loss at light load of 100 mA and a parallel combination of
4 k presented to the FB pin. For optimal system accuracy, it is
recommended that the feedback resistors have 1% tolerances.
PWM Switching Frequency (RFSET)
The PWM switching frequency is set by connecting a resistor
from the FSET pin to ground. Figure 11 is a graph showing the
relationship between the typical switching frequency (y axis)
and the FSET resistor, 1/RFSET (x axis). For a given switching
frequency (fSW), the FSET resistor can be calculated using equa-
tion 2, where fSW is in kHz and RFSET is in k.
1.8
26730
=
R
FSET
f
SW
(2)
When the PWM switching frequency is chosen, the designer
should be aware of the minimum controllable PWM on-time,
tON(MIN) of the A8582. If the system required on-time is less than
the A8582 minimum controllable on-time, then switch node jitter
will occur, and the output voltage will have increased ripple or
oscillations. The PWM switching frequency should be calculated
using equation 3, where VOUT is the output voltage, tON(MIN) is
the minimum controllable on-time of the A8582 (worst case of
Application Information
Figure 10. Connecting the feedback divider Figure 11. PWM switching frequency versus 1/RFSET
RFB1
RFB2
FB
A8582
VOUT
2400
2200
2000
1800
1600
1400
1200
1000
800
600
400
200
0.01 0.02 0.03 0.04
PWM Switching Frequency, fSW (kHz)
1/ RFSET Resistance, 1/RFSET (k)
0.05 0.06 0.07 0.08 0.09 0.10 0.11
Table 2. Recommended Feedback Resistor Values
VOUT
(V)
RFB1
VOUT to FB pin
(kΩ)
RFB2
FB pin to GND
(kΩ)
1.2 6.04 12.1
1.5 7.50 8.45
1.8 9.09 7.15
2.5 12.4 5.76
3.3 16.5 5.23
5.0 24.9 4.75
7.0 34.8 4.53
8.0 40.2 4.42
9.6 47.5 4.32
W ide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
A8582
17
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
100 ns), and VIN(MAX) is the maximum required operational input
voltage to the A8582 (not the peak surge voltage).
<
f
SW
V
OUT
tON(MIN) × VIN(MAX)
(3)
If the A8582 synchronization function is employed, the base
switching frequency should be chosen such that jitter will not
result at the maximum synchronized switching frequency accord-
ing to equation 3, that is, 1.5 × fSW < fSW calculated by equa-
tion 2.
Output Inductor (LO)
The value of the output inductor (LO) is usually calculated to set
a particular peak-to-peak ripple current in the inductor. However,
the inductor physical size and cost will be directly proportional
to the peak current or saturation specification. There are tradeoffs
among: peak-to-peak ripple current, system efficiency, transient
response, and cost. If the peak-to-peak inductor ripple is chosen
to be relatively high, then the inductor value will be low, the sys-
tem efficiency will be reduced, the transient response will be fast,
the inductor physical size will be small, and the cost reduced. If
the peak-to-peak inductor ripple is chosen to be relatively low,
then the inductor value will be high, the system efficiency will be
higher, the transient response will be slow, the inductor physical
size will be larger, and the cost will be increased.
Equation 4 can be used to estimate the inductor value, given a
particular peak-to-peak ripple current (IL ), input voltage (VIN
),
output voltage (VOUT), and switching frequency (fSW). The refer-
ence designs in this datasheet use a peak-to-peak ripple current of
25% of the 2.0 A, DC rating of the A8582, or 0.5 APP
.
L
O
1
V
OUT
fSW × IL
V
OUT
V
IN
(4)
If the preceding equation yields an inductor value that is not a
standard value, the next higher available value should be used.
After choosing a standard inductor value, equation 5 should be
used to make sure the A8582 slope compensation is adequate.
In this equation VIN(MIN) is the minimum required input voltage,
VOUT is the output voltage, fSW is the switching frequency, and
Vf is the forward voltage of the asynchronous Schottky diode.
0.18 × (V
IN(MIN)
+ V
f )
L
O
11.3 × V
OUT
+ V
f
V
OUT
+ V
f
fSW
(5)
Ideally, the rated saturation current of the inductor should be
higher than the maximum current capability of the A8582 at
the expected duty cycle. Unfortunately this usually results in
a physically larger, more costly inductor. At a minimum, the
saturation current of the inductor should support the DC rating
of the A8582 (2.0 A), plus ½ of the inductor peak-to-peak ripple
current (usually 0.5 APP
), the capacitive startup current (ICO
),
and some margin for component, frequency, and voltage toler-
ances. For example, an inductor with a 2.7 A rating allows 2.0 A
of load current, 0.25 APEAK of ripple current, 0.25 A of capaci-
tive startup current (ICO
), along with a 20% frequency decrease,
a 20% inductance decrease, and a 10% input voltage increase (at
5.0 VOUT
, 12 VIN
, 2 MHz ).
After an inductor is chosen, it should be tested during output
short circuit conditions. The inductor current should be monitored
using a current probe. A good design should ensure the inductor
or the regulator are not damaged when the output is shorted to
GND at maximum input voltage and the highest expected ambi-
ent temperature
Output Capacitors (COUT)
The output capacitors filter the output voltage to provide an
acceptable level of ripple voltage and they store energy to help
maintain voltage regulation during a load transient. The voltage
rating of the output capacitors must support the output voltage
with sufficient design margin.
The output voltage ripple (VOUT ) is a function of the output
capacitor parameters: ESRCO
, ESLCO
, and CO
, as follows:
VOUT = VESR + VESL + VCO (6)
It is commonly known that, for a constant load on the regula-
tor, the current in the output inductor is equal to the DC output
current plus IL . Therefore, using Kirchoffs Current law, it can
be shown that the current in the output capacitors is equal to the
ripple current in the output inductor, or IC = IL . Knowing this,
we can determine the first term in equation 6:
VESR = IL × ESRCO (7)
W ide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
A8582
18
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
To calculate the second term in equation 6, VESL
, we must
determine the slope of the output inductor current, di/dt, which is
(VIN – VOUT) / LO:
ESLCO ×
==
V
ESL
LOLO
V
IN
– V
OUT
LO
di
dt
(8)
To calculate the third term in equation 6, we must understand
that, over a single PWM cycle, the amount of charge into the
output capacitors must equal the amount of charge out of the
capacitors, or the capacitor output voltages would drift. What this
means is the output inductor current (IL) flows in and out of the
output capacitor and is centered at 0 A, as shown in figure 12.
For any capacitor, the voltage is:
VCO dt
×
i
1
C
OUT
In this case, the integral term can be graphically calculated by
examining the 2 areas, A1 and A2, shown in figure 12:
==×
A1
A1
+
A2
1
2
×
IL
2
DTSILDTS
2 8
=
==
=–×
A21
2
×
IL
2
(1 –D)TSILTS
2 8
ILDTS
8
ILDTS
8
dt
×
i
Substituting this into the equation for VCO results in:
=
VCO
IL
COUT
TS
8
=
IL
fSW COUT
8
(9)
Combining equations 7, 8, and 9 results in an expression for the
total output voltage ripple:
=
VOUT IL×
ESRCO +
VINVOUT
×
ESLCO +
LO
IL
fSW COUT
8
(10)
The type of output capacitors will determine which terms of
equation 10 are dominant.
For ceramic output capacitors the ESR and ESL are extremely
low, so the output voltage ripple will be dominated by the third
term of equation 10:
=
VOUT
IL
fSW COUT
8
(10a)
To reduce the voltage ripple of a design using ceramic output
capacitors, simply: increase the total capacitance, reduce the
inductor current ripple (that is, increase the inductor value), or
increase the switching frequency.
For electrolytic output capacitors the value of capacitance will be
relatively high, so the third term in equation 10 will be minimized
and the output voltage ripple will be determined primarily by the
first two terms of equation 10:
=
VOUT IL×
ESRCO +
VINVOUT
×
ESLCO
LO
(10b)
To reduce the voltage ripple of a design using electrolytic output
capacitors, simply: decrease the equivalent ESR and ESL by
using a high(er) quality capacitor, and/or add more capacitors in
parallel, or reduce the inductor current ripple (that is, increase
the inductor value). The ESR of some electrolytic capacitors
can be quite high, so Allegro recommends choosing a quality
capacitor that clearly documents the ESR or the total impedance
in the datasheet. Also, the ESR of electrolytic capacitors usu-
ally increases significantly at cold ambient, which increases the
output voltage ripple and, in many cases, reduces the stability of
the system.
To reduce the output voltage ripple and save PCB area, a design
could combine both ceramic and electrolytic capacitors in paral-
lel. If this is done, the ceramic capacitors should be placed and
grounded as close as possible to the load to be most effective. AC
Figure 12. Output capacitor current waveform
ICO
IL /
2
IL /
2
0
(A) TS
DTS
/2
A1 A2
Time
[(1 – D)TS
]/2
DTS(1 – D)TS
W ide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
A8582
19
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ripple voltage measurements should be made differentially across
the ceramic capacitors with a very short ground lead.
The transient response of the A8582 depends on the number and
type of output capacitors. In general, minimizing the ESR of the
output capacitance will result in a better transient response. The
ESR can be minimized by simply: adding more capacitors in
parallel, or by using higher quality capacitors. At the instant of a
fast load transient (di/dt), the output voltage will change by the
amount:
=
VOUT ILOAD ×
ESRCO +
di
dt ESLCO
(11)
After the load transient occurs, the output voltage will deviate
for a short time depending on the system bandwidth, the output
inductor value, and output capacitance. After a short delay, the
Error amplifier will bring the output voltage back to its nominal
value. The speed at which the Error amplifier brings the output
voltage back to its set point will depend mainly on the closed-
loop bandwidth of the system. A higher bandwidth usually results
in a shorter time to return to the nominal voltage. However, a
higher bandwidth system may be more difficult to obtain accept-
able gain and phase margins. Selection of the compensation
components (RZ, CZ, CP) are discussed in more detail in the
Compensation Components section of this datasheet.
Input Capacitors (CIN)
Three factors should be considered when choosing the input
capacitors. First, they must be chosen to support the maximum
expected input voltage with adequate design margin. Second,
their rms current rating must be higher than the expected rms
input current to the regulator. Third, they must have enough
capacitance and a low enough ESR to limit the input voltage
dV/dt to something much less than the hysteresis of the UVLO
circuitry (nominally 400 mV for the A8582) at maximum loading
and minimum input voltage.
The input capacitors must deliver the rms current according to
equation 12, where the duty cycle, D (VOUT + Vf
) / (VIN + Vf
)
and Vf is the forward voltage of the asynchronous diode (D1 in
figure 1):
=
Irms IO
D×(1–
D)
(12)
Figure 13 shows the normalized input capacitor rms current
versus duty cycle. To use this graph, simply find the operational
duty cycle (D) on the x axis and determine the input/output
current multiplier on the y axis. For example, at a 20% duty
cycle, the input/output current multiplier is 0.400. Therefore,
if the regulator is delivering 2.0 A of steady-state load current,
the input capacitor(s) must support 0.400 × 2.0 A or 0.8 Arms
. A
single capacitor may support the rms input current requirement or
several capacitors may have to be paralleled. Ceramic capacitors
can deliver quite a bit of current but their total capacitance will be
relatively low. For example, a 4.7 F, 16 V, 1206, X7R ceramic
capacitor can easily deliver 3 to 4 Arms
.
Electrolytic capacitors can typically deliver 100 to 500 mArms of
current so 2 or 3 of these may be required to support the ripple
current. Electrolytic capacitors will typically offer much more
capacitance than the same quantity of ceramic capacitors. So,
electrolytic capacitors are typically able to provide more current
over extended periods of time where VIN would otherwise droop.
However, ceramic capacitors have very low ESR and inductance,
so they are best for filtering the high frequency switching noise.
A good design will employ both types of capacitors with the
ceramic capacitors placed closest to the input pin of the A8582.
The input capacitors must limit the voltage deviations at the VIN
pin to something significantly less than the A8582 UVLO hyster-
esis during maximum load and minimum input voltage. Equation
13 allows us to calculate the minimum input capacitance:
CIN
IOUT ×
D
×
(1 – D
)
fSW(MIN) × (VIN(MIN)IOUT × ESRCIN)
(13)
Where VIN(MIN) is chosen to be much less than the hyster-
esis of the VIN UVLO comparator (VIN(MIN) 100 mV is
Figure 13. Normalized input capacitor ripple current versus duty cycle
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0 1020304050
Duty Cycle, D (%)
Irms / IOUT (A)
60 70 80 90 100