1
Radiation Hardened High-Speed, Dual Output PWM
HS-1825ARH, HS-1825AEH
The Radiation Hardened HS-1825ARH, HS-1825AEH Pulse
Width Modulator is designed to be used in high frequency
switched-mode power supplies and can be used in either
current-mode or voltage-mode. It is well suited for single-ended
boost converter applications.
Device features include a precision voltage reference, low
power start-up circuit, high frequency oscillator, wide-band
error amplifier, and fast current-limit comparator. The use of
proprietary process capabilities and unique design techniques
results in fast propagation delay times and high output current
over a wide range of output voltages.
Constructed with the Intersil Rad Hard Silicon Gate (RSG)
Dielectric Isolation BiCMOS process, the HS-1825ARH,
HS-1825AEH has been specifically designed to provide highly
reliable performance when exposed to harsh radiation
environments.
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HS-1825ARH,
HS-1825AEH are contained in SMD 5962-99558. That
document may be easily downloaded from our website.
www.intersil.com/
Features
Electrically Screened to DLA SMD # 5962-99558
QML Qualified per MIL-PRF-38535 Requirements
Radiation Environment
- Maximum Total Dose. . . . . . . . . . . . . . . . . . . . 300 krad(SI)
- Vertical Architecture Provides Low Dose Rate Immunity
- DI RSG Process Provides Latch-Up Immunity
Low Start-Up Current . . . . . . . . . . . . . . . . . . . . . . . 100µA (Typ)
Fast Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . 80ns (Typ)
12V to 30V Operation
1A (Peak) Dual Output Drive Capability
•5.1V Reference
•Undervoltage Lockout
•Programmable Soft-Start
Switching Frequencies to 500kHz
Latched Overcurrent Comparator with Full Cycle Restart
Programmable Leading Edge Blanking Circuit
Applications
Current or Voltage Mode Switching Power Supplies
Motor Speed and Direction Control
Pin Configuration
HS-1825ARH, HS-1825AEH
SBDIP (CDIP2-T16) AND FLATPACK (CDFP4-F16)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
INV
NON-INV
E/A OUT
CLOCK
RT
CT
SOFT START
RAMP
VREF 5.1V
OUTPUT B
VC
POWER GND
OUTPUT A
GND
ILIM/SD
VCC
NOTE: Grounding the Soft-Start pin does not inhibit the outputs. The outputs may be inhibited by applying >1.26V to the ILIM/SD pin.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2002, 2005, 2008, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
May 10, 2012
FN4561.9
HS-1825ARH, HS-1825AEH
2FN4561.9
May 10, 2012
Ordering Information
ORDERING NUMBER
INTERNAL
MKT. NUMBER
(Note) TEMP. RANGE (°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
5962F9955801V9A HS0-1825ARH-Q -50 to +125
5962F9955802V9A HS0-1825AEH-Q -50 to +125
HS0-1825ARH/Sample HS0-1825ARH/Sample -50 to +125
5962F9955801VEC HS1-1825ARH-Q -50 to +125 16 Ld SBDIP D16.3
5962F9955802VEC HS1-1825AEH-Q -50 to +125 16 Ld SBDIP D16.3
5962F9955801QEC HS1-1825ARH-8 -50 to +125 16 Ld SBDIP D16.3
5962F9955801VXC HS9-1825ARH-Q -50 to +125 16 Ld Flatpack K16.A
5962F9955802VXC HS9-1825AEH-Q -50 to +125 16 Ld Flatpack K16.A
5962F9955801QXC HS9-1825ARH-8 -50 to +125 16 Ld Flatpack K16.A
HS1-1825ARH/Proto HS1-1825ARH/Proto -50 to +125 16 Ld SBDIP D16.3
HS9-1825ARH/Proto HS9-1825ARH/Proto -50 to +125 16 Ld Flatpack K16.A
NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with
both SnPb and Pb-free soldering operations.
Typical Performance Curves
FIGURE 1. OSCILLATOR FREQUENCY vs Rt AND CtFIGURE 2. MAXIMUM DUTY CYCLE vs Rt
110100
10
100
1k
10k
Rt TIMING RESISTANCE (kΩ)
FREQUENCY (kHz)
C220pFC470pF
C1000pF
C2200pF C4700pF
C10nF
C22nF
1 10 100
50
60
70
80
90
100
DMAX (%)
Rt TIMING RESISTANCE (kΩ)
DMAX
HS-1825ARH, HS-1825AEH
3
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4561.9
May 10, 2012
For additional products, see www.intersil.com/product_tree
Die Characteristics
DIE DIMENSIONS
4710µm x 3570µm (185 mils x 140 mils)
Thickness: 483µm ±25.4µm (19 mils ±1 mil)
INTERFACE MATERIALS
Glassivation
Type: PSG (Phosphorous Silicon Glass)
Thickness: 8.0kÅ ±1.0kÅ
Top Metallization
Type: ALSiCu
Thickness: 16.0kÅ ±2kÅ
Substrate
Radiation Hardened Silicon Gate,
Dielectric Isolation
Backside Finish
Silicon
ASSEMBLY RELATED INFORMATION
Substrate Potential
Unbiased (DI)
ADDITIONAL INFORMATION
Worst Case Current Density
<2.0 x 105 A/cm2
Transistor Count
225
Metallization Mask Layout HS-1825ARH,HS-1825AEH
NOTES:
1. This is the oscillator ground (OSCGND) bond pad and must be
connected to GND.
2. PGND and VC each require two bond pad connections.
PGND (12)
OUTA (11)
GND (10)
OSCGND
ILIM (9)
SS (8)
RAMP (7)
CT (6)
RT (5)
(1) IN-
(16) VREF
(15) VCC
(14) OUTB
(13) VC
(3) EAOUT
(4) CLK/LEB
(2) IN+
VC (13)
(12) PGND
(NOTE 2)
(NOTE 2)
(NOTE 1)
(NOTE 2)
(NOTE 2)