TDC1035 try Monolithic Peak Digitizer 8-Bit, 30ns Full Response Peak Width The TDC1035 is a unique variant of the full-parallel (flash) analog-to-cigital converter, capable of capturing the maximum peak amplitude of one or more pulses applied to its input between asynchronous reset pulses. Multiple peak read operations can be performed between resets. Peaks are detected digitally, so operation is stable and predictable. Packaged in a 24 pin CERDIP, the TDC1035 features lower power consumption and smaller size than an analog peak detector/ADC combination. All digital inputs and outputs are TTL compatible, and all outputs are registered and three-state. Features 8-Bit Resolution Full DC Linearity For Pulses 30ns Wide Does Not Require Analog Peak-Hold Circuit Continuous Peak Capture Between Resets Multiple Read Operations Between Resets 1/2 LSB Linearity Narrow Ambiguity Region Around Reset Detects Pulses As Small As 12ns Wide e Guaranteed Monotonic Selectable Data Format @ Available In A 24 Pin CERDIP Package 1.0W Power Consumption e Three-State Registered Outputs Applications e Instrumentation Radar Pulse Classification Electronic Countermeasures Radiation Measurement Functional Block Diagram Vat R/2 Vin a p oS a 2 ry ay i WA A We? Vv! by A mm Qo =)] RESET < z gq CLK Tso 8 BIT OUTPUT 77 TRW LSI Products Inc. PO. Box 2472 La Jolla, CA 92038 Phone: (619) 457-1000 FAX: (619) 455-6314 TRW Ine. 1990 40606460 Rev. A-11/90 Printed in the U.S.A.a, awe TDC1035 71try Pin Assignments oe D, (MsB) 1[] 24 MINV db, 2f 123 OE pb; 3[] 122 Rp pb, f M21 Agnp Denn 5] [120 Ryip Vee 6 119 Vy cuK 7[] 118 Agnp Voc 8] Hi? Ry Vee 9f] [16 RESET Deno of] 1145 Dg (LSB) unv 1{] 14 Dy ps 2] 13. Dg 21220A 24 Pin CERDIP B7 Package Functional Description General Information The TDC1035 peak cetector operates on ground- referenced negative-going signals. Within tap nanoseconds after the rising edge of the clock signal CLK, it outputs the most negative value reached since the previous RESET pulse. The active-HIGH RESET control is independent of CLK, but may be connected to CLK to provide a single-contro! peak detector. Multiple output cycles are permitted between reset operations. The TDC1035 contains parallel array of comparators, an array of latches, and an encoder which outputs the location of the highest-valued latch which is set. The TDC1035's response characteristics are determined by its comparator array. A comparator's response time is determined by the degree of overdrive, since the output changes only when the area above threshold reaches a characteristic value. Therefore, the digitization accuracy of a pulses peak value depends on the shape of the pulse. To permit accurate, repeatable characterization, the TDC1035 is tested with a slew-rate limited square pulse. It will digitize (to its OC accuracy) the peak value of a square pulse having a minimum duration of 3O0ns. The accuracy degrades gracefully as the duration decreases from 30 down to 12ns, where it understates the applied amplitude by 15% (Figure 7). Production characterization of the TDC1035 uses square pulses with controlled rise and fall times of 8ns. 78 Performance of the TDC1035 with other pulse shapes {such as Gaussian or bandwidth-limited square pulse) can be estimated by applying an energy above threshold model, with area of 120 picoVolt-seconds. The operation of all asynchronous sequential logic circuits involves some temporal ambiguity. The most common form of this ambiguity, metastability, occurs in data syn- chronizers. In a peak digitizer such as the TDC1035, this ambiguity comes in the form of periods during which the accuracy of the measurement of a pulse may be affected, or the pulse may not even be detected. There is a 10ns (tap) ambiguity period after the falling edge of the RESET signal, during which detection or accuracy of detection of any pulse is not guaranteed. There is also a region of 40ns (tpc} before the rising edge of the (output) clock (CLK) where a pulse may be missed or detected inaccurately. These regions are shown in the timing diagrams, Figures 1 and 2. During the latter period, if the input signal increases to a new peak larger than the previously-latched value, the value loaded into the output register may be incorrect (and will mast likely be zero}; nonetheless, the peak detection latches will hold the (correct) new peak value. As shown in Figure 3, the TDC1035s comparator inputs have emitter-follower buffers, which limit the permissible input signal slew rate to 250V/ys. This corresponds to a full-scale transition time of 8ns. TRW LSI Products Inc.TDC1035 7mItvy Power The TDC1035 operates fram two supply voltages: +5.0V and 5.2V. The current return for the positive supply is DGnp. and the return for the negative (analog) supply is AGNp- All power and ground pins MUST be connected. Reference The reference for the TDC1035 is a negative voltage applied across a chain of 255 resistors. The top of this chain is connected to the RT pin, and the voltage applied to the RT pin (VpT} should be within 0.1V of the analog ground. Note that the difference between the voltage applied to the pin and the voltage at the reference chain is the offset specification (Egy and Egp). The bottom of the reference resistor chain is connected to the RB pin, and the voltage applied to the Rp pin (Vpp} should be between 1.8 and 2.2V negative with respect to the RT pin for full-specification operation. Reduced reference voltage operation is possible at reduced accuracy {for example, for generating a non- linear transfer function). The RTRp reference source should be able to deliver at least 45mA. Due to the variation in the reference currents with clock and input signals, RT and Rp should be connected to circuit nodes with a low impedance to ground. For circuits in which the reference is not varied at a high rate, a bypass capacitor to ground is recommended. If the reference inputs are exercised dynamically (e.g., for AGC or nonlinear operation), a low-impedance reference source is required. The reference voltages may be varied dynamically; contact the factory for information on limitations when the device is used in this mode. The performance of the TDC1035 is specified with DC references of VaT=0.0V and Vap= 2.0V. Control Two function contro! pins, MINV and LINV, are provided. These names stand for active-LOW Most significant bit INVert and active-LOW Least significant bits [NVert, respectively. These controls are for DC (ie., steady- state), not dynamic, use. They permit the output coding to be either straight binary or offset two's complement, in either true or inverted sense, according to the Output Coding Table. A single output state control pin, OE, Is provided. The three-state outputs may be placed in a high-impedance state by applying a logic HIGH to the OE control pin, and enabled by driving OF LOW. TRW LSI Products Inc. The function control pins may be tied to Vcc for a logic HIGH, and Denp for a fogic LOW; however, a 2.2 kOhm pull-up resistor is preferred over direct connection to Vcc. If a pull-up resistor is not used, the absolute maximum voltage rating for the part becomes that of the TTL input, 5.5V, rather than the higher value for the Vcc terminal. Command Two pins, RESET and CLK, control the TDC1035. When brought HIGH, the level-sensitive RESET contro! resets the peak-storing latches. The edge-sensitive CLK control causes the peak value to be loaded into the output register when a rising-edge (LOW-to-HIGH} signal is applied. As noted above, there is a data ambiguity period associated with the operation of each of these inputs. Analog Input Although the TDC1035s 255 comparators have emitter- follower isolated inputs, the input impedance can vary up to 25 percent with the signal level, as comparator input transistors switch on or off. As a result, for optimal performance, the source impedance of the driving device must be less than 25 Ohms. The input signal will not damage the TDC1035 if it remains in the range Vee0.5V to VaGND+O.5V. If the input signal stays between the Vat and Vpp reference voltages, the 8-bit digital equivalent of the most negative voltage reached will be latched into the array of latches, subject to the dynamic effects mentioned above. A transient more negative than Vpp will cause a full-scale output tog after the CLK line rises. Outputs The outputs of the TDC1035 are TTL compatible, capable of driving four low-power Schottky TTL (54LS/74LS) unit loads or the equivalent. The outputs hold the previous data a minimum time ty after the rising edge of the CLK input, and are guaranteed to have the new output value after a maximum time tpg. Under light DC load conditions (such as driving CMOS loads or base-input low-power Schottky such as the 7415374) 2.2k pull-up resistors to +5.0V are recommended. 79TDC1035 7 It Package Interconnections Name Function Value B7 Package Pins Vec Positive Supply Voltage +5.0V Vee Negative Supply Voltage 5.2V 6,9 Denp Digital Ground 0.0V 5, 10 AGND Analog Ground 0.0V 18, 21 Rr Reference Resistor, Top 0.0V 7 Rp Reference Resistor, Bottom 2.0V 22 MINV MSB Invert TTL (Active LOW) 24 LINV LSB Invert TTL (Active LOW) 11 OE Output Enable TTL (Active LOW) 23 RESET Resets Peak Value to Zero TTL (Active HIGH) 16 CLK Loads Qutput Register TTL (Rising Edge} 7 Vin Analog Input Signal 0.0V to 2.0V 19 Dy MSB Output TTL 1 Dg TTL 2 Dg TTL 3 Dy TTL 4 Ds TTL 12 Dg TTL 13 07 TTL 14 Dg LSB Output TTL 15 Figure 1. Timing with Separate RESET and CLK tap ale |e ANALOG INPUT =k RESET jn mal x tewan | | pune > | OOK PEAKN 7 tho < | tno 21222A FULL SCALE 1 CLK DATA PEAK N-4 Figure 2. Timing with Common RESET and CLK tap Bulee PCL ANALOG F SAK + FULL SCALE INPUT | RESET yn sl 1 & CLK > tpwur, >| ie tpwHe |) tho tbo 21223A TRW LSI Products Inc.TDC1 Tati 035 sityy Figure 3. Simplified Analog Input Equivalent Circuits VinO- rm | r C= op Rin Vin V EEA Vee Cyy IS ANONLINEAR JUNCTION CAPACITANCE v T N Vpp SA VOLTAGE EQUAL TO THE VOLTAGE ON PIN Rg nerenieNce Vee EE RESISTOR EE CHAIN 211918 Figure 4. Digital Input Equivalent Circuit Figure 5. Output Circuits Voc Vee --- 7 t Vee B10 30K 20K = 1600 < To ] OUTPUT INPUT --- PIN __ 40pF DIODES --- OUTPUT P T {N3062 = 21188A ~ LoaD1 + > 211B9A Figure 6. Recommended Input Circuit Figure 7. Variation of Accuracy as a Function of Width, Square Input Pulse 750 i) TDC1035 8 VV TIN 3 VIDEO 16pF < | OPERATIONAL T 57 4 AMPLIFIER = 21224A 8 a _ a 6 7 ~ / e a 5 1 jt jt jt do 10 15 20 25 30 PULSE WIDTH ( ns at 50%) 212254 TRW LSI Products Inc. 81TDC1035 7 Itly Output Coding Binary Offset Two's Complement Range True Inverted True Inverted 2.0000V FS 2.0480V FS MINV = 0 0 1 Step 7.8431mV Step 8.000mV Step TINV = 1 0 1 0 000 0.0000V 0.0000V ocooo00e 14411111 10000000 01171711 001 0.0078V 0.0080V 00000001 11114110 10000001 01111110 e e es e e e e e e * e e e * e e e e e e 127 ~0.9922V ~1.0160V 01141111 10000000 14111114 00000000 4128 1.0000V 1.0240V 10000000 01111171 0000000 141191111 129 ~ 1.0078V 1.0320V 10000001 01111110 00000001 14111110 e e e e e e cd e e e e e es e e e e e 254 1.9844V 2.0240V 11111110 00000001 01111110 10000001 255 1.9922V 2.0320V 14999911 00000000 01111111 10000008 Absolute maximum ratings (beyond which the device may be damaged} Supply Voltages Vcc {measured to Denyp) ~0.5 to +7.0V Veg (measured to Deno! ~7.0 to +0.5V AGnp (measured to Deno! 0.5 to +0.5V Input Voltages RESET, CLK, OE, MINV, LINV (measured to Agyp) 0.5 to +5.5V Vin: Vat Vpp (measured to Agno! (Veg 0.5) to +0.5V Vat (measured to Vag} -2.2 to +2.2V Outputs Applied voltage (measured to Dgnp) 0.5 to +0.5V2 Applied current (externally forced) 1.0 to 6.0mA 34 Short-circuit duration (single output HIGH to shorted to ground} 1 Second Temperature Operating, ambient 55 to + 125C junction +179C Lead, soldering (10 seconds) +300C Storage 65 to +150C Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. 82 Functional operation under any of these conditions is NOT implied. Device performance is guaranteed only if specified operating conditions are met. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as positive current flowing into the device. TRW LSI Products Inc.TDC1035 7rtw f wv Operating conditions Temperature Range Standard Extended Parameter Min Nom Max Min Nom Max Units Vec Positive Supply Voltage 4.75 5.0 5.25 4.50 5.0 5.5 V VEE Negative Supply Voltage 4.90 ~5.2 5.5 -4.90 5.2 -55 V VaAGND Analog Ground Voltage -0.1 0.0 0.1 0.1 0.0 0.1 V tpWHR Reset Minimum Pulse Width, HIGH 20 20 ns tpwe CLK Minimum Pulse Width, LOW 20 20 ns tpwue CLK Minimum Pulse Width, HIGH 20 20 ns SR Input Signal Siew Rate 250 250 VipS Vit Input Voltage, Logic LOW 0.8 0.8 V Vin Input Voltage, Logic HIGH 2.0 2.0 Vv lon Qutput Current, Logic LOW 40 40 | mA on Output Current, Logic HIGH 400 400 pA VRT Reference Voltage, Top -0.1 0.0 0.1 -0.1 0.0 0.1 Vv Vap Reference Voltage, Bottom 1.8 ~2.0 -2.2 -1.8 -2.0 -2.2 Vv VatVap Reference Valtage Span 18 2.0 22 18 2.0 2.2 Vv VIN Input Voltage Range Vet Vee VaT Vep Vv Ta Ambient Temperature, Still Air 0 70 C Te Case Temperature 55 +125 C Electrical characteristics within specified operating conditions Temperature Range Standard Extended Parameter Test Conditions Min | Max | Min | Max | Units Ic Positive Supply Current Vec = Max, Static 35 35 | mA lee Negative Supply Current Veg =Max, Static 160 160 | mA Ipep Reference Current VeTVag=Nom 35 35 {| mA Reece Reference Resistance Total, Rt to Rg 57 57 Ohms Rin Input Equivalent Resistance (DC) Vet. Vap=Nom, Vin=Vpp 50 50 kOhms Ciny Input Capacitance, Analog Vet, Vagp=Nom, Vin=Vag 50 50 | pF cp [nput Constant Bias Current Veg = Max 250 350 | uA Wie Input Current Logic LOW Veco= Max, Vp =0.4V 500 500 J vA liq Input Current Logic HIGH Voc = Max, Vy =2.4V 50 50 | #A lim Input Current, Vin = Max Vec= Max, Vy =5.5V 1 1 mA Ioz_ Hi-Z Output Leakage Current, Output LOW | Vcc=Max, Vg=0V -30 30 | -30 30 7 pA lozy Hi-Z Output Leakage Current, Gutput HIGH | Voc=Max, Vp=5V -30 30 | -30 30 | A Iopg Short-Circuit Output ! Vec = Max, Output HIGH, one 50 ~50 f| mA output tied to Dgnjp for 1 second. Vo_ Output Voltage, Logic LOW Vee = Max, Ip, = Max 0.5 O05, V VoH Gutput Voltage, Logic HIGH Voc = Min, Igy =Max 2.4 24 Vv Ci Input Capacitance, Digital 10 10 pF Note: 1. Worst case, all digital inputs and outputs LOW. TRW LSI Products Inc. 83TDC1035 Trew fz vw Switching characteristics within specified operating conditions Temperature Range Standard Extended Parameter Test Conditions Min Max Min Max Units tpc CLK Setup Time Vec= Min, Veg=Min, Load 1 30 30 ns trp RESET Delay Vec= Min, Vee=Min, Load 1 5 5 ns too Output Delay Vec=Min, Veg=Min, Load 1 35 35 ns tuo Output Hold Time Vec=Min, Vee =Min, Load 1 5 5 ns tpis Output Disable Time Vec=Min, Veg=Min, Load 1 20 20 ns tena Output Enable Time Vec=Min, Veg=Min, Load 1 70 90 ns Note: 1. tgp and tpc are the guaranteed maximum lengths of the ambiguity periods. System performance characteristics within specified operating conditions Temperature Range Standard Extended Parameter Test Conditions Min Max Min Max | Units Ey) Linearity Error, Integral, Independent Vet. Vap=Nom 0.2 0.2 %FS Eip __Linearity Error, Differential Vet Vrp=Nom 0.2 0.2 %FS CS Code Size Vat. Vag=Nom 30 170 30 170 % Nominal twin Analog Input Pulse Width Square Pulse, 15% Accuracy 12 12 ns DC Accuracy 30 30 ns Egy Offset Error, Top Vin=Vrt +8 +8 mV Egp Offset Error, Bottom Vin=Yrp +15 15 mV Teg Offset Error, Temperature Coefficent Vat: Veep Vee: Vee=Nom +20 +20 pViC Applications Discussion Under certain conditions, the real component of the input impedance may go negative at frequencies near 100MHz. To prevent oscillation at the input signal port, TRW recommends connecting the input signal to the TDC1035 via a series-connected resistor of at least 10 Ohms located close to the device. Further, if the signal bandwidth is not already limited so that the input slew rate limit is not exceeded, external circuitry is also recommended.: The circuit shown in Figure 6 accomplishes both goals. Ordering Information 84 Product Temperature Range Screening Package Package Number Marking TDC1035B7C STDTp =0C to 70C Commercial 24 Pin CERDIP 1035B7C TDC1035B7V EXTTp= 59C to 125C MIL-STD-883 24 Pin CERDIP 1035B7V All parameters in this specification are guaranteed by design, characterization, sample testing or 100% testing, as appropriate. TRW reserves the right to change products and specifications without notice. This information does not convey any license under patent rights af TRW Inc. or others. Life Support Policy TRW LS! Products Inc. components are not designed for use in life support applications, wherein a failure ar malfunction of the component can reasonably be expected to result in personal injury. The user of TRW LSI Products Inc. components in life support applications assumes all risk of such use and indemnifies TRW LS! Products Inc. against all damages. TRW LSI Products Inc