54AC/74AC161 # 54ACT/74ACT161 Synchronous Presettable Binary Counter General Description Features The 'AC/'ACT161 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The 'AC/ 'ACT161 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. Y Y Y Y Y Y Y ICC reduced by 50% Synchronous counting and loading High-speed synchronous expansion Typical count rate of 125 MHz Outputs source/sink 24 mA 'ACT161 has TTL-compatible inputs Standard Military Drawing (SMD) 'AC161: 5962-89561 'ACT161: 5962-89848 Logic Symbols Connection Diagrams Pin Assignment for DIP, Flatpak and SOIC IEEE/IEC TL/F/9931-1 TL/F/9931 - 3 TL/F/9931 - 2 Pin Names CEP CET CP MR P0 - P3 PE Q0 - Q3 TC Pin Assignment for LCC Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Asynchronous Master Reset Input Parallel Data Inputs Parallel Enable Inputs Flip-Flop Outputs Terminal Count Output TL/F/9931 - 4 TRI-STATEE is a registered trademark of National Semiconductor Corporation. FACTTM is a trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9931 RRD-B30M75/Printed in U. S. A. 54AC/74AC161 # 54ACT/74ACT161 Synchronous Presettable Binary Counter April 1993 Functional Description period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. Logic Equations: Count Enable e CEP # CET # PE TC e Q0 # Q1 # Q2 # Q3 # CET The 'AC/'ACT161 count in modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the '161) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset, parallel load, count-up and hold. Five control inputsMaster Reset, Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The 'AC/'ACT161 use D-type edge-triggered flip-flops and changing the PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Mode Select Table PE CET CEP X L H H H X X H L X X X H X L Action on the Rising Clock Edge (L) Reset (Clear) Load (Pn x Qn) Count (Increment) No Change (Hold) No Change (Hold) H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial State Diagram Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle requires 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock TL/F/9931 - 5 TL/F/9931 - 8 FIGURE 1. Multistage Counter with Ripple Carry TL/F/9931 - 9 FIGURE 2. Multistage Counter with Lookahead Carry 2 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. TL/F/9931 - 6 Block Diagram 3 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI e b0.5V VI e VCC a 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO e b0.5V VO e VCC a 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP PDIP Supply Voltage (VCC) 'AC 'ACT Input Voltage (VI) b 0.5V to a 7.0V b 20 mA a 20 mA 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC Output Voltage (VO) Operating Temperature (TA) 74AC/ACT 54AC/ACT b 0.5V to VCC a 0.5V b 20 mA a 20 mA b 40 C to a 85 C b 55 C to a 125 C Minimum Input Edge Rate (DV/Dt) 'AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (DV/Dt) 'ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V b 0.5V to VCC a 0.5V g 50 mA g 50 mA b 65 C to a 150 C 125 mV/ns 125 mV/ns 175 C 140 C Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT TM circuits outside databook specifications. DC Characteristics for 'AC Family Devices Symbol Parameter VCC (V) 74AC 54AC 74AC TA e a 25 C TA e b 55 C to a 125 C TA e b 40 C to a 85 C Typ VIH VIL VOH IIN Conditions Guaranteed Limits Minimum High Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT e 0.1V or VCC b 0.1V Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT e 0.1V or VCC b 0.1V Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 2.9 4.4 5.4 V 2.56 3.86 4.86 2.4 3.7 4.7 2.46 3.76 4.76 V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V 3.0 4.5 5.5 0.36 0.36 0.36 0.5 0.5 0.5 0.44 0.44 0.44 V 5.5 g 0.1 g 1.0 g 1.0 mA 3.0 4.5 5.5 VOL Units Maximum Low Level Output Voltage Maximum Input Leakage Current 3.0 4.5 5.5 0.002 0.001 0.001 *All outputs loaded; thresholds on input associated with output under test. 4 IOUT e b50 mA *VIN e VIL or VIH b 12 mA b 24 mA IOH b 24 mA IOUT e 50 mA *VIN e VIL or VIH 12 mA IOL 24 mA 24 mA VI e VCC, GND DC Characteristics for 'AC Family Devices (Continued) Symbol Parameter VCC (V) 74AC 54AC 74AC TA e a 25 C TA e b 55 C to a 125 C TA e b 40 C to a 85 C Typ Minimum Dynamic Output Current IOLD IOHD ICC Maximum Quiescent Supply Current Units Conditions VOLD e 1.65V Max Guaranteed Limits 5.5 50 75 mA 5.5 b 50 b 75 mA VOHD e 3.85V Min mA VIN e VCC or GND 5.5 4.0 80.0 40.0 Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ ICC for 54AC 3.0V are guaranteed to be less than or equal to the respective limit @ 25 C is identical to 74AC @ @ 5.5V VCC. 25 C. DC Characteristics for 'ACT Family Devices 74ACT 54ACT 74ACT TA e a 25 C TA e b 55 C to a 125 C TA e b 40 C to a 85 C Parameter VCC (V) VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 V VOUT e 0.1V or VCC b 0.1V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 0.8 0.8 V VOUT e 0.1V or VCC b 0.1V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 4.4 5.4 V 3.86 4.86 3.70 4.70 3.76 4.76 V 0.1 0.1 0.1 0.1 0.1 0.1 V 4.5 5.5 0.36 0.36 0.50 0.50 0.44 0.44 V g 0.1 g 1.0 g 1.0 mA VI e VCC, GND 1.6 1.5 mA VI e VCC b 2.1V Symbol Typ 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 IIN Maximum Input Leakage Current 5.5 ICCT Maximum ICC/Input 5.5 IOLD Minimum Dynamic Output Current IOHD ICC Maximum Quiescent Supply Current 0.001 0.001 0.6 IOUT e b50 mA *VIN e VIL or VIH b 24 mA IOH b 24 mA IOUT e 50 mA *VIN e VIL or VIH 24 mA IOL 24 mA 5.5 50 75 mA VOLD e 1.65V Max 5.5 b 50 b 75 mA VOHD e 3.85V Min 80.0 40.0 mA VIN e VCC or GND 5.5 4.0 Maximum test duration 2.0 ms, one output loaded at a time. @ Conditions Guaranteed Limits *All outputs loaded; thresholds on input associated with output under test. Note: ICC for 54ACT Units 25 C is identical to 74ACT @ 25 C. 5 AC Electrical Characteristics Symbol Parameter VCC* (V) 74AC 54AC 74AC TA e a 25 C CL e 50 pF TA e b55 C to a 125 C CL e 50 pF TA e b40 C to a 85 C CL e 50 pF Min Min Min Typ fmax Maximum Count Frequency 3.3 5.0 70 110 111 167 tPLH Propagation Delay CP to Qn (PE Input HIGH or LOW) 3.3 5.0 2.0 1.5 7.0 5.0 12 9.0 1.0 1.0 14.0 10.0 1.5 1.0 13.5 9.5 ns tPHL Propagation Delay CP to Qn (PE Input HIGH or LOW) 3.3 5.0 1.5 1.5 7.0 5.0 12 9.5 1.0 1.0 14.0 10.0 1.5 1.5 13 10 ns tPLH Propagation Delay CP to TC 3.3 5.0 3.0 2.0 9 6 15 10.5 3.0 3.0 18.5 13.0 2.5 1.5 16.5 11.5 ns tPHL Propagation Delay CP to TC 3.3 5.0 3.5 2.0 8.5 6.5 14 11 1.0 1.0 17.5 13.0 2.5 2.0 15.5 11.5 ns tPLH Propagation Delay CET to TC 3.3 5.0 2.0 1.5 5.5 3.5 9.5 6.5 1.0 1.0 13.0 8.5 1.5 1.0 11 7.5 ns tPHL Propagation Delay CET to TC 3.3 5.0 2.5 2.0 6.5 5 11 8.5 1.0 1.0 13.5 10.5 2.0 1.5 12.5 9.5 ns tPHL Propagation Delay MR to Qn 3.3 5.0 2.0 1.5 6.5 5.5 12 9.5 1.0 1.0 14.5 10.5 1.5 1.5 13.5 10 ns tPHL Propagation Delay MR to TC 3.3 5.0 3.5 2.5 10 8.5 15 13 1.0 1.0 18.5 14.0 3.0 2.5 17.5 13.5 ns *Voltage Range 3.3 is 3.3V g 0.3V Voltage Range 5.0 is 5.0V g 0.5V 6 Max Max Units 55 80 Max 60 95 MHz AC Operating Requirements 74AC 54AC 74AC TA e a 25 C CL e 50 pF TA e b55 C to a 125 C CL e 50 pF TA e b40 C to a 85 C CL e 50 pF Parameter VCC* (V) ts Setup Time, HIGH or LOW Pn to CP 3.3 5.0 6.0 3.5 13.5 8.5 16.0 10.5 16 10.5 th Hold Time, HIGH or LOW Pn to CP 3.3 5.0 b 7.0 b 4.0 b1 0.5 1.5 b 0.5 0 ts Setup Time, HIGH or LOW PE to CP 3.3 5.0 6.5 4.0 11.5 7.5 15.0 10.5 14 8.5 ns th Hold Time, HIGH or LOW PE to CP 3.3 5.0 b 6.0 b 3.5 0 0.5 b 1.0 0.0 0 1 ns ts Setup Time, HIGH or LOW CEP or CET to CP 3.3 5.0 3.0 2.0 6.0 4.5 7.5 5.5 7 5 ns th Hold Time, HIGH or LOW CEP or CET to CP 3.3 5.0 b 3.5 b2 0 0 2.0 2.0 0 0.5 ns tw Clock Pulse Width (Load) HIGH or LOW 3.3 5.0 2.0 2.0 3.5 2.5 5.0 5.0 4 3 ns tw Clock Pulse Width (Count) HIGH or LOW 3.3 5.0 2.0 2.0 4.0 3.0 5.0 5.0 4.5 3.5 ns tw MR Pulse Width, LOW 3.3 5.0 3.0 2.5 5.5 4.5 5.0 5.0 7.5 6.0 ns trec Recovery Time MR to CP b2 b1 b 0.5 1.5 2.0 0 0.5 ns Symbol Typ Units Guaranteed Minimum 0 ns ns 0 *Voltage Range 3.3 is 3.3V g 0.3V Voltage Range 5.0 is 5.0V g 0.5V AC Electrical Characteristics Symbol Parameter VCC* (V) 74ACT 54ACT 74ACT TA e a 25 C CL e 50 pF TA e b55 C to a 125 C CL e 50 pF TA e b40 C to a 85 C CL e 50 pF Min Typ 5.0 115 125 Propagation Delay CP to Qn (PE Input HIGH or LOW) 5.0 1.5 5.5 9.5 1.0 10.5 1.5 10.5 ns tPHL Propagation Delay CP to Qn (PE Input HIGH or LOW) 5.0 1.5 6.0 10.5 1.0 10.5 1.5 11.5 ns tPLH Propagation Delay CP to TC 5.0 2.0 7.0 11.0 1.0 14.0 1.5 12.5 ns tPHL Propagation Delay CP to TC 5.0 1.5 8.0 12.5 1.0 12.5 1.5 13.5 ns tPLH Propagation Delay CET to TC 5.0 1.5 5.5 8.5 1.0 9.5 1.5 10.0 ns tPHL Propagation Delay CET to TC 5.0 1.5 6.5 9.5 1.0 9.5 1.5 10.5 ns tPHL Propagation Delay MR to Qn 5.0 1.5 6.0 10.0 1.0 10.0 1.5 11.0 ns tPHL Propagation Delay MR to TC 5.0 2.5 8.0 13.5 1.0 11.5 2.0 14.5 ns fmax Maximum Count Frequency tPLH Max Min Max 85 *Voltage Range 5.0 is 5.0V g 0.5V 7 Min Units Max 100 MHz AC Operating Requirements Symbol Parameter VCC* (V) 74ACT 54ACT 74ACT TA e a 25 C CL e 50 pF TA e b55 C to a 125 C CL e 50 pF TA e b40 C to a 85 C CL e 50 pF Typ Units Guaranteed Minimum ts Setup Time, HIGH or LOW Pn to CP 5.0 4.0 9.5 13.0 11.5 ns th Hold Time, HIGH or LOW Pn to CP 5.0 b 5.0 0 0 0 ns ts Setup Time, HIGH or LOW PE to CP 5.0 4.0 8.5 11.0 9.5 ns th Hold Time, HIGH or LOW PE to CP 5.0 b 5.5 b 0.5 0 b 0.5 ns ts Setup Time, HIGH or LOW CEP or CET to CP 5.0 2.5 5.5 7.0 6.5 ns th Hold Time, HIGH or LOW CEP or CET to CP 5.0 b 3.0 0 0.5 0 ns tw Clock Pulse Width, (Load) HIGH or LOW 5.0 2.0 3.0 5.0 3.5 ns tw Clock Pulse Width, (Count) HIGH or LOW 5.0 2.0 3.0 5.0 3.5 ns tw MR Pulse Width, LOW 5.0 3.0 3.0 6.5 7.5 ns trec Recovery Time MR to CP 5.0 0 0 0.5 0.5 ns *Voltage Range 5.0 is 5.0V g 0.5V Capacitance Typ Units Conditions CIN Symbol Input Capacitance Parameter 4.5 pF VCC e OPEN CPD Power Dissipation Capacitance 45.0 pF VCC e 5.0V Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74AC 161 P Temperature Range Family 74AC e Commercial 54AC e Military 74ACT e Commercial TTL-Compatible 54ACT e Military TTL-Compatible C QR Special Variations X e Devices shipped in 13x reels QR e Commercial grade device with burn-in QB e Military grade device with environmental and burn-in processing shipped in tubes Temperature Range C e Commercial (b40 C to a 85 C) M e Military (b55 C to a 125 C) Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Ceramic Chip Carrier (LCC) S e Small Outline (SOIC) 8 9 Physical Dimensions inches (millimeters) 20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 16 Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 10 Physical Dimensions inches (millimeters) (Continued) 16 Lead Small Outline Integrated Circuit (S) NS Package Number M16A 16 Lead Plastic Dual-In-Line Package (P) NS Package Number N16E 11 54AC/74AC161 # 54ACT/74ACT161 Synchronous Presettable Binary Counter Physical Dimensions inches (millimeters) (Continued) 16 Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 2900 Semiconductor Drive P.O. Box 58090 Santa Clara, CA 95052-8090 Tel: 1(800) 272-9959 TWX: (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str. 10 D-82256 F4urstenfeldbruck Germany Tel: (81-41) 35-0 Telex: 527649 Fax: (81-41) 35-1 National Semiconductor Japan Ltd. Sumitomo Chemical Engineering Center Bldg. 7F 1-7-1, Nakase, Mihama-Ku Chiba-City, Ciba Prefecture 261 Tel: (043) 299-2300 Fax: (043) 299-2500 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductores Do Brazil Ltda. Rue Deputado Lacorda Franco 120-3A Sao Paulo-SP Brazil 05418-000 Tel: (55-11) 212-5066 Telex: 391-1131931 NSBR BR Fax: (55-11) 212-1181 National Semiconductor (Australia) Pty, Ltd. Building 16 Business Park Drive Monash Business Park Nottinghill, Melbourne Victoria 3168 Australia Tel: (3) 558-9999 Fax: (3) 558-9998 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.