54ACT161SMQB - National Semiconductor

TL/F/9931

54AC/74AC161 #54ACT/74ACT161 Synchronous Presettable Binary Counter

April 1993

54AC/74AC161 #54ACT/74ACT161

Synchronous Presettable Binary Counter

General Description

The ’AC/’ACT161 are high-speed synchronous modulo-16

binary counters. They are synchronously presettable for ap-

plication in programmable dividers and have two types of

Count Enable inputs plus a Terminal Count output for versa-

tility in forming synchronous multistage counters. The ’AC/

’ACT161 has an asynchronous Master Reset input that

overrides all other inputs and forces the outputs LOW.

Features

YICC reduced by 50%

YSynchronous counting and loading

YHigh-speed synchronous expansion

YTypical count rate of 125 MHz

YOutputs source/sink 24 mA

Y’ACT161 has TTL-compatible inputs

YStandard Military Drawing (SMD)

Ð ’AC161: 5962-89561

Ð ’ACT161: 5962-89848

Logic Symbols

TL/F/9931–1

IEEE/IEC

TL/F/9931–2

Connection Diagrams

Pin Assignment

for DIP, Flatpak and SOIC

TL/F/9931–3

Pin Assignment

for LCC

TL/F/9931–4

Pin Names Description

CEP Count Enable Parallel Input

CET Count Enable Trickle Input

CP Clock Pulse Input

MR Asynchronous Master Reset Input

P0–P3Parallel Data Inputs

PE Parallel Enable Inputs

Q0–Q3Flip-Flop Outputs

TC Terminal Count Output

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

FACTTM is a trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

Functional Description

The ’AC/’ACT161 count in modulo-16 binary sequence.

From state 15 (HHHH) they increment to state 0 (LLLL). The

clock inputs of all flip-flops are driven in parallel through a

clock buffer. Thus all changes of the Q outputs (except due

to Master Reset of the ’161) occur as a result of, and syn-

chronous with, the LOW-to-HIGH transition of the CP input

signal. The circuits have four fundamental modes of opera-

tion, in order of precedence: asynchronous reset, parallel

load, count-up and hold. Five control inputsÐMaster Reset,

Parallel Enable (PE), Count Enable Parallel (CEP) and

Count Enable Trickle (CET)Ðdetermine the mode of opera-

tion, as shown in the Mode Select Table. A LOW signal on

MR overrides all other inputs and asynchronously forces all

outputs LOW. A LOW signal on PE overrides counting and

allows information on the Parallel Data (Pn) inputs to be

loaded into the flip-flops on the next rising edge of CP. With

PE and MR HIGH, CEP and CET permit counting when both

are HIGH. Conversely, a LOW signal on either CEP or CET

inhibits counting.

The ’AC/’ACT161 use D-type edge-triggered flip-flops and

changing the PE, CEP and CET inputs when the CP is in

either state does not cause errors, provided that the recom-

mended setup and hold times, with respect to the rising

edge of CP, are observed.

The Terminal Count (TC) output is HIGH when CET is HIGH

and counter is in state 15. To implement synchronous multi-

stage counters, the TC outputs can be used with the CEP

and CET inputs in two different ways.

Figure 1

shows the connections for simple ripple carry, in

which the clock period must be longer than the CP to TC

delay of the first stage, plus the cumulative CET to TC de-

lays of the intermediate stages, plus the CET to CP setup

time of the last stage. This total delay plus setup time sets

the upper limit on clock frequency. For faster clock rates,

the carry lookahead connections shown in

Figure 2

are rec-

ommended. In this scheme the ripple delay through the in-

termediate stages commences with the same clock that

causes the first stage to tick over from max to min in the Up

mode, or min to max in the Down mode, to start its final

cycle. Since this final cycle requires 16 clocks to complete,

there is plenty of time for the ripple to progress through the

intermediate stages. The critical timing that limits the clock

period is the CP to TC delay of the first stage plus the CEP

to CP setup time of the last stage. The TC output is subject

to decoding spikes due to internal race conditions and is

therefore not recommended for use as a clock or asynchro-

nous reset for flip-flops, registers or counters.

Logic Equations: Count Enable eCEP #CET #PE

TC eQ0#Q1#Q2#Q3#CET

Mode Select Table

PE CET CEP Action on the Rising

Clock Edge (L)

X X X Reset (Clear)

L X X Load (Pn

Qn)

H H H Count (Increment)

H L X No Change (Hold)

H X L No Change (Hold)

HeHIGH Voltage Level

LeLOW Voltage Level

XeImmaterial

State Diagram

TL/F/9931–5

TL/F/9931–8

FIGURE 1. Multistage Counter with Ripple Carry

TL/F/9931–9

FIGURE 2. Multistage Counter with Lookahead Carry

Block Diagram

TL/F/9931–6

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage (VCC)b0.5V to a7.0V

DC Input Diode Current (IIK)

VIeb

0.5V b20 mA

VIeVCC a0.5V a20 mA

DC Input Voltage (VI)b0.5V to VCC a0.5V

DC Output Diode Current (IOK)

VOeb

0.5V b20 mA

VOeVCC a0.5V a20 mA

DC Output Voltage (VO)b0.5V to VCC a0.5V

DC Output Source

or Sink Current (IO)g50 mA

DC VCC or Ground Current

per Output Pin (ICC or IGND)g50 mA

Storage Temperature (TSTG)b65§Ctoa

150§C

Junction Temperature (TJ)

CDIP 175§C

PDIP 140§C

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, without

exception, to ensure that the system design is reliable over its power supply,

temperature, and output/input loading variables. National does not recom-

mend operation of FACTTM circuits outside databook specifications.

Recommended Operating

Conditions

Supply Voltage (VCC)

’AC 2.0V to 6.0V

’ACT 4.5V to 5.5V

Input Voltage (VI) 0VtoV

Output Voltage (VO) 0VtoV

Operating Temperature (TA)

74AC/ACT b40§Ctoa

85§C

54AC/ACT b55§Ctoa

125§C

Minimum Input Edge Rate (DV/Dt)

’AC Devices

VIN from 30% to 70% of VCC

VCC @3.3V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate (DV/Dt)

’ACT Devices

VIN from 0.8V to 2.0V

VCC @4.5V, 5.5V 125 mV/ns

DC Characteristics for ’AC Family Devices

74AC 54AC 74AC

Symbol Parameter VCC TAea

25§CTAeTAeUnits Conditions

(V) b55§Ctoa

125§Cb40§Ctoa

85§C

Typ Guaranteed Limits

VIH Minimum High Level 3.0 1.5 2.1 2.1 2.1 VOUT e0.1V

Input Voltage 4.5 2.25 3.15 3.15 3.15 V or VCC b0.1V

5.5 2.75 3.85 3.85 3.85

VIL Maximum Low Level 3.0 1.5 0.9 0.9 0.9 VOUT e0.1V

Input Voltage 4.5 2.25 1.35 1.35 1.35 V or VCC b0.1V

5.5 2.75 1.65 1.65 1.65

VOH Minimum High Level 3.0 2.99 2.9 2.9 2.9 IOUT eb

50 mA

Output Voltage 4.5 4.49 4.4 4.4 4.4 V

5.5 5.49 5.4 5.4 5.4

*VIN eVIL or VIH

3.0 2.56 2.4 2.46 b12 mA

4.5 3.86 3.7 3.76 V IOH b24 mA

5.5 4.86 4.7 4.76 b24 mA

VOL Maximum Low Level 3.0 0.002 0.1 0.1 0.1 IOUT e50 mA

Output Voltage 4.5 0.001 0.1 0.1 0.1 V

5.5 0.001 0.1 0.1 0.1

*VIN eVIL or VIH

3.0 0.36 0.5 0.44 12 mA

4.5 0.36 0.5 0.44 V IOL 24 mA

5.5 0.36 0.5 0.44 24 mA

IIN Maximum Input 5.5 g0.1 g1.0 g1.0 mAVIeVCC, GND

Leakage Current

*All outputs loaded; thresholds on input associated with output under test.

DC Characteristics for ’AC Family Devices (Continued)

74AC 54AC 74AC

Symbol Parameter VCC TAea

25§CTAeTAeUnits Conditions

(V) b55§Ctoa

125§Cb40§Ctoa

85§C

Typ Guaranteed Limits

IOLD ²Minimum Dynamic 5.5 50 75 mA VOLD e1.65V Max

IOHD Output Current 5.5 b50 b75 mA VOHD e3.85V Min

ICC Maximum Quiescent 5.5 4.0 80.0 40.0 mAVIN eVCC

Supply Current or GND

²Maximum test duration 2.0 ms, one output loaded at a time.

Note: IIN and ICC @3.0V are guaranteed to be less than or equal to the respective limit @5.5V VCC.

ICC for 54AC @25§C is identical to 74AC @25§C.

DC Characteristics for ’ACT Family Devices

74ACT 54ACT 74ACT

Symbol Parameter VCC TAea

25§CTAeTAeUnits Conditions

(V) b55§Ctoa

125§Cb40§Ctoa

85§C

Typ Guaranteed Limits

VIH Minimum High Level 4.5 1.5 2.0 2.0 2.0 VVOUT e0.1V

Input Voltage 5.5 1.5 2.0 2.0 2.0 or VCC b0.1V

VIL Maximum Low Level 4.5 1.5 0.8 0.8 0.8 VVOUT e0.1V

Input Voltage 5.5 1.5 0.8 0.8 0.8 or VCC b0.1V

VOH Minimum High Level 4.5 4.49 4.4 4.4 4.4 VIOUT eb

50 mA

Output Voltage 5.5 5.49 5.4 5.4 5.4

*VIN eVIL or VIH

4.5 3.86 3.70 3.76 VI

b24 mA

5.5 4.86 4.70 4.76 b24 mA

VOL Maximum Low Level 4.5 0.001 0.1 0.1 0.1 VIOUT e50 mA

Output Voltage 5.5 0.001 0.1 0.1 0.1

*VIN eVIL or VIH

4.5 0.36 0.50 0.44 VI

24 mA

5.5 0.36 0.50 0.44 24 mA

IIN Maximum Input 5.5 g0.1 g1.0 g1.0 mAV

CC, GND

Leakage Current

ICCT Maximum 5.5 0.6 1.6 1.5 mA VIeVCC b2.1V

ICC/Input

IOLD ²Minimum Dynamic 5.5 50 75 mA VOLD e1.65V Max

IOHD Output Current 5.5 b50 b75 mA VOHD e3.85V Min

ICC Maximum Quiescent 5.5 4.0 80.0 40.0 mAVIN eVCC

Supply Current or GND

*All outputs loaded; thresholds on input associated with output under test.

²Maximum test duration 2.0 ms, one output loaded at a time.

Note: ICC for 54ACT @25§C is identical to 74ACT @25§C.

AC Electrical Characteristics

74AC 54AC 74AC

VCC*TAea

25§CTAeb

55§CT

40§C

Symbol Parameter (V) CLe50 pF to a125§Cto

85§C Units

CLe50 pF CLe50 pF

Min Typ Max Min Max Min Max

fmax Maximum Count 3.3 70 111 55 60 MHz

Frequency 5.0 110 167 80 95

tPLH Propagation Delay CP to Qn3.3 2.0 7.0 12 1.0 14.0 1.5 13.5 ns

(PE Input HIGH or LOW) 5.0 1.5 5.0 9.0 1.0 10.0 1.0 9.5

tPHL Propagation Delay CP to Qn3.3 1.5 7.0 12 1.0 14.0 1.5 13 ns

(PE Input HIGH or LOW) 5.0 1.5 5.0 9.5 1.0 10.0 1.5 10

tPLH Propagation Delay 3.3 3.0 9 15 3.0 18.5 2.5 16.5 ns

CP to TC 5.0 2.0 6 10.5 3.0 13.0 1.5 11.5

tPHL Propagation Delay 3.3 3.5 8.5 14 1.0 17.5 2.5 15.5 ns

CP to TC 5.0 2.0 6.5 11 1.0 13.0 2.0 11.5

tPLH Propagation Delay 3.3 2.0 5.5 9.5 1.0 13.0 1.5 11 ns

CET to TC 5.0 1.5 3.5 6.5 1.0 8.5 1.0 7.5

tPHL Propagation Delay 3.3 2.5 6.5 11 1.0 13.5 2.0 12.5 ns

CET to TC 5.0 2.0 5 8.5 1.0 10.5 1.5 9.5

tPHL Propagation Delay 3.3 2.0 6.5 12 1.0 14.5 1.5 13.5 ns

MR to Qn5.0 1.5 5.5 9.5 1.0 10.5 1.5 10

tPHL Propagation Delay 3.3 3.5 10 15 1.0 18.5 3.0 17.5 ns

MR to TC 5.0 2.5 8.5 13 1.0 14.0 2.5 13.5

*Voltage Range 3.3 is 3.3V g0.3V

Voltage Range 5.0 is 5.0V g0.5V

AC Operating Requirements

74AC 54AC 74AC

VCC*TAea

25§CTAeb

55§CT

40§C

Symbol Parameter (V) CLe50 pF to a125§Cto

85§C Units

CLe50 pF CLe50 pF

Typ Guaranteed Minimum

tsSetup Time, HIGH or LOW 3.3 6.0 13.5 16.0 16 ns

Pnto CP 5.0 3.5 8.5 10.5 10.5

thHold Time, HIGH or LOW 3.3 b7.0 b1 0.5 b0.5 ns

Pnto CP 5.0 b4.0 0 1.5 0

tsSetup Time, HIGH or LOW 3.3 6.5 11.5 15.0 14 ns

PE to CP 5.0 4.0 7.5 10.5 8.5

thHold Time, HIGH or LOW 3.3 b6.0 0 b1.0 0 ns

PE to CP 5.0 b3.5 0.5 0.0 1

tsSetup Time, HIGH or LOW 3.3 3.0 6.0 7.5 7 ns

CEP or CET to CP 5.0 2.0 4.5 5.5 5

thHold Time, HIGH or LOW 3.3 b3.5 0 2.0 0 ns

CEP or CET to CP 5.0 b2 0 2.0 0.5

twClock Pulse Width 3.3 2.0 3.5 5.0 4 ns

(Load) HIGH or LOW 5.0 2.0 2.5 5.0 3

twClock Pulse Width 3.3 2.0 4.0 5.0 4.5 ns

(Count) HIGH or LOW 5.0 2.0 3.0 5.0 3.5

twMR Pulse Width, 3.3 3.0 5.5 5.0 7.5 ns

LOW 5.0 2.5 4.5 5.0 6.0

trec Recovery Time b2b0.5 1.5 0 ns

MR to CP b1 0 2.0 0.5

*Voltage Range 3.3 is 3.3V g0.3V

Voltage Range 5.0 is 5.0V g0.5V

AC Electrical Characteristics

74ACT 54ACT 74ACT

VCC*TAea

25§CTAeb

55§CT

40§C

Symbol Parameter (V) CLe50 pF to a125§Cto

85§C Units

CLe50 pF CLe50 pF

Min Typ Max Min Max Min Max

fmax Maximum Count 5.0 115 125 85 100 MHz

Frequency

tPLH Propagation Delay CP to Qn5.0 1.5 5.5 9.5 1.0 10.5 1.5 10.5 ns

(PE Input HIGH or LOW)

tPHL Propagation Delay CP to Qn5.0 1.5 6.0 10.5 1.0 10.5 1.5 11.5 ns

(PE Input HIGH or LOW)

tPLH Propagation Delay 5.0 2.0 7.0 11.0 1.0 14.0 1.5 12.5 ns

CP to TC

tPHL Propagation Delay 5.0 1.5 8.0 12.5 1.0 12.5 1.5 13.5 ns

CP to TC

tPLH Propagation Delay 5.0 1.5 5.5 8.5 1.0 9.5 1.5 10.0 ns

CET to TC

tPHL Propagation Delay 5.0 1.5 6.5 9.5 1.0 9.5 1.5 10.5 ns

CET to TC

tPHL Propagation Delay 5.0 1.5 6.0 10.0 1.0 10.0 1.5 11.0 ns

MR to Qn

tPHL Propagation Delay 5.0 2.5 8.0 13.5 1.0 11.5 2.0 14.5 ns

MR to TC

*Voltage Range 5.0 is 5.0V g0.5V

AC Operating Requirements

74ACT 54ACT 74ACT

VCC*TAea

25§CTAeb

55§CT

40§C

Symbol Parameter (V) CLe50 pF to a125§Cto

85§C Units

CLe50 pF CLe50 pF

Typ Guaranteed Minimum

tsSetup Time, HIGH or LOW 5.0 4.0 9.5 13.0 11.5 ns

Pnto CP

thHold Time, HIGH or LOW 5.0 b5.0 0 0 0 ns

Pnto CP

tsSetup Time, HIGH or LOW 5.0 4.0 8.5 11.0 9.5 ns

PE to CP

thHold Time, HIGH or LOW 5.0 b5.5 b0.5 0 b0.5 ns

PE to CP

tsSetup Time, HIGH or LOW 5.0 2.5 5.5 7.0 6.5 ns

CEP or CET to CP

thHold Time, HIGH or LOW 5.0 b3.0 0 0.5 0 ns

CEP or CET to CP

twClock Pulse Width, 5.0 2.0 3.0 5.0 3.5 ns

(Load) HIGH or LOW

twClock Pulse Width, 5.0 2.0 3.0 5.0 3.5 ns

(Count) HIGH or LOW

twMR Pulse Width, LOW 5.0 3.0 3.0 6.5 7.5 ns

trec Recovery Time 5.0 0 0 0.5 0.5 ns

MR to CP

*Voltage Range 5.0 is 5.0V g0.5V

Capacitance

Symbol Parameter Typ Units Conditions

CIN Input Capacitance 4.5 pF VCC eOPEN

CPD Power Dissipation Capacitance 45.0 pF VCC e5.0V

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are

defined as follows:

74AC 161 P C QR

Temperature Range Family Special Variations

74AC eCommercial X eDevices shipped in 13×reels

54AC eMilitary QR eCommercial grade device with

74ACT eCommercial TTL-Compatible burn-in

54ACT eMilitary TTL-Compatible QB eMilitary grade device with

environmental and burn-in

Device Type processing shipped in tubes

Package Code Temperature Range

PePlastic DIP CeCommercial (b40§Ctoa

85§C)

DeCeramic DIP MeMilitary (b55§Ctoa

125§C)

FeFlatpak

LeLeadless Ceramic Chip Carrier (LCC)

SeSmall Outline (SOIC)

Physical Dimensions inches (millimeters)

20 Terminal Ceramic Leadless Chip Carrier (L)

NS Package Number E20A

16 Lead Ceramic Dual-In-Line Package (D)

NS Package Number J16A

Physical Dimensions inches (millimeters) (Continued)

16 Lead Small Outline Integrated Circuit (S)

NS Package Number M16A

16 Lead Plastic Dual-In-Line Package (P)

NS Package Number N16E

54AC/74AC161 #54ACT/74ACT161 Synchronous Presettable Binary Counter

Physical Dimensions inches (millimeters) (Continued)

16 Lead Ceramic Flatpak (F)

NS Package Number W16A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life

systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

National Semiconductor National Semiconductor National Semiconductor National Semiconductor National Semiconductores National Semiconductor

Corporation GmbH Japan Ltd. Hong Kong Ltd. Do Brazil Ltda. (Australia) Pty, Ltd.

2900 Semiconductor Drive Livry-Gargan-Str. 10 Sumitomo Chemical 13th Floor, Straight Block, Rue Deputado Lacorda Franco Building 16

P.O. Box 58090 D-82256 F4urstenfeldbruck Engineering Center Ocean Centre, 5 Canton Rd. 120-3A Business Park Drive

Santa Clara, CA 95052-8090 Germany Bldg. 7F Tsimshatsui, Kowloon Sao Paulo-SP Monash Business Park

Tel: 1(800) 272-9959 Tel: (81-41) 35-0 1-7-1, Nakase, Mihama-Ku Hong Kong Brazil 05418-000 Nottinghill, Melbourne

TWX: (910) 339-9240 Telex: 527649 Chiba-City, Tel: (852) 2737-1600 Tel: (55-11) 212-5066 Victoria 3168 Australia

Fax: (81-41) 35-1 Ciba Prefecture 261 Fax: (852) 2736-9960 Telex: 391-1131931 NSBR BR Tel: (3) 558-9999

Tel: (043) 299-2300 Fax: (55-11) 212-1181 Fax: (3) 558-9998

Fax: (043) 299-2500

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.