MTC-20135PQ-I - AMI Semiconductor, Inc.

Features

• ANSI TI.413 issue 2 standard

DMT modem with embedded ,

bypassable, ATM framer

•Byte interface or Standard

Utopia level 1 and level 2 ATM

interfaces

•Main functions:

Receive Direction:

•Rotor and Adaptive Frequency

domain Equalizing

•Demapping of DMT carriers

into a digital bitstream, includ-

ing 4D trellis coding

•Error and noise monitoring on

individual carriers and pilot

tones

•Reed-Solomon decoding and

deinterleaving

•ADSL Deframing

• ATM cell-specific Deframing

(can be bypassed)

• 144 Pin PQFP Package

• Power consumption 1 Watt at

3.3V

Transmit Direction:

•ATM cell-specific Framing

•ADSL Framing

•Reed-Solomon encoding

•Mapping of digital bitstream

onto DMT carriers

•Rotor and frequency domain

gain correction

General Description

The MTC-20135 is the DMT modem

and ATM Framer chip of the MTK-

20131 Rate adaptive ADSL DynaMiTe

chipset.

When used in conjunction with the

MTC-20134 analog front-end and an

external controller running Alcatel

firmware, the product supports ANSI

TI.413 release 2 ADSL specification.

The MTC-20135 may be used in both

central office (ATU-C) and remote (ATU-

R) applications. It provides both a cell

based UTOPIA Level 1 and 2 ATM

data interface to the host and a non

ATM synchronous bit stream.

The MTC-20135 performs the DMT

modulation, demodulation, Reed -

Solomon encoding, bit interleaving and

4D trellis coding. The ATM section pro-

vides framing functions for the generic

and ATM Transmission Convergence

(TC) layers. The generic TC consists of

data scrambling and Reed- Solomon

error corrections, with and without inter-

leaving.

The MTC-20135 is controlled and con-

figured by an external Transceiver

Controller. All programmable coeffi-

cients and parameters are loaded by

the Controller. The latter also controls

the initialization procedure and per-

forms the monitoring and adaptive func-

tions during operation.

Ordering Information

Part number Package Temp

MTC-20135PQ-I 144 pin PQFP -40 + 85°C

MTC-20135PQ-C 144 pin PQFP 0 + 70°C

Can also be ordered using kit number MTK-20131

MTC-20135

ADSL

DMT Transceiver

with ATM Framer

Preliminary Information

Rev. 3 - October 1998

Data Sheet

Fig. 1: General Block Diagram

ATM MTC-20135

DMT Modem

and ATM Framer

MTC-20134

Analog

Front-end

UTOPIA 2

MTC-20136

POTS

Splitter

CTRL-E RAM

Line

A/B

non-ATM bitstream

MTC-20135

FFT /

IFFT

Rotor

DSP

Front-end

Trellis

coding

Mapper/

Demapper

Generic

Reed /

Solomon

ATM

Specific

Interface Module

Controller interface

Test

Module Data Symbol Timing Unit

Reset

Controller bus General purpose I/Os

VCXO

Test signals Clock

AFE

Interface Utopia

Reset

SLAP

Fig. 2: MTC-20135 Block Diagram

Interface Module

* Synchronous Link Access Protocol

Main Blocks Description

The following essentially describes the

sequence of actions for the receive

direction, corresponding functions for

the transmit direction are readily

derived.

DSP Front-End

To DMT modem

Bypass

Analog

Interface IN

Select AFE

I/F DEC TEQ

MTC-20135

The DSP Front-End contains 4 parts in

the receive direction: the Input Selector,

the Analog Front-End Interface, the

Decimator and the Time Equalizer.

The input selector is used internally to

enable test loopbacks inside the chip.

The Analog Front-End Interface transfers

16-bits word, multiplexed on 4

input/output signals. As a result, 4 clock

cycles are needed to transfer 1 word.

The Decimator receives the 16-bits sam-

ples at 8.8 MHz (as sent by the Analog

Front-End chip) and reduces this rate to

2.2 MHz.

The Time Equalizer (TEQ) module is an

FIR filter with programmable coeffi-

cients. Its main purpose is to reduce the

effect of Inter-Symbol Interferences (ISI)

by shortening the channel impulse

response.

Both the Decimator and TEQ can be

bypassed.

In the transmit direction, the DSP Front-

End includes: sidelobe filtering, clip-

ping, delay equalization and interpola-

tion.

The sidelobe filtering and delay equal-

ization are implemented by IIR filters,

reducing the effect of echo in FDM sys-

tems.

Clipping is a statistical process limiting

the amplitude of the output signal, opti-

mizing the dynamic range of the AFE.

The interpolator receives data at 2.2

MHz and generates samples at a rate of

8.8 MHz.

Fig. 3: DSP Front-End

MTC-20135

DMT Modem

FFT FEQ ROTORRotor Demapper

FEQ

Coefficients

FEQ

Update

Trellis

Coding

Monitor

Indications

From

DSP FE To TC

DMT Codec

This computational module is a pro-

grammable DSP unit. Its instruction set

enables functions like FFT, IFFT, Scaling,

Rotor and Frequency Equalization

(FEQ).

This block implements the core of the

DMT algorithm as specified in ANSI

T1.413.

In the RX path, the 512-point FFT trans-

forms the time-domain DMT symbol into

a frequency domain representation

which can be further decoded by the

subsequent demapping stages. After the

first stage time -domain equalization

and FFT block an essentially ICI

(InterCarrier Interference)- free carrier

information stream has been obtained.

This stream is still affected by carrier-spe-

cific channel distortion resulting in an

attenuation of the signal amplitude and

a rotation of the signal phase. To com-

pensate for these effects, the FFT is fol-

lowed by a Frequency domain equaliz-

er (FEQ) and a Rotor (phase shifter).

In the TX path, the IFFT transforms the

DMT symbol generated in the frequency

domain by the mapper into a time

domain representation. The IFFT block is

preceded by a Fine Tune Gain and a

Rotor stage, allowing for a compensa-

tion of the possible frequency mismatch

between the master clock frequency and

the transmitter clock frequency (which

may be locked to another reference).

The FFT module is a slave DSP engine

controlled by the transceiver controller. It

works off line and communicates with

the other blocks via buffers controlled by

the DSTU block. The DSP executes a

program stored in a RAM area, a very

flexible implementation open for future

enhancements.

Fig. 4: DMT Modem

MTC-20135

DPLL

The Digital PLL module receives a metric

for the phase error of the pilot tone. In

general, the clock frequencies at the

transmitter and receiver do not match

exactly. The phase error is filtered and

integrated by a low pass filter, yielding

an estimation of the frequency offset.

Various processes can use this estimate

to deal with the frequency mismatch. In

particular, small accumulated phase

error can be compensated in the fre-

quency domain by a rotation of the

received code constellation (Rotor).

Larger errors are compensated in the

time domain by inserting or deleting

clock cycles in the sample input

sequence.

Mapper/Demapper, Monitor, Trellis Coding, FEQ Update

The Demapper converts the constellation

points computed by the FFT to a block of

bits. This essentially consists in identify-

ing a point in a 2D QAM constellation

plane.

The Demapper supports trellis coded

demodulation and provides a Viterbi

maximum likelihood estimator. When

the trellis is active, the Demapper

receives an indication for the most likely

constellation subset to be used.

In the transmit direction, the Mapper

performs the inverse operation, map-

ping a block of bits into one constella-

tion point (in a complex x+jy representa-

tion) which is passed to the IFFT block.

The Trellis Encoder generates redundant

bits to improve the robustness of the

transmission, using a 4-Dimensional

Trellis Coded Modulation scheme.

The Monitor computes error parameters

for carriers specified in the Demapper

process. Those parameters can be used

for updates of adaptive filters coeffi-

cients, clock phase adjustments, error

detection,etc. A series of values is con-

stantly monitored, such as signal power,

pilot phase deviations, symbol erasures

generation, loss of frame,etc.

MTC-20135

Generic TC Layer Functions

These functions relate to byte oriented

data streams. They are completely

described in ANSI T1.413. Additions

described in the Issue 2 of this specifica-

tion are also supported.

The data received from the demapper is

split into two paths, one dedicated to an

interleaved data flow, the other one for

a non-interleaved data flow. These data

flows are also referred to as slow and

fast data flows.

The interleaving/deinterleaving is used

to increase the error correcting capabili-

ty of block codes for error bursts.

After deinterleaving (if applicable), the

data flow enters a Reed-Solomon error

correcting code decoder, able to correct

a number of bytes containing bit errors.

The decoder also uses the information

of previous receiving stages that may

have detected the errored bytes and

have labelled them with an “erasure”

indication.

Each time the RS decoder detects and

corrects errors in a RS codeword, an RS

correction event is generated. The

occurrence of such events can be sig-

nalled to the management layer.

After leaving the RS decoder, the cor-

rected byte stream is descrambled in the

PMD (Physical Medium Dependent)

descramblers. Two descramblers are

used, for interleaved and non-inter-

leaved data flows. These are defined in

ANSI T1.413.

After descrambling, the data flows enter

the Deframer that extracts and process-

es bytes to support Physical layer relat-

ed functions according to ANSI T1.413.

The ADSL frames indeed contain physi-

cal layer-related information in addition

to the data passed to the higher layers.

In particular, the deframer extracts the

EOC (Embedded Operations Channel),

the AOC (ADSL Overhead Control) and

the indicators bits and passes them to

the appropriate processing unit (e.g. the

transceiver controller). The deframer

also performs a CRC check (Cyclic

Redundancy Check ) on the received

frame and generates events in case of

error detection. Event counters can be

read by management processes.

The outputs of the deframer are an inter-

leaved and a fast data streams. These

data streams can either carry ATM cells

or another type of traffic. In the latter

case, the ATM specific TC layer func-

tional block, described hereafter, is

bypassed and the data stream is direct-

ly presented at the input of the Interface

module.

SPLITTER

De-

Interleaver

Coding

PMD

Descrambler

PMD

Descrambler

Deframer F

AOC

EOC

Fast

From

Demapper

Indication bits

To ATM TC

Fig. 5: Generic TC Layer Functions

MTC-20135

ATM Specific TC Layer Functions

The 2 bytes streams (fast and slow) are

received from the byte-based process-

ing unit. When ATM cells are transport-

ed, this block provides basic cell func-

tions such as cell synchronization, cell

payload descrambling, idle/unas-

signed cell filter, cell Header Error

Correction (HEC) and detection. The

cell processing happens according to

ITU-T I.163 standard. Provision is also

made for BER measurements at this

ATM cell level.

When non cell oriented byte streams

are transported, the cell processing unit

is not active.

Cell

Descrambler

Synchronizer

Cell

Descrambler

Synchronizer

HEC

Cell

filter

Cell

filter

BER

Fast

Slow

To Interface

Module

From Generic

Fig. 6: ATM Specific TC Layer Functions

MTC-20135

Interface Module

The DSTU interfaces with various mod-

ules, like DSP Front-End, FFT/IFFT,

Mapper/Demapper, RS , Monitor and

Transceiver Controller. It consists of a

real time and a scheduler modules. The

real time unit generate a timebase for

the DMT symbols (sample counter),

superframes (symbol counter) and hyper-

frames (sync counter). The timebases

can be modified by various control fea-

tures. They are continuously fine-tuned

by the DPLL module.

The DSTU schedulers execute a program,

controlled by program opcodes and a

set of variables, the most important of

which are real time counters.The trans-

mit and receive sequencers are com-

pletely independent and run different

programs. An independent set of vari-

ables is assigned to each of them. The

sequencer programs can be updated in

real time.

level

UTOPIA 1

level

UTOPIA 2

level

UTOPIA 1

level

UTOPIA 2

SLAP

Fast byte stream

Fast ATM

Slow ATM

Slow byte stream

From ATM TC

The interface module collects cells (from

the cell-based function module) or a

byte stream (from the deframer). Cells

are stored in FIFO’s ( 424 bytes or 8

cells wide, transmit buffers have the

same size), from which they are extract-

ed by 2 interface submodules, one pro-

viding an Utopia level 1 interface and

the other an Utopia level 2 interface.

Byte streams are dumped on the SLAP

(Synchronous Link Access Protocol) inter-

face.

Only one type of interface can be

enabled in a specific configuration.

DMT Symbol Timing Unit (DSTU)

Fig. 7: Interface Module

Receive Interface

The 16 bit receive word is multiplexed

on 4 AFRXD input signals. As a result 4

cycles are needed to transfer 1 word.

Refer to Table 2 for the bit/pin alloca-

tion for the 4 cycles. The first of 4 cycles

is identified by the CLWD signal. Refer

to Figure 9. The CLWD must repeat

after 4 MCLK cycles.

Interfaces

Analog Front-End Control

Interface

The Analog Front-End Interface is

designed to be connected to the MTC-

20134 Analog Front-End component.

Transmit Interface

The 16 bit words are multiplexed on 4

AFTXD output signals. As a result 4

cycles are needed to transfer 1 word.

Refer to Table 1 for the bit/pin alloca-

tion for the 4 cycles. The first of 4 cycles

is identified by the CLWD signal. Refer

to Figure 8. The MTC-20135 fetches the

16 bit word to be multiplexed on

AFTXD from the Tx Digital Front-End

module.

MTC-20135

Fig. 8: Timing Diagram

Table 1: Transmitted Bits Assigned to Signal/Time Slot

Cycle 0 Cycle 1 Cycle 2 Cycle 3

AFTXD[0] b0 b4 b8 b12

AFTXD [1] b1 b5 b9 b13

AFTXD[2] b2 b6 b10 b14

AFTXD[3] b3 b7 b11 b15

GP_OUT t0 t1 t2 t3

Fig. 9: Receive Word Timing Diagram

Table 2: Transmitted Bits Assigned to Signal/Time Slot

Cycle 0 Cycle 1 Cycle 2 Cycle 3

AFRXD[0] b0 b4 b8 b12

AFRXD [1] b1 b5 b9 b13

AFRXD[2] b2 b6 b10 b14

AFRXD[3] b3 b7 b11 b15

GP_IN t0 t1 t2 t3

Master Clock ( MCLK )

Transmit Interface

Receive Interface

MTC-20135

Symbol Parameter Test Cond. Min Typ Max Unit

F Clock Frequency 35.328 MHz

Tper Clock Period 28.3 ns

Th Clock duty cycle 40 60 %

Table 3: MCLK, AC Electrical Characteristics

Symbol Parameter Test Cond. Min Typ Max Unit

Tv Data valid time 0 10 ns

Tc Data valid time 0 10 ns

Table 4: AFTXD AFTXED CLWD, AC Electrical Characteristics

Fig. 10: Transmit Interface

Symbol Parameter Test Cond. Min Typ Max Unit

Ts Data setup time 5 ns

Th Data hold time 5 ns

Table 5: AFRXD, AC Electrical Characteristics

Fig. 11: Receive Interface

Analog Front End Interface Timing

Controller Interface

Interface Types

Two interface types are supported for

an external ADSL Transceiver Controller

(ATC); a generic asynchronous interface

and a specific i960 interface. The inter-

face selection is made by the

OBC_TYPE pin. ( 0b selects i960 type

interface )

i960 Specific Interface

Basic Operation

The i960 supports a synchronous bus

interface protocol. Address and data

bus are multiplexed. The ATC is bus

master and the MTC-20135 is a slave.

A bus cycle consists of an access cycle (

Ta ) wait cycles ( Tw ), data cycle (Td ),

Recovery cycles (Tr). Let us have a look

at the 3 basic states of a bus cycle :

a)The bus cycle is initiated by the ATC.

The ATC asserts the AD[15:2], BE1 and

ALE signals. The MTC-20135 latches

AD[15:2] on the falling edge of the ALE

signal. The MTC-20135 computes the

address by a concatenation of the sig-

nal on AD[15:2] and BE1 and a fixed

0b.

b)The CSB (input from an external

decoder) and the WR_RDB (input from

ATC) are asserted synchronous to PCLK.

At this stage the MTC-20135 decides

whether it is involved in the current bus

cycle. If it is not selected ( by the signal

the MTC-20135 returns to state 1.

c)The RDYB output is synchronous to

PCLK. The signal is generated by the

MTC-20135. It is used to extend the bus

cycle.

MTC-20135

Fig. 12: Read Cycle Note: The RDYB output is continuously

in tri-state, except for 2 cycles.

Table 6: Pins & Functional Description

ATC Interface Timing

All timing parameters are specified at a load of 100 pF, all the electrical levels are CMOS compatible.

Table 7: All Signals

Table 8: PCLK

MTC-20135

Fig. 13: Write Cycle Note : The RDYB output is continuously

in tri-state, except for 2 cycles.

Name Type Function

AD[15:0] IO Multiplexed address-data bus,during address phase,

AD[15:2] reflect address bits [15:2]

BE1 I reflects address bit [1]

ALE I address latch enable

WR_RDB I write not read indication

PCLK I Processor clock

CSB I chip select

RDYB OZ Bus cycle ready indication

INTB O Interrupt

Symbol Parameter Min Typ Max Unit

tr,tf Rise and Fall time (10% - 90%) 3 ns

Ci Input load 10 pF

Co Output load 100 pF

Symbol Parameter Min Typ Max Unit

tf PCLK clock frequency 8 35.328 MHz

Table 9: Address with Respect to ALE

Table 10: Data Input with Respect to the Clock

Table 11: Data Output with Respect to the Clock

Table 12: WR_RDB Input Specification with Respect to PCLK

Table 13: CSB Input Specification with Respect to PCLK

Table 14: RDYB Output with Respect to PCLK

MTC-20135

Symbol Parameter Min Typ Max Unit

tr,tf Rise and Fall time (10-90%) 4 ns

Talew ALE pulse width 12 ns

Tavs Address valid setup time 7 ns

Tavh Address valid hold time 8 ns

Fig. 14: Address and ALE Timing

Symbol Parameter Min Max Unit

Tdh Data write hold time 3 ns

Tds Data write setup time 10 ns

Symbol Parameter Min Max Unit

Tzd Data active delay from clock, Z to data 3 20 ns

Tdz Data inactive delay from clock, data to Z 3 20 ns

Symbol Parameter Min Max Unit

Twrs setup WR_RDB to clock 10 ns

Twrh hold WR_RDB to clock 3 ns

Symbol Parameter Min Max Unit

Twrs setup CSB to clock 10 ns

Twrh hold CSB to clock 3 ns

Symbol Parameter Min Max Unit

Tzrd RDYB active delay from clock, Z to 0 3 19 ns

Trdz RDYB inactive delay from clock, 0 to Z 3 19 ns

Table 15: Pins & Functional Description

Dynamic Characteristics

Table 16: All Signals

Table 17: Timing Related to ALE Signal

Generic Interface

The generic interface allows for the con-

nection of a series of processors with

limited requirements for external inter-

face logic.

This interface targets a family of proces-

sors using a multiplexed address/data

bus.

MTC-20135

Signal name Type Function PIN

AD[15:0] IO Multiplexed address-data bus, AD[15:0]

ALE I address latch enable ALE

RDB I read cycle indication WR_RDB

WR_B I write cycle indication BE1

CSB I chip select CSB

RDYB OZ Bus cycle ready indication RDYB

INTB O Interrupt INTB

Symbol Parameter Min Typ Max Unit

tr,tf Rise and Fall time (10% - 90%) 3 ns

Ci Input load 10 pF

Co Output load 100 pF

Symbol Parameter Min Typ Max Unit

Talew ALE pulse width 12 ns

Tavs Address valid setup time 10 ns

Tavh Address valid hold time 10 ns

Tale2cs ALE to CSB 0 ns

Tale2Z ALE to high Z state of bus 50 ns

Cycle Timing

Symbol Parameter Min Typ Max Unit

Tcs2rs CSB to RDYB asserted 60 ns

Tcsre access time 900 ns

Tcs2wr CSB to WRB 0 ns

Twr2d WRB to data 15 ns

Trdy2wr RDYB to WRB 0 ns

Twvd data set up time 10 ns

Tdvh data hold time 1/2 Tmclk Tmclk ns

Twr2cs WRB to CSB -10 ns

Tcs2wr CSB to WRB 0 ns

Trdy2rd RDYB to RD 0 ns

Twvd data set up time 10 ns

Trd2cs RDB to CSB -10 ns

Tmclk master clock timing.

Table 18: Timing Parameters of the ATC Interface

All AC characteristics are measured in a circuit with a 100 pF capacitive load. Rise and fall times apply to all signals.

MTC-20135

Fig. 15: ATC Write Timing Diagram

Fig. 16: ATC Read Timing Diagram

Digital Interface

Utopia Level 2 Interface

The ATM forum takes the ATM layer

chip as a reference. It defines the direc-

tion from ATM to physical layer as the

Transmit direction. The direction from

physical layer to ATM as the Receive

direction is referred to as the receive

direction. Figure 17 shows the intercon-

nection between ATM and PHY layer

devices, the optional signals are not

supported and not shown.

The UTOPIA interface transfers one byte

in a single clock cycle, as a result cells

are transferred in 53 clock cycles.

Both transmit and receive interfaces are

synchronized on clocks generated by

the ATM layer chip, and no specific

relationship between Receive and

Transmit clock is assumed, they must be

regarded as mutually asynchronous

clocks. Flow control signals are avail-

able to match the bandwidth constraints

of the physical layer and the ATM layer.

The UTOPIA level2 supports point to

multi point configurations by introducing

an addressing capability and by mak-

ing a distinction between polling and

selecting a device :

—the ATM chip polls a specific physical

layer chip by putting its address on the

address bus when the Enb line is assert-

ed. The addressed physical layer

answers the next cycle via a Clav line

reflecting its status at that time.

—the ATM chip selects a specific physi-

cal layer chip by putting its address on

the address bus when the Enb line is

deasserted and asserting the Enb line

on the next cycle. The addressed physi-

cal layer chip will be the target or

source of the next cell transfer.

Reference Spec:

Utopia Specification

Level 2, Version 1.0, June 95.

See www.atmforum.com

MTC-20135

Fig. 17: Signals at Utopia Level 2 Interface

MTC-20135

UTOPIA Level 2 Signals

The physical layer chip sends cell data

towards the ATM layer chip. The ATM

layer chip polls the status of the FIFO of

the physical layer chip. Refer to Table

19 for a list of interface signals :

The cell exchange proceeds like :

a)The physical layer chip signals the

availability of a cell by asserting RxClav

when polled by the ATM chip.

b)The ATM chips selects a physical

layer chip, then starts the transfer by

asserting notRxEnb.

c)If the physical layer chip has data to

send, it puts them on the RxData line the

cycle after it sampled notRxEnb active. It

also advances the offset in the cell. If the

data transferred is the first byte of a cell,

RxSOC is 1b at the time of the data

transfer, 0b otherwise.

d)The ATM chip accepts the data when

they are available. If RxSOC was 1b

during the transfer, it resets its internal

offset pointer to the value 1, otherwise it

advances the offset in the cell.

MTC-20135 Utopia Level 2 MPHY

Operation

Utopia level 2 MPHY operation can be

done by various interface schemes. The

MTC-20135 supports only the required

mode, this mode is referred to as ’oper-

ation with 1 TxClav and 1 RxClav’.

PHY Device Identification

The MTC-20135 holds 2 PHY layer

Utopia ports, one is dedicated to the

fast data channel, the other one to the

interleaved data channel. The associat-

ed PHY address is specified by the

PHY_ADDR_x fields the Utopia PHY

address register. Beware that an incor-

rect address configuration may lead to

bus conflicts.

MTC-20135

Name Meaning Usage Remark

RxClav Receive Cell available Signals to the ATM chip that the physical Remains active for the entire cell

layer chip has a cell ready for transfer. transfer

notRxEnb Receive Enable (active low) Signals to the physical layer chip that the RxData and RxSOC could be

ATM layer chip will sample and accept tristate when notRxEnb is inactive

data during next clock cycle. (high).

RxClk Receive Byte Clock Gives the timing signal for the transfer,

generated by ATM layer chip.

RxData Receive Data ATM cell data from physical layer chip to

ATM chip, byte wide

RxSOC Receive Start Of Cell Identifies the cell boundary on RxData

RxAddr Receive Address Use to select the port that will be active

or polled

Table 19: Signal Definitions for the Utopia Receive Path

Name Meaning Usage

TxClav Transmit Cell available Signals to the ATM chip that the physical layer chip is ready to accept a cell.

notTxEnb Transmit Enable (active low) Signals to the physical layer chip that TxData and TxSOC are valid.

TxClk Transmit Byte Clock Gives the timing signal for the transfer, generated by ATM layer chip.

TxData Transmit Data ATM cell data from ATM chip to physical later chip, byte wide

TxSOC Transmit Start Of Cell Identifies the cell boundary on TxData

TxAddr Transmit Address Use to select the port that will be active or polled

Table 20: Signal Definitions for the Utopia Transmit Path

Utopia level 1 Handshake

Protocol PHY->ATM

The MTC-20135 supports a cell level

handshake protocol only.

The ATM layer indicates it wants to

read data by asserting the notRxEnb sig-

nal. The PHY layer dumps 53 bytes ( 1

cell ) on the RxDATA bus, a cell start

indication is available on the RxSOC

signal. Refer to Figure 19.

MTC-20135

Fig.18: Signals at UTOPIA Level 1 interface

Utopia Level 1

Data Flow Selection

In this mode the MTC-20135 can only

support one data flow ( either fast or

interleaved ). The selection between fast

or interleaved is under control of the

Transceiver Controller.

Utopia Level 1 Configuration

MTC-20135

Reference Spec:

Utopia Specification

Level 1, Version 2.0, March 94.

See www.atmforum.com

Fig.19a: Utopia Level 1 Functional Timing Diagram (PHY -> ATM)

Fig.19b: Utopia Level 1 Functional Timing Diagram (ATM -> PHY)

Utopia level 1 Reference Clock

The Utopia reference clock ( notRxRef )

has a duty cycle of 50%. It is asynchro-

nous to all other Utopia signals.

Utopia level 1 Signal

Multiplexing

UTOPIA Interface Timings

Clock Signals

ATM to PHY Signals

MTC-20135

Table 21: Utopia level 1 Pinout

Name signal Type Pin

RxData O U_RxData

RxSOC O U_RxSOC

notRxEnb I U_RxENBB

RxClav O U_RxCLAV

RxClk I U_RxCLK

Symbol Parameter Test Cond. Min Typ Max Unit

F Clock Frequency 1.5 25 MHz

Tc Clock duty cycle 40 60 %

Tj Clock peak to peak jitter 5 %

Trf Clock rise/fall time 4 ns

L Load 100 pF

Table 22: U_TxCLK, U_RxCLK, AC Electrical Characteristics

Fig.20: Utopia Timing Diagram

Symbol Parameter Test Cond. Min Typ Max Unit

T5 Input set up time to 10 ns

U_TxCLK

T6 Hold time time to 1 ns

U_TxCLK

L Load 100 pF

Table 23: U_TxData, U_TxSOC, U_TxADDR, AC Electrical

MTC-20135

Symbol Parameter Min Typ Max Unit

T5 Input set up time to U_RxCLK 10 ns

T6 Hold time time to U_RxCLK 1 ns

L Load 100 pF

Table 24: U_RxADDR AC Electrical Characteristics

PHY to ATM Signals U_TxCLAV

Table 25: U_RxData, U_RxSOC, U_RxCLAV AC Electrical Characteristics

Table 26: U_RxADDR AC Electrical Characteristics

Symbol Parameter Min Typ Max Unit

T7 Input set up time to U_TxCLK 10 ns

T8 Hold time time to U_TxCLK 1 ns

T9 Signal going low impedance to U_RxCLK 10 ns

T10 Signal going high impedance to U_RxCLK 0 ns

T11 Signal going low impedance to U_RxCLK 1 ns

T12 Signal going high impedance to U_RxCLK 1 ns

L Load 100 pF

Symbol Parameter Min Typ Max Unit

T7 Input set up time to U_TxCLK 10 ns

T8 Hold time time to U_TxCLK 1 ns

T9 Signal going low impedance to U_RxCLK 10 ns

T10 Signal going high impedance to U_RxCLK 0 ns

T11 Signal going low impedance to U_RxCLK 1 ns

T12 Signal going high impedance to U_RxCLK 1 ns

L Load 100 pF

SLAP (Synchronous Link

Access Protocol) Interface

The SLAP ATM interface is a point to

point bitstream interface. The MTC-

20135 is the bus master of the inter-

face. The interface is synchronous, a

common clock (INTERFACE_CLOCK) is

used. The SLAP interface dumps the

data of the fast and interleaved chan-

nels on 2 separate sub interfaces. The

data flow from the SLAP interface must

be enabled by the Transceiver

Controller. A disabled cell interface

does not dump data on its interface.

Receive SLAP Interface

The interface signals uses 2 signal types

: ( refer to Figure 21)

—SLR_DATA[1:0]: data pins, a byte is

transferred in 4 cycles of 2 bits. The

msb are transmitted first, odd bits are

asserted on SLR_DATA[1].

—SLR_VAL: indicates the data transfer

and the byte boundary

—SLR_FRAME: indicates the start of a

superframe

Notice 2 SLAP interfaces are supported,

one for the fast data flow, the other one

for the interleaved data flow.

The logical timing diagram is shown in

Figure 22.

MTC-20135

Fig. 21: Receive Path, SLAP Interface

The implementation must guarantee that

all active SLR_Valid signals must be sep-

arated by at least 8 clock cycles. Refer

to Figure 22. The SLR_FRAME signals

are asserted when the first pair of bits of

a frame are transferred. For the fast

channel a frame is defined as a

superframe timebase. For the inter-

leaved channel the frame is defined by

a timebase period of 4 superframes.

Both timebases are synchronized to the

data flow and guarantee that the frame

Fig. 22: SLAP Interface Timing

Transmit SLAP Interface

The Transmit interface uses the following

signals (refer to Figure 23)

—SLT_REQ: byte request

—SLT_FRAME: start of frame indication

—SLT_DATA[1:0]: data pins, a byte is

transferred 2 bits at the time in 4 succes-

sive clock cycles. MSB first, odd bits on

SLT_DATA[1]

The logical timing diagram is shown in

Figure 24. The delay between Request

and the associated data byte is defined

as 8 cycles.

The SLT_FRAME signals are asserted

when the first pair of bits of a frame are

transferred. For the fast channel a frame

is defined as a superframe timebase.

For the interleaved channel the frame is

defined by a timebase period of 4

superframes. Both timebases are syn-

chronized to the data flow and

guarantee that the frame indication is

asserted when the first bits of the first

DMT symbol are transferred.

MTC-20135

Fig. 23: Interface Towards PHY Layer

Fig. 24: Functional Interface Timing Diagram

MTC-20135

Fig. 25: SLAP Interface Timing Information

SLAP Interface Timings

Symbol Parameter Test Cond. Min Typ Max Unit

Tper Clock Period refer to MCLK ns

Th Clock High 11 17 ns

Tl Clock Low 11 17 ns

Ts Setup 8 ns

Thd Hold -2 ns

Td Data delay 20 pF load 0 3 ns

Table 27: SLAP Interface, AC Electrical Characteristics

MTC-20135

TAP Bus Signals

The interface from the board to the on-

chip Test Access Port is the TAP bus,

consisting of five signals:

—the standard bus : TDI, TDO, TCK,

TMS.

—TRSTB : Test Reset, reset the TAP con-

troller. TRSTB is an active low signal.

TRSTB is explicitly required because

TCK is not active in functional mode. To

guarantee a correct operation of the

component on the board, all flipflops

that control the signals in the interface

between the TAP controller and the

device logic must support an asynchro-

nous reset.

Instructions

The IEEE standard requires that INTEST,

EXTEST, BYPASS and SAMPLE be imple-

mented as a minimum. It is also manda-

tory to implement an IDCODE. The

Alcatel Identification Code used in the

IDCODE instruction is a 32 bit pattern.

Boundary Scan Data Register

The scan chain uses 4 types of cells :

a)input cells: able to sample and control

the state of an external signal during BS

tests.

b)output cells: able to control the state of

an external signal during BS tests.

c)capture cell: able to sample the state

of an external signal during BS tests. Its

usage is restricted to paths where addi-

tional delay caused by an input cell is

inacceptable.

d)enable cell: provides a signal for

direction control of bidirectional pins

during BS tests.

In boundary scan mode, the input sig-

nals are sampled at the rising edge of

TCK, while the output signal changes at

the falling edge. The component ensures

correct operation of scan instructions

related to any internal register up to 10

MHz (5 Mbit/s).

JTAG TAP and Boundary Scan

Version Part Number Manufacturer Identity 1

31 28 27 Bit number 12 11 1 0

MS Bit LS Bit

Fig. 26: JTAG TAP Idcode

Table 28: Boundary Scan Chain Sequence

MTC-20135

Sequence Number Mnemonic Pin BS Type

2 AD_0 B

3 AD_1 B

4 AD_2 B

6 AD_3 B

7 AD_4 B

9 AD_5 B

10 AD_6 B

12 AD_7 B

13 AD_8 B

14 AD_9 B

16 AD_10 B

17 AD_11 B

19 AD_12 B

21 PCLK I

23 AD_13 B

24 AD_14 B

25 AD_15 B

27 BE1 I

28 ALE C

30 CSB I

31 WR_RDB I

32 RDYB O

33 OBC_TYPE I

34 INTB O

35 RESETB I

38 U_RxData_0 B

39 U_RxData_1 B

41 U_RxData_2 B

42 U_RxData_3 B

44 U_RxData_4 B

45 U_RxData_5 B

46 VSS

47 U_RxData_6 B

48 U_RxData_7 B

50 U_RxADDR_0 I

51 U_RxADDR_1 I

52 U_RxADDR_2 I

53 U_RxADDR_3 I

55 U_RxADDR_4 I

56 GP_IN_0 I

58 GP_IN_1 I

60 U_RxRefB O

61 U_TxRefB I

63 U_RxCLK C

64 U_RxSOC I

65 U_RxCLAV O

66 U_RxENBB I

68 U_TxCLK C

69 U_TxSOC I

70 U_TxCLAV O

71 U_TxENBB I

MTC-20135

74 U_TxData_7 I

75 U_TxData_6 I

77 U_TxData_5 I

78 U_TxData_4 I

79 U_TxData_3 I

80 U_TxData_2 I

82 U_TxData_1 I

83 U_TxData_0 I

84 U_TxADDR_4 I

85 U_TxADDR_3 I

87 U_TxADDR_2 I

88 U_TxADDR_1 I

89 U_TxADDR_0 I

90 SLR_FRAME_F O

92 SLR_FRAME_S O

93 SLR_DATA_S_1 O

94 SLR_DATA_S_0 O

96 SLR_DATA_S O

97 SLR_DATA_F_1 O

98 SLR_DATA_F_0 O

99 SLR_VAL_F O

100 INTERFACE_CLOCK none

101 SLT_FRAME_F O

103 SLT_DATA_F_1 I

104 SLT_DATA_F_0 I

105 SLT_DATA_S_1 I

106 SLT_DATA_S_0 I

107 SLT_REQ_F O

110 SLT_REQ_S O

111 SLT_FRAME_S O

112 TDI none

113 TDO none

114 TMS none

116 TCK none

118 TRSTB none

119 TESTSE C

120 GP_OUT O

121 PDOWN O

123 AFRXD_0 I

124 AFRXD_1 I

125 AFRXD_2 I

126 AFRXD_3 I

128 CLWD I

129 MCLK C

130 CTRLDATA O

132 AFTXED_0 O

133 AFTXED_0 O

135 AFTXED_0 O

136 AFTXED_0 O

138 IDDq C

139 AFTXD_0 -

140 AFTXD_1 -

142 AFTXD_0 -

143 AFTXD_1 -

MTC-20135

Reset Initialization

The MTC-20135 supports two reset

modes:

—A ’hardware’ reset is activated by the

RESETB pin (active low). A hard reset

occurs when a low input value is detect-

ed at the RESETB input. The low level

must be applied for at least 1ms to guar-

antee a correct reset operation. All

clocks and power supplies must be sta-

ble for 200ns prior to the rising edge of

the RESETB signal.

—’Soft’ reset, activated by the controller

write access to a soft reset configuration

bit.

The reset process takes less than 10000

MCLK clock cycles.

Electrical Specifications

Absolute Maximum Ratings

Operation of the device beyond these

conditions is not guaranteed. Sustained

exposure to these limits will adversely

effect device reliability.

Parameter Max Units

DVDD, AVDD 4.8 V (see note)

Vin, Voltage on any device pin VSS-0.3 V

VDD+0.3 or 3.63 V, whichever is lower

Storage temperature -65 to +150 °C

Temperature under bias -55 to +125 °C

Lead Temperature 300 °C

(soldering 10 sec)

Table 1

Note: Exposure to voltages at or above

this level for more than 10 hours accum-

mulated over the device’s operating life

will adversely effect reliability.

Note 2. All logic pins except NRESET,

which is a Schmitt-trigger input with hys-

teresis.

Operating Conditions

Electrical characteristics are specified over the following operating conditions unless otherwise specified.

Table 33: Operating Conditions

Maximum Ratings

Symbol Parameter Note Min Typ Max Unit

VDD Supply voltage 3.0 3.3 3.6 V

TA Ambient temperature - I version -40 +85 °C

1m/s airflow - C version 0 70 °C

MTC-20135

Input/Output CMOS Generic

Characteristics

The values presented in the following

table apply for all CMOS inputs and/or

outputs unless specified otherwise.

* The reference current is dependent on

the exact buffer chosen and is a part of

the buffer name. The available values

are 2, 4 and 8 mA.

DC Electrical Characteristics

All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device

Symbol Parameter Test Conditions Min Typ Max Unit

VIL Low level input voltage 0.2*VDD V

VIH High level input voltage 0.8*VDD V

VHY Schmitt trigger hysteresis slow edge < 1 V/ms, 0.8 V

only for SCHMITx

VOL Low level output voltage IOUT = XmA* 0.4 V

VOH High level output voltage IOUT = -XmA* 0.85*VDD V

Table 31: CMOS IO Buffers Generic Characteristics

DC Electrical Characteristics

All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device

Symbol Parameter Test Conditions Min Typ Max Unit

IIN Input leakage current VIN = VSS, VDD -1 1 mA

no pull up/pull down

IOZ Tristate leakage current VIN = VSS, VDD, -1 1 mA

no pull up/pull down

IPU Pull up current VIN = VSS -25 -66 -125 mA

IPD Pull down current VIN = VDD 25 66 125 mA

RPU Pull up resistance VIN = VSS 50 kOhm

RPD Pull down resistance VIN = VDD 50 kOhm

Table 29: IO Buffers Generic DC Characteristics

DC Electrical Characteristics, important for transient but measured at (near) DC

All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device

Symbol Parameter Test Conditions Min Typ Max Unit

CIN Input capacitance @f = 1MHz 5 pF

dI/dt Current derivative 8 mA driver, slew rate control 23.5 mA/ns

8 mA driver, no slew rate control 89 mA/ns

Ipeak Peak current 8 mA driver, slew rate control 85 mA

8 mA driver, no slew rate control 100 mA

COUT Output capacitance @f = 1MHz 7 pF

(also bidirectional

and tristate drivers)

Table 30: IO Buffers Dynamic DC Characteristics

Generic

The values presented in the following

table apply for all inputs and/or outputs

unless specified otherwise.

Specifically they are not influenced by

the choice between CMOS or TTL lev-

els.

MTC-20135

Transient Energy Capabilities

ESD

ESD (Electrostatic Discharge) tests been

performed for the Human Body Model

(HBM) and for the Charged Device

Model (CDM)

The pins of the device are to be able to

withstand minimum1500 V for the HBM

and minimum 250 V for CDM.

Latch-up

The maximum sink or source current

from any pin is limited to 100 mA to

prevent latch-up.

Input/Output TTL Generic

Characteristics

The values presented in the following

table apply for all TTL inputs and/or out-

puts unless specified otherwise.

DC Electrical Characteristics

All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device

Symbol Parameter Test Conditions Min Typ Max Unit

VIL Low level input voltage 0.8 V

VIH High level input voltage 2.0 V

VILHY Low level threshold, falling slow edge < 1 V/ms 0.9 1.35 V

VIHHY High level threshold, rising slow edge < 1 V/ms 1.3 1.9 V

VHY Schmitt trigger hysteresis slow edge < 1 V/ms 0.4 0.7 V

VOL Low level output voltage IOUT = XmA* 0.4 V

VOH High level output voltage IOUT = -XmA* 2.4 V

Table 32: TTL IO buffers generic characteristics

* The reference current is dependent on

the exact buffer chosen and is a part of

the buffer name. The available values

are currently 2, 4 and 8 mA.

MTC-20135

Fig. 27: Pinout ( Topside View)

Pin Layout and Package

The MTC-20135 is packaged in a Standard 144 pin PQFP

Table 34: Pin summary

MTC-20135

Mnemonic Type BS Type Signals Function

Power supply

VDD VSS + 3.3 Volts power supply

VSS OV GROUND

ATC Interface

ALE I C 1 Used to latch the address of the internal register to

be accessed

PCLK I I 1 Processor clock

CSB I I 1 Chip selected to respond to bus cycle.

BE1 I I 1 Address[1] input

WR_RDB I I 1 Specifies the direction of the access cycle

RDYB OZ O 1 Controls the ATC bus cycle termination

INTB O O 1 Requests ATC interrupt service

AD IO B 16 Multiplexed address data bus

OBC_TYPE I-PD I 1 Selects between I960 or generic interface

Test Access Port Interface

TDI I-PU 1 JTAG I/P

TDO OZ 1 JTAG O/P

TCK I-PD 1 JTAG CLOCK

TMS I-PU 1 JTAG IMODE SELECT

TRSTB I-PD 1 JTAG RESET

Analog Front End Interface

AFRXD I I 4 Receive data nibble

AFTXD O O 4 Transmit data nibble

AFTXED O O 4 Transmit echo nibble

CLWD I I 1 Start of word indication

PDOWN O O 1 Power down analog front end

CTRLDATA O O 1 Serial data transmit channel

MCLK I C 1 Master clock

ATM UTOPIA Interface

U_RxData OZ B 8 Utopia RX data

U_TxData I I 8 Utopia TX data

U_RxADDR I I 5 Utopia RX address

U_TxADDR I I 5 Utopia TX address

U_RxCLAV O-Z O 1 Utopia Receive cell available

U_TxCLAV O-Z O 1 Utopia Transmit cell available

U_RxENBB I-TTL I 1 Utopia Receive enable

U_TxENBB I-TTL I 1 Utopia Transmit enable

U_TxSOC I-TTL I 1 Transmit interface Start of Cell indication

U_RxSOC O-Z O 1 Receive interface Start of Cell indication

U_RxCLK I-TTL C 1 Receive interface Utopia clock

U_TxCLK I-TTL C 1 Transmit interface Utopia clock

ATM SLAP Interface

SLR_VAL_S O 1 Data valid indicator interleaved

SLR_VAL_F O 1 Data valid indicator fast

SLR_DATA_S O 2 Data interleaved

SLR_DATA_F O 2 Data fast

SLT_REQ_S O 1 Byte request interleaved

SLT_REQ_F O 1 Byte request fast

SLT_DATA_S I 2 Data

SLT_DATA_F I 2 Fast Data

INTERFACE_CLOCK O 1 Clock for Slap I/F

MTC-20135

SLR_FRAME_I_S O 1 Frame indicator interleaved

SLT_FRAME_I_S O 1 Start of Frame indicator interleaved

SLR_FRAME_F O 1 Frame indicator fast

SLT_FRAME_F O 1 Start of Frame indicator fast

Miscellaneous

GP_IN I-PD I 2 General purpose input

GP_OUT O O 1 General purpose output

RESETB I I I Hard reset

TESTSE I none none Enables scan test mode

IDDq I none none Test pin, active high

I = Input, CMOS levels

I-PU = Input with pull-up resistance, CMOS levels

I-PD = Input with pull-down resistance, CMOS levels

I-TTL = Input TTL levels

O = Push-pull output

OZ = Push-pull output with high-impedance state

IO = input / Tri-state Push-pull output

BS cell = Boundary-Scan cell

I = Input cell

O = Output cell

B = Bidirectional cell

C = Capture cell

Pin Mnemonic Type Supply Driver BS Description

1 VSS OV GROUND

2 AD_0 B VDD BD8SCR B Micro processor interface

3 AD_1 B VDD BD8SCR B Address / Data 1

4 AD_2 B VDD BD8SCR B Address / Data 2

5 VDD + 3.3 Volts power supply

6 AD_3 B VDD BD8SCR B Address / Data 3

7 AD_4 B VDD BD8SCR B Address / Data 4

8 VSS OV GROUND

9 AD_5 B VDD BD8SCR B Address / Data 5

10 AD_6 B VDD BD8SCR B Address / Data 6

11 VDD + 3.3 Volts power supply

12 AD_7 B VDD BD8SCR B Address / Data 7

13 AD_8 B VDD BD8SCR B Address / Data 8

14 AD_9 B VDD BD8SCR B Address / Data 9

15 VSS OV GROUND

16 AD_10 B VDD BD8SCR B Address / Data 10

17 AD_11 B VDD BD8SCR B Address / Data 11

18 VDD + 3.3 Volts power supply

19 AD_12 B VDD BD8SCR B Address / Data 12

20 VSS OV GROUND

21 PCLK I VDD IBUF I Processor clock

22 VDD + 3.3 Volts power supply

23 AD_13 B VDD BD8SCR B Address / Data 13

24 AD_14 B VDD BD8SCR B Address / Data 14

25 AD_15 B VDD BD8SCR B Address / Data 15

26 VSS OV GROUND

27 BE1 I VDD IBUF I Address[1] input

28 ALE I VDD IBUF C Used to latch the address of the internal

29 VDD + 3.3 Volts power supply

30 CSB I VDD IBUF I Chip selected to respond to bus cycle.

31 WR_RDB I VDD IBUF I Specifies the direction of the access

cycle

32 RDYB OZ VDD BT4CR O Bus Cycle ready indication

33 OBC_TYPE I-PD VDD IBUF I ATC Mode Selection

34 INTB O VDD IBUF O Requests ATC interrupt service

35 RESETB I VDD IBUF I Hard reset

36 VSS OV GROUND

37 VDD + 3.3 Volts power supply

38 U_RxData_0 OZ VDD BD8SRC B UTOPIA RX Data 0

39 U_RxData_1 OZ VDD BD8SRC B UTOPIA RX Data 1

40 VSS OV GROUND

41 U_RxData_2 OZ VDD BD8SRC B UTOPIA RX Data 2

42 U_RxData_3 OZ VDD BD8SRC B UTOPIA RX Data 3

43 VDD + 3.3 Volts power supply

44 U_RxData_4 OZ VDD BD8SRC B UTOPIA RX Data 4

45 U_RxData_5 OZ VDD BD8SRC B UTOPIA RX Data 5

46 VSS OV GROUND

47 U_RxData_6 OZ VDD BD8SRC B UTOPIA RX Data 6

48 U_RxData_7 OZ VDD BD8SRC B UTOPIA RX Data 7

49 VDD + 3.3 Volts power supply

MTC-20135

Table 35: Pin List

Pin Mnemonic Type Supply Driver BS Description

50 U_RxADDR_0 I VDD IBUF I UTOPIA RX Address 0

51 U_RxADDR_1 I VDD IBUF I UTOPIA RX Address 1

52 U_RxADDR_2 I VDD IBUF I UTOPIA RX Address 2

53 U_RxADDR_3 I VDD IBUF I UTOPIA RX Address 3

54 VSS OV GROUND

55 U_RxADDR_4 I VDD IBUF I UTOPIA RX Address 4

56 GP_IN_0 I-PD VDD IBUFDQ I General purpose input

57 VDD + 3.3 Volts power supply

58 GP_IN_1 I-PD VDD IBUFDQ I General purpose input 1

59 VSS OV GROUND

60 U_RxRefB O VDD IBUF O

61 U_TxRefB I VDD BT4CR I

62 VDD + 3.3 Volts power supply

63 U_RxCLK I VDD IBUF Receive interface Utopia clock

64 U_RxSOC O-Z VDD BD8SCR Receive interface Start of Cell indication

65 U_RxCLAV O-Z VDD BD8SCR Receive cell available

66 U_RxENBB I VDD IBUF Receive enable

67 VSS + 3.3 volts power supply

68 U_TxCLK I VDD IBUF Transmit interface Utopia clock

69 U_TxSOC I VDD IBUF Transmit interface Start of Cell indication

70 U_TxCLAV O-Z VDD BD8SCR Transmit cell available

71 U_TxENBB I VDD IBUF UTOPIA TX Enable

72 VDD + 3.3 Volts power supply

73 VSS OV GROUND

74 U_TxData_7 I VDD IBUF I UTOPIA TX Data 7

75 U_TxData_6 I VDD IBUF I UTOPIA TX Data 6

76 VDD + 3.3 Volts power supply

77 U_TxData_5 I VDD IBUF I UTOPIA TX Data 5

78 U_TxData_4 I VDD IBUF I UTOPIA TX Data 4

79 U_TxData_3 I VDD IBUF I UTOPIA TX Data 3

80 U_TxData_2 I VDD IBUF I UTOPIA TX Data 2

81 VDD OV GROUND

82 U_TxData_1 I VDD IBUF I UTOPIA TX Data 1

83 U_TxData_0 I VDD IBUF I UTOPIA TX Data 0

84 U_TxADDR_4 I VDD IBUF I UTOPIA TX Addresss 4

85 U_TxADDR_3 I VDD IBUF I UTOPIA TX Addresss 3

86 VDD + 3.3 Volts power supply

87 U_TxADDR_2 I VDD IBUF I UTOPIA TX Addresss 2

88 U_TxADDR_1 I VDD IBUF I UTOPIA TX Addresss 1

89 U_TxADDR_0 I VDD IBUF I UTOPIA TX Addresss 0

90 SLR_FRAME_F O VDD BT4CR Frame Identifier Fast

91 VSS OV GROUND

92 SLR_FRAME_S O VDD BT4CR Frame Identifier Interleaved

93 SLR_DATA_S_1 O VDD BT4CR Data Interleave 1

94 SLR_DATA_S_0 O VDD BT4CR Data Interleave 0

95 VDD + 3.3 Volts power supply

96 SLR_VAL_S O VDD BT4CR Data Valid Indicator Interleaved

97 SLR_DATA_F_1 O VDD BT4CR Data Fast 1

98 SLR_DATA_F_0 O VDD BT4CR Data Fast 0

99 SLR_VAL_F O VDD BT4CR Data Valid Indicator Fast

100 INTERFACE_CLOCK O VDD BT4CR Clock for SLAP I/F

101 SLT_FRAME_F O VDD BT4CR Start of Frame Indicator Fast

102 VSS OV GROUND

MTC-20135

Pin Mnemonic Type Supply Driver BS Description

103 SLT_DATA_F_1 I VDD IBUFDQ Fast Data 1

104 SLT_DATA_F_0 I VDD IBUFDQ Fast Data 0

105 SLT_DATA_S_1 I VDD IBUFDQ Data 1

106 SLT_DATA_S_0 I VDD IBUFDQ Data 0

107 SLT_REQ_F O VDD BT4CR Byte Request Fast

108 VDD + 3.3 Volts power supply

109 VSS OV GROUND

110 SLT_REQ_S O VDD BT4CR Byte Request Interleaved

111 SLT_FRAME_S O VDD BT4CR Start of Frame Indication Interleaved

112 TDI I-PU VDD IBUFUQ JTAG I/P

113 TDO OZ VDD BT4CR JTAG O/P

114 TMS I-PU VDD IBUFUQ JTAG Mode Select

115 VDD + 3.3 Volts power supply

116 TCK I-PD VDD IBUFDQ JTAG Clock

117 VSS OV GROUND

118 TRSTB I-PD VDD IBUFDQ JTAG Reset

119 TESTSE I VDD IBUF none Enables scan test mode

120 GP_OUT O VDD BD8SCR O General purpose output

121 PDOWN O VDD BT4CR O Power down analog front end

122 VDD + 3.3 Volts power supply

123 AFRXD_0 I VDD IBUF I Receive data nibble

124 AFRXD_1 I VDD IBUF I Receive data nibble

125 AFRXD_2 I VDD IBUF I Receive data nibble

126 AFRXD_3 I VDD IBUF I Receive data nibble

127 VSS OV GROUND

128 CLWD I VDD IBUF I Start of word indication

129 MCLK I VDD IBUF C Master clock

130 CTRLDATA O VDD BT4CR O Serial data transmit channel

131 VDD + 3.3 Volts power supply

132 AFTXED_0 O VDD BT4CR O Transmit echo nibble

133 AFTXED_1 O VDD BT4CR O Transmit echo nibble

134 VSS OV GROUND

135 AFTXED_2 O VDD BT4CR O Transmit echo nibble

136 AFTXED_3 O VDD BT4CR O Transmit echo nibble

137 VDD + 3.3 Volts power supply

138 IDDq I VDD IBUF none Test pin, active high

139 AFTXD_0 O VDD BT4CR O Transmit data nibble

140 AFTXD_1 O VDD BT4CR O Transmit data nibble

141 VSS OV GROUND

142 AFTXD_2 O VDD BT4CR O Transmit data nibble

143 AFTXD_3 O VDD BT4CR O Transmit data nibble

144 VDD + 3.3 Volts power supply

Table 36: I/O Driver Function

Driver Function

BD4CR CMOS bidirectional, 4mA, slew rate control

BD8SCR CMOS bidirectional, 8mA, slew rate control, Schmitt trigger

IBUF CMOS input

IBUFDQ CMOS input, pull down, IDDq control

IBUFUQ CMOS input, pull up, IDDq control

MTC-20135

12/98-DS253c

All dimensions are in inches and parenthetically in millimeters. Inches dimensions are approximated.

Drawing revision: 11

Date: 07-06-95

eneral dimensions

1.238(31.45)

1.218(30.95)

.016(0.40)

.008(0.20)

TYP.026(0.65)

.141(3.59)

.125(3.17)

TYP.063(1.60)

MAX .160(4.07)

1.238(31.45)

1.218(30.95)

1.106(28.10)

1.098(27.90)

1.106(28.10)

1.098(27.90)

PIN 1

0 - 10

TYP 0 - 10

.041(1.03)

.026(0.65)

TYP.006(0.15)

MIN .002(0.05)

144 LEAD PQFP / DQFP

DWG.NR.90-0040

Fig.28:Package 144 Lead PQFP

Alcatel Microelectronics acknowledges the trademarks of all companies referred to in this document.

This document contains information on a new product.

Alcatel Microelectronics

reserves the right to make

changes in specifications at any time and without notice.

The information furnished by

Alcatel Microelectronics

in this

document is believed to be accurate and reliable.

However, no responsibility is assumed by

Alcatel

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for its use, nor for any infringements of

patents or other rights of third parties resulting from its use.

No licence is granted under any patents or patent rights

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20059 Vimercate MI

Italy

Tel. +39 039 686 4520

Fax +39 039 686 6899

Stuttgart Office

Schwieberdingerstraße 9

70435 Stuttgart

Germany

Tel. +49 711 821 45 304

Fax +49 711 821 44 619

Westerring 15

9700 Oudenaarde

Belgium

Tel. +32 55 33 24 70

Fax +32 55 33 27 68

USA

M/S 412-115

1225 N. Alma Road

Richardson

TX 75081-2206

Tel. +1 972 996 2489

Fax +1 972 996 2503

Sales &

Design Centres

Marketing &

Design Centre Headquarters

Manufacturing

& Customer Service

Alcatel Microelectronics

info@mie.alcatel.be

http://www.alcatel.com/telecom/micro

Benelux & Nordic

Countries

Excelsiorlaan 44-46

1930 Zaventem

Belgium

Tel. +32 2 718 18 11

Fax +32 2 725 37 49

Northern Germany

TRIAS

Moerser Landstraße 408

47802 Krefeld

Germany

Tel. +49 2151 95 30 10

Fax +49 2151 95 30 105

Representatives

Taiwan ROC

Alcatel ITS Ltd

Suite D, 8th floor 133

Section 3, Min Seng E. Rd

Taipei 015,

Taiwan

Tel. +886 2 717 1255

Fax +886 2 717 1250

Japan

Alcatel ITS Japan Ltd

Yubisu Gdn Pl Twr 24

20-3 Ebisu 4-chrome,

Shibuyaku

Tokyo, 150, Japan

Tel. +81 3 5424 8561

Fax +81 3 5424 8581

Alfa-µ Comp.

Springfield Hse, Cranes Rd

Sheborne St. John

Basingstoke, HA RG24 9LJ

United Kingdom

Tel. +44 12 56 851 770

Fax +44 12 56 851 771