SIEMENS SAB 8085AH 8-Bit Microprocessor SAB 8085AH (3 MHz} SAB 8085AH-2 (5 MHz) @ Single +5V Power Supply with + 10% @ Four Vectored Interrupt Inputs (one is Voltage Margins Non-Maskable} Plus an SAB 8080A @ 30% Less Joc than SAB 8085A Compatible Interrupt @ 100% Software Compatible with SAB 8080A @ Serial In/Serial Out Port @ 1.3 us Instruction Cycle (SAB 8085AH); @ Decimal, Binary and Double Precision 0.8 us (SAB 8085AH-2) Arithmetic @ On-Chip Clock Generator (with External Crystal, @ Direct Addressing Capability to 64K LC or RC Network) Bytes of Memory @On-Chip System Controller; Advanced Cycle Status Information Available for Large System Control Pin Diagram Pin Names LF xO aD Ke AeAys | Address Bus INTA Interrupt Acknowledge et Ho AD,AD, | Mux. Address/ RST 5.5, | Restart Interrupts out 45 SL HLOK Data Bus 6.5, 7.5 sete Gwenn ALE Address Latch Enable |] TRAP Trap sear Cle 5 Daeanv So, Si, Machine Cycle Status |} RESET IN} Reset in ast 7547 wom 10/M RESET | Reset out astesCla sts, RD Read Control OUT ast 55(18 hye WR Write Control My, Xz Crystal/Clock Input wrecjo SAB om READY Ready CLK Clock Output mmn PAN bate HOLD Hold SID Serial Input Data AD, L112 aD HLDA Hold Acknowledge SOD Serial Output Data ad, C3 21] Ay INTR Interrupt Request Voc +5V aD, 4 aay Veg Ground (OV} AD, (15 Ol Ay AD, [16 25(7 hg ADs [17 #4, AD, (]18 2B] Ay aD; ((]19 22(7] Ag Ms C]20 PAs SAB 8085AH is a complete 8 bit parallel Central (system controller) provided for the SAB BO80A, Processing Unit (CPU). Its instruction set is 100% thereby offering a high level of system integration. software compatible with the SAB 8080A micro- The SAB 8085AH uses a multiplexed data bus. processor. Its high level of system integration The address is split between the 8 bit address bus allows a minimum of three IC's [SAB 8085AH (CPU}, and the 8 bit data bus. The on-chip address latches SAB 8156 (RAM/IO) and SAB 8355/SAB 87554 of SAB 8155/SAB 8156/SAB 8355/SAB 8755A (ROM/PROM/|0}} while maintaining total system memory products allow a direct interface with the expandability. The SAB 8085AH-2 is a faster SAB 8085AH. version of the SAB 8085AH. SAB 8085AH is implemented in +5V advanced The SAB 8085AH incorporates all of the features N-channel, silicon gate Siemens MYMOS technolagy that the SAB 8224 (clock generator) and SAB 8228 and is a selected version of the standard SAB 8085A. 35 August 1985SAB 8085AH Pin Definitions and Functions Symbol Number Input {{) Output (O} Function Xe X2 1,2 X, AND X, Are connected to a crystal, LC, or RC network to drive the internal clock generator. X, can also be an external clock input from a jagic gate. The input frequency is divided by 2 to give the processor's internal operating frequency. RESET OUT RESET OUT Reset Out indicates CPU is being reset. Can be used as a system reset. The signal is synchronized to the processor clock and lasts an integral number of clock periods SOD SERIAL GUTPUT DATA LINE The output SOD is set or reset as specified by the SIM instruction. SID SERIALINPUT DATA LINE - The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed. TRAP TRAP Trap interrupt is a nonmaskable RESTART inter- rupt. It is recognized at the same time as INTR or RST 5.5- 7.5. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt (see following table). RST 5.5 RST 6.5 RST 7.5 ~1 00 60 RESTART INTERRUPTS These three inputs have the same timing as INTR except they cause an internal RESTART to be automatically inserted. The priority of these interrupts is ordered as shown in the following table. These interrupts have a higher priority than INTR. In addition, they may be individually masked out using the SIM instruction. INTR 10 INTERRUPT REQUEST Is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle of an instruction and during Hold and Halt states. If it is active, the Program Counter (PC} will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted. INFA 11 INTERRUPT ACKNOWLEDGE - Is used instead of (and has the same timing as) RD during the instruction cycle after an NTR is accepted. It can be used to activate an SAB 8259A Interrupt chip or some other interrupt port. AD)AD; 12-19 oO MULTIPLEXED ADDRESS/DATA BUS - Lower 8 bits of the memory address {or l/O address) appear on the bus during the first clock cycle (T state) of a machine cycle. It then becomes the data bus during the second and third clock cycles. AsAus 21-28 ADDRESS BUS -The most significant 8 bits of the memory address or the & bits of the I/O address, 3-stated during Hold and Halt modes and during RESET. 36SAB 8085AH Symbol Number Input {I} Output (O) Function Se. Si, and 1O/M 29, 33 34 G MACHINE CYCLE STATUS 1Io/M Status Memory write Memory read 1/0 write 1/O read Opcode fetch Opcode fetch Interrupt Acknowledge Halt Hold Reset * = 3-state (high impedance} X = unspecified S, can be used as an advanced R/W status. |O/M, S,and S$, become valid at the beginning of a machine cycle and remain stable throughout the cycle. The falling edge of ALE may be used to Jatch the state of these lines. ke kr RGA OS ALE 30 ADDRESS LATCH ENABLE - It occurs during the first clock state of a machine cycle and enables the address to get latched into the on-chip jatch of peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information. The falling edge of ALE can also be used to strobe the status information. ALE is never 3-stated. 31 WRITE CONTROL A low level on WR indicates the data on the Data Bus is to be written into the selected memory or I/O location. Data is set up at the trailing edge of WR. 3-stated during Hold and Halt modes and during RESET. 32 READ CONTROL A low level on RD indicates the selected memory or I/O device is to be read and that the Data Bus is available for the data transfer, 3-stated during Hold and Halt modes and during RESET. READY 35 READY If READY is high during a read or write cycle, it indicates that the memory cr peripheral is ready to send or receive data. lf READY is low, the CPU will wait an integral number of clock cycles for READY to go high before completing the read or write cycle. READY must conform to specified setup and hold times. RESET IN 36 RESET IN Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops. The data and address buses and the control jines are 3-stated during RESET and because of the asynchronous nature of RESET, the processor's internal registers and flags may be altered by RESET with unpredictable results. RESET INis a Schmitt-triggered input, allowing connection to an RC network for power-on RESET delay. The CPU is held inthe reset condition as long as RESET IN is applied. CLK 37 CLOCK Clock output for use as a system clock. The period of CLK is twice the X,, X, input period. 37SAB 8085AH Symbol Number Input (I) Output (O) Function HLDA 33 0 HOLD ACKNOWLEDGE - Indicates that the CPU has received the HOLD request and that it will relinquish the bus in the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the bus one half clock cycle after HLDA goes low. HOLD 39 HOLD - !ndicates that another master is requesting the use of the address and data buses. The CPU, upon receiving the hold request, will relinquish the use of the bus as soon as the completion of the current bus transfer. internal processing can continue. The processor can regain the bus only after the HOLD is removed. When the HOLD is acknowledged, the Address, Data RD, WR, and 10/M lines are 3-stated. Voc 40 POWER SUPPLY (+5V) Vg 20 GROUND (OV) Functional Block Diagram INTA RST6.5 TRAP INTR | RSTS5 ey" SID soo Interrupt control Serial 1/0 control {t 8-Bit Internal Qala Bus ft \ ? Ac lat Te Req. Instruction cumulalor emp. Reg e) Register () Flag (5) Aip-Flops Instruction B-Reg. 4,5) C-Regya) Avithmeti decades nithmetic and D-A E-Reg. logic machine Fig) TS t8) unit f cycle - - (ALU) encoding He Regia] R916 | Register (8) artay Stack pointer tie) Po m +5 supply GON . Program counter (4p) Inctementer/decrementer Address latch (16) XI Timing and control NZ J NZ Yq CLK RESET talk b ; GEN CONTROL STATUS DMA S Adiress buffer (5) Data/Adiress buffer CLK QUT RO WR ALE Sg 5S, IOV HLDA RESET OUT It it READY HOLD RESET IN Ayg-Ap AD7-ADg Address. bus Address/Data bus. 38SAB 8085AH Interrupt Priority, Restart Address, and Sensitivity Dot: Address Branched To" Name Priority When Interrupt Occurs Type Trigger TRAP 1 24H Rising edge AND high ievel until sampled RST 7.5 2 3CH Rising edge (latched) RST 6.5 3 34H High level until sampled RST 5.5 4 2CH High level until sampled INTR 5 see Note 2 High level until sampled NOTES 1. The processor pushes the PC on the stack before branching to the indicated address. 2. The address branched to depends on the instruction provided to the CPU when the interrupt is acknowledged. Functional Description The SAB 80854H is a complete 8-bit parallel central processor. It is designed with N-channel depletion loads and requires a single +5 volt supply. Its basic clock speed is 3 MHz (SAB 8085AH) or 5 MHz (SAB 8085AH-2), thus improving on SAB 80B0A's performance with higher system speed. Also it is designed to fit into a minimum system of three ICs: The CPU (SAB 8085AH)}), a RAM/IO (SAB 8156), and a ROM or EPROM/IO chip (SAB 8355 or SAB 8755A)., The SAB 8085AH has twelve addressable -bit registers. Four of them can function only as two 16-bit register pairs. Six others can be used inter- changeably as 8-bit registers or as 16-bit register pairs. The SAB 8085AH register set is as follows: Mnemonic| Register Contents ACCorA_ | Accumulator 8 bits PC Program Counter | 16-bit address BC, DE, HL| General-Purpose | 8 bits x 60r Registers; data 16 bits x 3 pointer (HL) SP Stack Pointer 16-bit address Flags or F | Flag Register 5 flags (8-bit space) The SAB 8085AH uses a multiplexed Data Bus. The address is split between the higher 8-bit Address Bus and the lower 8-bit Address/Data Bus. During the first T state (clock cycle) of a machine cycle the low order address is sent out on the Address/ Data bus. These lower 8 bits may be latched externally by the Address Latch Enable signal (ALE). During the rest of the machine cycle the data bus is used for memory or I/O data. 39 The SAB 8085AH provides RD, WR, Sq, S, and |O/M signals for bus control. An Interrupt Acknowledge signal (INTA) is also provided. HOLD and all Interrupts are synchronized with the processors internal clock. The SAB 8085AH also provides Serial Input Data (SID) and Serial Output Data {SOD} lines for simpie serial interface. In addition to these features, the SAB 8085AH has three maskable, vector interrupt pins and one nonmaskable TRAP interrupt. Interrupt and Serial i/O The SAB 8085AH has 5 interrupt inputs: INTR, RST 5.5, RST 6.5, RST 7.5, and TRAP. INTR is identical in function to the SAB 8080A INT. Each of the three RESTART inputs, 5.5, 6.5, and 7.5, has a programmable mask. TRAP is also a RESTART interrupt but it is nonmaskable. The three maskable interrupts cause the internal execution of RESTART (saving the program counter in the stack and branching to the RESTART address) if the interrupts are enabled and if the interrupt mask is not set. The non-maskable TRAP causes the internal execution of aRESTART vector independent of the state of the interrupt enable or masks (see table above). There are two different types of inputs in the restart interrupts. RST 5.5 and RST 6.5 are high level- sensitive like INTR (and INT on the SAB 8080} and are recognized with the same timing as INTR. RST 7.5 is rising edge-sensitive. For RST 7.5, only a pulse is required to set an internal flip-flop which generates the internal interrupt request. The RST 7.5 request flip-flop remains set until the request is serviced. Then it is reset automatically. This flip-flop may also be resetSAB 8085AH by using the SIM instruction or by issuing aRESETIN to the SAB 8085AH. The RST 7.5 internal flip-flop will be set by a pulse on the RST 7.5 pin even when the RST 7.5 interrupt is masked out. The status of the three RST interrupt masks can only be affected by the SIM instruction and RESET IN. The interrupts are arranged in a fixed priority that determines which interrupt is to be recognized if more than one is pending as follows: TRAP highest priority, RST 7.5, RST 6.5, RST 5.5, INTR lowest priority. This priority scheme does not take into account the priority of a routine that was started by a higher priority interrupt. RST 5.5 can interrupt an RST 7.5 routine if the interrupts are re-enabled before the end of the RST 7.5 routine. The TRAP interrupt is useful for catastrophic events such as power failure or bus error. The TRAP input is recognized just as any other interrupt but has the highest priority. It is not affected by any flag or mask. The TRAP input is both edge and level sensitive. The TRAP input must go high and remain high until it is acknowledged. It will not be recognized again until it goes low, then high again. This avoids any false triggering due to noise or logic glitches. The following figure illustrates the TRAP interrupt request circuitry within the SAB 8085AH. Note that the servicing of any interrupt (TRAP, RST 7.5, RST 6.5, RST 5.5, INTR} disables all future interrupts (except TRAPs) until an El instruction is executed. The TRAP interrupt is special in that it disables interrupts, but preserves the previous interrupt enable status. Performing the first RIM instruction following a TRAP interrupt allows you to determine whether interrupts were enabled or disabled prior to the TRAP. All subsequent RIM instructions provide current interrupt enable status. Performing a RIM instruction following INTR or RST 5.57.5 will provide current Interrupt Enable status, revealing that Interrupts are disabled. The serial |/O system is also controlled by the RIM and SIM instructions. SID is read by RIM, and SIM sets the SOD data. TRAP- Acknowledge TRAP and RESET in Circuit External TRAP inside the Interrupt SAB 8085AH Request _ Reset In Schmitt - TRAP Trigger | Reset a Interrupt i Request CLK +5Vj4 D D- Q Flip-Flop fps Internal TRAP-Flip- Fiop Driving the X, and X, Inputs You may drive the clock inputs of the SAB 80854AH or SAB 8085AH-2 with a crystal, an LC tuned circuit, an RC network, or an external clock source. The driv- 40 ing frequency must be at least 1 MHz, and must be twice the desired internal clock frequency; hence, the SAB 8085AH is operated with a 6 MHz crystal (for 3 MHz clock}, and the SAB 8085AH-2 can be operated with a 10 MHz crystal (for 5 MHz clock).SAB 8085AH If a crystal is used, it must have the following characteristics: Parallel resonance at twice the clock frequency desired C, (load capacitance) = 30 pf C, (shunt capacitance) = 7 pf R, (equivalent shunt resistance) = 75 Ohms Drive level: 10 mW Frequency tolerance: +.005% (suggested) Note the use of the 20 pF capacitor between X, and ground. This capacitor is required with crystal frequencies below 4 MHz to assure oscillator startup at the correct frequency. A parallel-resonant LC circuit may be used as the frequency-determining network for the SAB 8085AH, providing that its frequency tolerance of approximately + 10% is acceptable. The components are from the formula: 1 f = _____ 2m VL (Cog + Ciny To minimize variations in frequency, it is recom- mended that you choose a value for C,,, that is at least twice that of C,,,, or 30 pF. The use of an LC circuit is not recommended for frequencies higher than approximately 5 MHz. An RC circuit may be used as the frequency-deter- mining network for the SAB 8085AH if maintaining a precise clock frequency is of no importance. Variations in the on-chip timing generation can cause a wide variation in frequency when using the RC mode. lts advantage is its low component costs. The driving frequency generated by the circuit shown is approximately 3 MHz. Itis not recommend- ed that frequencies greatly higher or lower than this be attempted. The following figures show the recommended clock driver circuits. Note in D and E that pullup resistors are required to assure that the high levei voltage of the input is at least 4V. For driving frequencies up to and including 6 MHz you may supply the driving signa! to X, and leave X; opencircuited {Figure D). If the driving frequency is from 6 MHz to 10 MHz, stability of the clock generator wilt be improved by driving both X, and X%, with a pushpull source (Figure E). To prevent self-oscillation of the SAB 8085AH, be sure that Xz is not coupled back to X, through the driving circuit. Clock Driver Circuits A) Quartz Crystal Clock Driver X SAB 8085AH PO | 1 | | Cl CJ Cint = m2 19 pF #) | 20pF 9 Po X) *) 20pF Capacitors required far Crystal Frequency <4MHz only. B) LC Tuned Circuit Clock Driver i x SAB 8085AH Ly 1 | | Lext B= Cent Cure 1S pF | 2 | i _ Ly, 41SAB 8085AH C) RC Circujt Clock Driver SAB 8085AH D} 16 MHz Input Frequency External Clock Driver Circuit +5 470Q Low time> 60 ns to kQ Lo |} } " *) X *) X> left floating E) 110 MHz Input Frequency External Clock Driver Circuit +6V Low time => 40ns 42SAB 8085AH Generating Wait State If your system requirements are such that slow As in the SAB 8080, the READY line is used to memories or peripheral devices are being used, extend the read and write pulse lengths so that the the circuit shown in the following figure may be SAB 8085AH can be used with slow memory. used to insert one WAIT state in each HOLD causes the CPU to relinquish the bus when it SAB 8085AH machine cycle. is through with it by floating the Address and Data Buses. The D flip-flops should be chosen so that @ CLK is rising edge-triggered @ CLEAR is low-level active. Generation of a Wait State for SAB 8085AH CPU ~ CLEAR x} ALE *] CLK CLK Output CLK SAB 8085AH 9 3 7 5 oo a i Flip-Flo Flip-Flop ~ BOBS, SV D pee 0 P Ready Input *} ALE and CLK (Out) should be buffered if CLK Input of Latch Exceeds SAB 8085AH IOL or IOH. System Interface This minimum system, using the standard I/O technique i h in the following fi . The SAB 8085A family includes memory compo- ee nique is as shown in the Tolowing tigure nents, which are directly compatible to the In addition to standard I/O, the memory mapped I/O SAB 8085AH CPU. For example, a system con- offers an efficient I/O addressing technique. With sisting of the three chips, SAB 8085AH, SAB 8156, this technique, an area of memory address space is and SAB 8355 will have the following features: assigned for I/O address, thereby, using the memory address for 1/0 manipulation. The figure Sone eee aoa on page 11 shows the system configuration of 8 counter Memory Mapped I/O using SAB 8085AH. @4 bit I/O Ports The SAB 8085AH CPU can also interface with the @1 6bit1/O Port standard memory that does not have the multi- @ 4 Interrupt Levels plexed address/data bus. lt will require a simple @ Serial In/Serial Out Ports SAB 8282 (8-bit latch) as shown in the figure on page 12. 43SAB 8085AH us SAB 8085AH Minimum System (Standard I/O Technique) V 5S ; c fy Trap Xt X2 RST 75 RST 65 RST55 INFR INTA# ADDR Data ALE RESET IN# ~ SAB 8085AH RESET RO# WR#IO/M Out RDY CLK HOLD HLDA fF $OD SID $1 {a (8} * Kes >| RO # > ALE PortaA (8) : CE WR # Part B SAB Oata/ 16 ADDR 10/M# RESET PortC Timer IN Timer OUT de Uy uy | %} Optional Connection lOW# RD # ALE CE # Part AB-A10 SAB B355/ Data S755A ADDR > RESET RDY cLK Hg IOR# ff Vs Vic oo PROG 4 -- V er + _ Ver Lt Ver MPO0109 44SAB 8085AH SAB 8085AH Minimum System (Memory Mapped I/O) i 1 Voc Voc Voc Sra es SAB 8355 (ROM+1/O} cr SAB 8755A(PROM +1/0) iO/M AD, -AD?7 CE ALE ALE Ag Ais KAD KO7 D WR \O/M CLK Reset Out Ready SAB 8156 (RAM +1/0+Counter/Timer} B (8) (6) SAB 8085AH x) Optional Connection ! Timer out 45SAB 8085AH SAB 8085AH System (Using Standard Memories) Oo Fy a] TRAP X| X3 Reset in HOLD ~]| RST 7 HLDA RST 6 SAB $00|-~ ~] RST 5 8085AH SiO NTR 8 _INTA ADDR/ oe Reset Saf ADOR Data ALE RD WR I0/M Out RDY CLK ~N Ka) (ay i lo/M (Cs) WR SAB aN p82 [| RD K Data Standard Memory "> ADDR (CS) (16) CLK Reset 10/MICS) WR 1/0 Ports, RD Controls Data Standard 40 >) ADOR S=& c \Z V4 = 46SAB 8085AH Basic System Timing The SAB 8085AH has a multiplexed Data Bus. ALE cycle (as would occur during processing of the OUT is used as a strobe to sample the lower 8-bits of instruction). Note that during the I/O write and read address onthe Data Bus. The followingfigureshows cycle that the I/O port address is copied on both, the an instruction fetch, memory read and I/O write upper and lower half of the address. SAB 8085AH Basic System Timing M,; Me Mg CLK Ty Ts Ts Ts T lh T Ty Th & \T | Ag- Ais PC,,{high order Address) (PO+1), 10. Port {Low order Data from Memory Data from Memor Data to Memory Address) (Instruction) (1/0 Port Address or Peripheral ae [ff \ [\ [\ na . _ Status S, Sq (Fetch) XxX 10 (Read) @1 (Write) 1" 47SAB 8085AH There are seven possible types of machine cycles. Which of these seven takes place is defined by the status of the three status lines (IO/M, S1, Sp) and the three control signals (RD, WR, and INTA); (see since they become active at the T; state, at the outset of each maching cycle. Control lines RD and WR become active later, at the time when the transfer of data is to take place, so are used as command following table}. The status lines can be used as advanced controls (fordeviceselection,forexample)}, SAB 8085AH Machine Cycle Chart lines. Status Control Machine Cycle 10/M $1 S@ RDB WR INTA Opcode Fetch (OF) @ 1 1 @ 1 1 Memory Read Q 1 0 @ 1 1 Memory Write 0 0 1 1 0 1 I/O Read (IOR) 1 1 a 0 1 1 1/0 Write (lOW) 1 g 1 1 @ 1 Acknowledge for INTR (INA) 1 1 1 1 1 Q Bus Idle (BI): DAB a 1 1 1 1 ACK of RST, TRAP 1 1 1 1 1 1 HALT TS Q 0 TS TS 1 @ = Logic @"'; 1 = Lagic 1; TS = High Impedance or HOLD states are forced by the receipt of READY or HOLD inputs). Any T state must be one of ten possible states, as summarized in the following table. A machine cycle normally consists of three T states, with the exception of OPCODE FETCH, which normally has either four or six T states (unless WAIT SAB 8085AH Machine State Chart Machine Status and Buses Control State $1,809 |10/M Ac-Ai; | AD,-AD, |RD,WR |INTA ALE T, x 4 x x 1 1 1) To x x x x x x 6 Twwart x xX x x x x Ts x xX x x xX x @ Ta 1 07) x TS 1 1 0 Ts 1 @?) x TS 1 1 0 Ts 1 @7) x TS 1 1 @ Treser x TS TS Ts TS 1 0 Twatt 9 TS TS TS TS 1 0 Tyowp x TS TS TS Ts 1 a @ = Logic @"; 1 = Logic 1; TS = High Impedance; X = Unspecified. *) ALE not generated during 2nd and 3nd machine cycles of DAD instruction. -2410/M = 1 during Ts-T; of INA machine cycle. 48SAB 8085AH Instruction Set Summary Instruction Code Operations Mnemonic DBD OB ODF DB OD, BM OD, Ds Description MOVE, LOAD, AND STORE MOvr1 r2 0 1 DBD OD Ss 5 Move register to register MOV M.r 6 1 1 1 S S8 & Move register to memory MOV r.M 0 1 D DB OD 1 1 0 Move memory to register MVIr Q 0 D DB OD 1 1 9 Move immediate register MvVI M @ 0 1 1 Q 1 1 q Move immeciate memory LXIB o @ @ @ @ @ @ 1 Load immediate register Pair B & C LXID @ @ @ 1 @ 9 @ 1 Load immediate register Pair D & E LXIH @6@ 1 40 60 @ @ 1 Load immediate register Pair H & L STAX B @ @ @ @ @ @ 1 @ Store A indirect STAXD o @ 60 1 @ @ 1 @ Store A indirect LDAX B @ @ @ t+ 1 6 Load A indirect LDAX D 0 90 1 1 0 1 0 Load A indirect STA @ 1 1 @ @ 1 @ Store A direct LDA 6 @ 1 1 1 @ 1 @ Load A direct SHLD 0 0 1 0 0 0 1 0 Store H & L direct LHLO 0 0 1 0 1 0 1 0 Load H & L direct XCHG 1 1 1 0 1 Q 1 1 Exchange D & E, H & L Registers STACK OPS PUSH B 1 1 6 6 6 1 9 1 Push register Pair B & C an stack PUSH DB 1 1 @ 1 0 1 9 1 Push register Pair D & E on stack PUSH H 1 1 1 @ 6 1 0 1 Push register Pair H & L on stack PUSH PSW 1 1 1 1 0 1 Q 1 Push A and Flags on stack POP B 1 1 # @ 6 @ @ 1 Pop register Pair B & C off stack POP D 1 1 1 6 % @O 1 Pop register Pair D & E off stack POP H 1 1 1 @ @ @ 1 Pop register Pair H & L off stack POP PSW 1 1 1 1 @ @ @ 1 Pop A and Flags off stack XTHL 1 1 1 @ 0 1 1 Exchange top of stack, H & L SPHL 1 1 1 1 1 Q @ 1 H & L to stack pointer LXISP 6 @ 1 1 @ @ @ 1 Load immediate stack pointer INX SP 0 @ #1 1 @ 68 1 1 Increment stack pointer DCX SP o 1 1 1 0 1 1 Decrement stack pointer JUMP JMP 1 1 @ 8 @ @ 1 1 Jump unconditional Jc 1 1 a 1 1 0 1 0 Jump on carry JNC 1 1 @ 1 60 %@ 1 @ Jump on no carry JZ 1 1 @ Q 1 Q 1 Jump on zero JNZ 1 1 @ 6 @ 14 @ Jump on no zero JP 1 1 1 1 o 6 1 @ Jump on positive JM 1 1 1 #1 1 @ 1 Jump on minus JPE 1 1 1 @ 1 Q 1 0 Jump on parity even JPO 1 1 1 @ 6 @ 14 @ Jump on perity odd PCHL 1 1 1 G 1 eo 6 1 H & L to program counter 49SAB 8085AH Instruction Set Summary (Cont'd) Instruction Code Gperations Mnemonic D OB Ds O DD; D. D, De Description CALL CALL 1 1 @ @ 1 1 0 1 Call unconditional cc 1 1 @ 1 1 1 6 $6 Call on carry CNC 1 1 1 0 1 o @ Call on no carry CZ 1 1 @ @ 1 1 o 66 Call on zerro CNZ 1 1 @ 68 1 6 Call on no zerro cP 1 1 1 1 @ 1 9 @ Call on positive CM 1 1 1 1 1 1 o Call on minus CPE 1 1 1 @ 1 1 @ OB Call on parity even cPO 1 1 7 8 @ 1 60 @ Call on parity odd RETURN RET 1 1 9 0 1 @ 9 1 Return RC 1 1 0 1 1 6 @ @ Return on carry RNC 1 1 @ 1 o 6 @ @ Return on no carry RZ 1 1 0 1 6 @ Return on zero RNZ 1 1 @ @ 6 @ @ Return on no zero RP 1 1 1 1 6 6 @ 6 Return on positive RM 1 1 1 1 1 o @ @ Return on minus RPE 1 1 1 @ 1 6 6 Return on parity even RPO 1 #1 1 @ @ @ Return on parity odd RESTART RST 1 1 A A A 1 1 1 Restart INPUT/OUTPUT IN 1 1 Q t 0 1 1 Input OUT 1 1 @ 1 4 8 1 1 Output INCREMENT AND DECREMENT INR r o @ DB B DB 1 @ @ Increment register DCRr @ @ D DB oO 1 q 1 Decrement register INR M 0 1 1 @ 1 o 9 Increment memory DCRM o 1 1 0 1 @ 1 Decrement memory INX B o @ @ @ @ 8 1 = 1 increment B & C registers INX D o @ @ 1 @ 6 1 1 increment D &E registers INX H o @ 1 4 @ @ 1 1 Increment H & L registers DCX B o @ 6 @ 1 @ 1 1 Decrement B & C pcx D o oo 6 1 1 @ 1 1 Decrement D&E DCXH 0 @ 1 @ 1 0 1 1 Decrement H & L ADD ADD r 1 9 6 @ @ S&S $ 5 Add register to A ADCr 1 0 6 1 S s Add register to A with carry ADD M 1 o c @ @ 1 1 0 Add memory to A ADC M 1 @ 8b @ 1 1 1 @ Add memory to A with carry ADI 1 1 6 6 6 1 1 0 Add immediate to A ACI 1 1 0 Q 1 1 t 0 Add immediate to A with carry DAD B | 0 6 0 9 1 a % 1 Add B&CtoHRL DAD D a6 64 1 71 @ 1 Add D&EtoH&L DAD H a @ 1 Q 1 a @ 1 AddH&LtoH &L DAD SP @@ 74 7 14 @ @ 1 Add stack pointer to H&LSAB 8085AH Instruction Set Summary (Contd} Instruction Code Operations Mnemonic D, De Ds Ds Ds DBD, D, Dg Description SUBTRACT SUBr 1 @ @ 1 @ Ss 8 5 Subtract register from A SBBr 1 @ @ 1 1 Ss S Subtract register from A with borrow SUBM 1 @ @O 1 0 1 1 Q Subtract memory from A SBBM 1 @ 0 1 1 1 1 Q Subtract memory from A with borrow SUI 1 1 #@ 1 a 1 0 Subtract immediate from A SBI 1 1 g 1 1 1 1 @ Subtract immediate from A with borrow LOGICAL ANAr 1 o 1 @ S&S 5S And register with A XRAr 1 0 1 Q 1 Ss $8 5 Exclusive OR register with A ORAr 1 o 1 1 Ss Ss OR register with A CMP r 1 0 1 1 1 s $s 5 Compare register with A ANAM 1 6 1 406 80 14 1 @ And memory with A XRAM 1 0 1 Q 1 1 1 q Exclusive OR memory with A ORAM 1 Q 1 1 0 1 1 q OR memory with A CMP M 1 @ 1 1 1 1 1 q Compare memory with A ANI 1 1 1 6 1 1 Q And immediate with A XRI 1 1 1 % 1 1 1 9 Exclusive OR immediate with A ORI 1 1 1 1 o 1 1 0 OR immediate with A CPI 1 1 1 1 1 1 T Q Compare immediate with A ROTATE RLC 6 @ 0 @ 1 1 #1 Rotate A left RRC 6 @ 6 1 1 1 1 Rotate A right RAL 6 @ 14 @ 1 1 1 Rotate A left throught carry RAR o 4 1 1 1 1 1 Rotate A right through carry SPECIALS CMA o 1 6 1 1 1 1 Complement A sTCc @ 6 1 1 0 1 1 1 Set carry CMC Q 0 1 1 1 1 1 1 Complement carry DAA o 1 @ 0 1 1 1 Decimal adjust A CONTROL El 1 1 1 1 1 0 1 1 Enable interrupts DI 1 1 1 1 @ 696 1 1 Disable Interrupt NOP 9 @ @ @ 0 8 @ No-operation HLT Q 1 1 1 a 1 1 0 Halt NEW SAB 8085AH INSTRUCTIONS RIM o 9 1 @ @ @8 4 Read Interrupt Mask SIM @ 9 1 1 09 O68 @ Set Interrupt Mask NOTES 1. DDS or SSS: B 000, C 001, 0010, E011, H t00, L 101, Memory 110, A 111. 2. Two possible cycle times (6/12) indicate instruction cycles dependent on condition flags. * All mnemonic copyrighted Intel Corporation 1976. 51SAB 8085AH Absolute maximum ratings *) Ambient Temperature Under Bias Oto 70C Storage Temperature 65 to + 150C Voltage on any Pin with Respect to Ground -0.5t0 +7V Power Dissipation 1.5 Watt D.C. Characteristics Ta = Oto 70C: Vee = 5V +10%; Veg = OV; (unless otherwise specified) Symbol Parameter Limit Values Units Test Conditions Min. Max. Vit Input Low Voltage 0.5 +0.8 Vin Input High Voltage 2.0 Vecot+0.5 Vv VoL Output Low Voltage - 0.45 Ip, =2mMA Vou Output High Voltage 2.4 - Ton = ~400 pA Tec Power Supply Current 120 mA - fi Input Leakage - +10 WA 0 = Vin < Vec tio Output Leakage 0.45V = Vout S Vee Vitr Input Low Level, RESET 0.5 +0.8 Vink Input High Level, RESET 2.4 Vect+ 0.5 | V - Vay Hysteresis, RESET 0.25 *) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 52SAB 8085AH A.C. Characteristics Ta = Oto 70C; Ver = 5V + 10%; Veg = OV Symbol Parameter Limit Values Units SAB 8085AH-2? | SAB 8085AH?) Min. Max. Min. Max. teve CLK Cycle Period 320 2000 200 2000 t CLK Low Time (Standard CLK Loading) 80 40 _ & CLK High Time Standard CLK Loading) 120 70 tet CLK Rise and Fall Time 30 - 30 tyer X, Rising to CLK Rising 30 120 30 100 tyne X, Rising to CLK Failing 150 110 tac AgAys Valid to Leading Edge of Control *'| 270 _ 6 _ tac. AgA; Valid to Leading Edge of Control 240 tap AgAts Valid to Valid Data In 575 350 tara Address Float After Leading Edge of ~ ~ READ (NTA) 0 0 tat AgAis Valid Before Trailing Edge of ALE") 115 _ 50 _ tau AgAy Valid Before Trailing Edge of ALE | 90 tary READY Valid from Address Valid _ 220 - 100 ns toa Address (Ag~Ajgs) Valid After Contral 120 60 tec Width of Control Low . (RD, WR, INTA) 400 _ 230 _ ter Trailing Edge of Control to Leading Edge | 50 25 of ALE tow Data Valid to Trailing Edge of WRITE 420 230 tHAgE HLDA to Bus Enable _ 210 _ 150 tage Bus Float After HLDA tuack HLDA Valid to Trailing Edge of CLK 110 40 thou HOLD Hold Time 0 0 thos HOLD Setup Time to Trailing Edge of CLK | 170 120 tive INTR Hold Time 0 0 tins . INTR, RST, and TRAP Setup Time to 160 - 150 - Falling Edge of CLK tla Address Hold Time After ALE 100 50 tic Trailing Edge of ALE to Leading Edge 130 60 of Control tick ALE Low During CLK High 100 50 Notes see next page. 33SAB 8085AH A.C. Characteristics (continued) Symbol | Parameter Limit Values Units SAB 8085AH) SAB 8085AH-27) Min. Max. Min. Max. tipr ALE to Valid Data During Read 460 270 tlow ALE to Valid Data During Write 200 120 ti ALE Width 140 - 80 - tiry ALE to READY Stable _ 110 - 30 trac Trailing Edge of READ to Re-Enabling 150 - 90 - of Address tro READ (or INTA} to Valid Data - 300 - 150 tay Control Trailing Edge to Leading Edge 400 220 ns of Next Control tape Data Hold Time After READ INTA 0 0 as tev READY Hold Time - - tavs READY Setup Time to Leading Edge 110 100 of CLK two Data Valid After Trailing Edge of WRITE =| 100 60 two LEADING dge of WRITE to Data Valid - 40 - 20 NOTES 1. AgAxs address Specs apply to |O/M, Sq, and S, except AgsAys are undefined during T,Tg of OF cycle, whereas |0/M, Sp, and 5, are stable. 2. Test conditions: tceyvc = 320 ns (SAB 8085AH)/200 ns (SAB 8085AH-2); C_ = 150 pF. 3. For all output timing where C, = 150 pF use the following correction factors: 25 pF = C_ < 150 pF: 0.10 ns/pF 150 pF < C,_ < 300 pF: +0.30 ns/pF 4. Output timings are measured with purely capacitive load. 5. All timings are measured at output votage V, = 0.8V, Vy = 2.0V, and 1.5V with 20 ns rise and fall time on inputs. 6. To calculate timing specifications at other values of tfcyc the following table should be used. 7. Data hold time is guaranteed under all loading conditions. 54SAB 8085AH A.C. Testing Input, Output Waveform 24 20. 20 Test Points 087 08 0.45 A.C. Testing: Input are driven at 2.4V for a Lagic 1" and 0.45V for a Logic 0. Timing Measurements are made at 2.0V for a Logic 1" and 0.8 for a Logic 0. Load Circuit C, = 150 pF C, = includes JIG Capacitance Device under Test | f CL =150 pF 55SAB 8085AH Bus Timing Specification as a icy; Dependent SAB 8085AH SAB 8085AH-2 Symb. | Min. Max. Symb. | Min. Max. tat (1/2) T 45 tar (1/2) T 50 tla (1/2} T ~ 60 fla {1/2} T 50 tu (1/2) T 20 - tu (1/2) T 20 - fick {1/2) T 60 tick (1/2} T 50 tic (1/2) T 30 lic (1/2) T 40 tap _ (5/2 + N) T 225 tap (5/2 + N) T 150 tro (3/2 + N) F 180 tro | (3/2 + N) T 150 Tpac (1/2) T 10 trac (1/2) T 10 ton (1/2) T 40 tea (1/2) T 40 tow {3/2 + N) T 60 tow (3/2 + N)T 70 _ two (1/2) T ~ 60 - two (1/2) T 40 foc (3/2 + N}T 80 lec {3/2 + N)T 70 tor (1/2) T 110 ter (1/2) T 75 tary |- (3/2) T 260 tary - (3/2) T 200 tack (1/2) T 50 tack (1/2}T 60 - tHaBF (1/2) T + 50 tuABE _ (1/2) T + 50 tuage - {1/2} T + 50 tase (1/2) T + 50 tac {2/2} T 50 fac (2/2) T 85 hy (1/2) T 80 ~- th, (1/2) T 60 lb (1/2) T 40 b (1/2) T 30 trv (3/2} T 80 tay (3/2) T 80 tion - (4/2) T 186 tLor - (4/2) T 130 N is equal to the total WAIT states. T = foyc. 56SAB 8085AH Waveforms Read | b Ts | T, CLK fuck bP tea Ag-Ass x Address K fap taou ~~ fae J ADg- AD; x Address }<Y// HHS Data in f ti tin a tare ZLOR b= ter ALE Pe oa fap , cc a ROVINTA \ / te tic tac Write Tt % qT CLK fick Ag Ais Address tow AD,-AD; Address Data out ALE fla tow 57SAB 8085AH Read Operation with Cycle (Typical) Poon | Same Ready Timing Applies to Write Ta | Tait | Ts | yy befor Ag- Ais i Address bo of; -- th RAE ao mH y 5 ADg- AD? y Address HAY Data in ( m tha fare t ~ -_ fipr & i ALE fro me tae fcc ROJINTA N I rmetic- mtipy == a any trys | evi teys_} fRvH, READY \ 7 READY must remain stable during setup and hold times. 58SAB 8085AH Clock Hold \_ SN THoLo Tyoun q, HOLD \ - \ ee ee ~ tips ACR HLDA / . P= tHABE {HABE Bus (Address,Controls) A 59SAB 8085AH Interrupt and Hold st ADp- AD7 CALL-Inst. > oF Lt My x) ~ Bus floating -__ Ih r INTR fit Le rr it =r tHABE tin fins [77 Th T HOLD uy \ / __| fHOH fyps | LL HLDA } tack *) 1O/M is also floating during this time 60SAB 8085AH Ordering Information Component Description Ordering Number 8-Bit Microprocessor SAB 8085AH-P 3 Mbz, 1.3 ps, (plastic) 0 67120-C122 SAB 8085AH-2-P 5 MHz, 0.8 us, (plastic) QO 67120-C124 61Edition 10.90 Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation BalanstraBe 73, D-8000 Miinchen 80. Siemens AG 1990. All Rights Reserved. As far as patents or other rights of third parties are concerned, liability is only assumed for components per se, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. 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