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FEATURES
10 years minimu m data retent io n in the
absence o f exter na l po w er
Dat a is automat ically prot ected during power
loss
Rep laces 512k x 8 vo lat ile static RAM,
EEPROM or Flash memory
Unlim ited write cycles
Low-power CMOS
Read and wr it e access times of 100ns
Lit h iu m energy sour ce is electr ical l y
d iscon nect ed to retain fres hne ss u nt il power is
applied for the fi rst time
Optional industria l t e mperat ur e range of -
40°C to +85°C, designat ed I ND
JEDEC standard 32-pin DIP package
PowerCap Module (PCM) package
– Directly surface-mount able module
– Replaceable snap-o n PowerCap provides
lit hiu m backup bat ter y
– St andardized pinout for all nonvolatile
SRAM products
– Detachment feature on PCM allo ws easy
removal us ing a reg ular scr ewdriver
PIN ASSIGNMENT
PIN DESCRIPTION
A0 - A18 - Address Inputs
DQ0 - DQ7 - Data I n/Dat a Out
CE
- Chip Enable
WE
- Wr ite E nable
OE
- Output Enable
VCC - Po w er (+3.3V)
GND - Ground
NC - No Conne c t
DS1250W
3.3V 4096k Nonvolatile SR AM
19-5648; Rev 12/10
www.maxim-ic.com
13
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3
4
5
6
7
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31
740-Mil Extended
A14
A7
A5
A4
A3
A2
A1
A0
DQ1
DQ0
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ5
DQ6
32
30
29
28
27
26
25
24
23
22
21
19
20
A16
A12
A6
A18
DQ2
GND
15
16
18
17
DQ4
DQ3
WE
NC
A15
A16
NC
VCC
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A17
A14
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34
A18
GND
VBAT
34-Pin PowerCap Module (PCM)
(Uses DS9034PC+ or DS9034PCI+ PowerCap)
DS1250W
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DESCRIPTION
The DS1250W 3.3V 4096k Nonvolatile SRAM is a 4,194,304-bit, fully static, nonvolatile SRAM
organized as 524,288 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and
control circuitry, whi ch constantly monitors VCC for an o ut-of-tolerance cond it io n. Whe n such a co ndition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. DIP-package DS1250W devices can be used in place of exist ing 512k
x 8 stat ic R AMs d irect ly confor ming to the popular byt ewide 32-pin DIP standard. DS1250W devices i n
t he Power Cap Mod ule pack age ar e d ir ect ly sur fac e mo unt able and are nor mally p aired w it h a DS9034 PC
PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write
cycles that can be executed and no additional support circuitry is requir ed for microp r ocessor int er fac ing.
READ MODE
The DS1250W executes a read cycle whenever
WE
(Write Enable) is inactive (high) and
CE
(Chip
Enable) and
OE
(Output Enable) are active (low). The unique address specified by the 19 address inputs
(A0 - A18) de fines which o f the 524,288 bytes o f data is to be accessed. Valid dat a will be av ailable t o t he
e ig ht dat a output drivers w it hin tACC (Access T ime) after the last address input sig na l is stable, pro viding
that
CE
and
OE
(Output Enable) access times are also satisfied. If
OE
and
CE
access times are not
sat isfied, t he n dat a access must be measured fro m t he later -occurring s ig nal (
CE
or
OE
) and t he li mitin g
paramet er is either t CO for
CE
or tOE for
OE
rather than ad dr ess acces s.
WRITE MODE
The DS1250W executes a write cycle whenever the
WE
and
CE
signals are active (low) after address
input s are stable. The lat er -o ccurring falling edge of
CE
or
WE
w ill det ermine t he st art o f the write cycle.
The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must be kept
valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time (tWR)
before another cycle can be init iated. The
OE
control signal should be kept inactive (high) during writ e
c ycles t o avo id bus content io n. H oweve r, if t he o ut p ut drivers are e nab led (
CE
and
OE
ac tive) then
WE
wil l dis ab l e the outputs in tODW fro m it s fal ling edge.
DATA RETENTION MODE
The DS1250W provides full functional capabilit y fo r VCC great er t han 3.0 vo lts a nd wr ite p rot ect s by 2 .8
vo lt s. Dat a is ma inta ined in t he abse nce o f VCC w ithout any add itional support cir cuitr y. The nonvo latile
static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically
write prot ect t hemselves, all inputs become “do n’t car e,” and a ll outputs become high-impedance. A s VCC
falls below approximately 2.5 volts, a power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when VCC rises above approximately 2.5 volts, the power
switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal
RAM op er ation can resu me a fter VCC exceeds 3.0 v olts .
FRESH NESS SEAL
Each DS1250 W device is shipped fro m Maxim with its l it h iu m energy so ur ce disconnected, gu ar ant eeing
fu ll e ne r g y c ap acity. W he n V CC is first app lied at a le ve l great er tha n 3.0 vo lts, t he lit hiu m energy so urce
is enabled for bat tery back-up o per ation.
PACKAGES
The DS1250W is available in two packages: 32-pin DIP and 34-pin PowerCap Module (PCM). The 32-
pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single
package with a JEDEC-standard 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM
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memory and nonvolatile control into a module base along with contacts for connection to the lithium
battery in the DS9034PC PowerCap. The PowerCap Module package design allows a DS1250W PCM
device to be surface mounted without subjecting its lithium backup battery to destructive high-
t emp erat ure r eflo w so lder ing. After a DS1250W modu le base is re flow soldered, a DS 9034PC Po werCap
is snapped o n top of the base to for m a co mplete No nvo latile SRAM mo du le. The DS9034P C is keyed to
prevent improper attachment. DS1250W modu le bases and DS9034PC Po werCaps are ordered separately
and shipped in separate co nt ainers. S ee the DS90 34P C data sheet for furt her info rmation.
DS1250W
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ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground -0.3V to +4.6V
Operating Temper ature Range
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
Stor ag e T emperat ur e
EDIP -40°C to +85°C
PowerCap -55° C to + 125° C
Lead Temperature ( soldering, 10s) +260°C
Soldering Temperatu r e (reflo w, P owerCap) +260°C
Note: EDIP is wave or hand so ldered onl y.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDI TIONS (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Po wer Supply Voltage VCC 3.0 3.3 3.6 V
Log ic 1 VIH 2.2 VCC V
Log ic 0 VIL 0.0 +0.4 V
DC ELECTRICAL CHARACTERISTICS (TA: See Note 10) (VCC = 3.3V ±0.3V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Cu r r ent IIL -1.0 +1.0 µA
I/O Leakage Cu r r ent
CE
≥ VIH ≤ VCC IIO -1.0 +1.0 µA
Output Current @ 2.2V IOH -1.0 mA
Output Current @ 0.4V IOL 2.0 mA
St andby Current
CE
=2.2V ICCS1 50 250 µA
St andby Current
CE
=VCC-0.2V ICCS2 30 150 µA
Operating Curr ent ICCO1 50 mA
Write Protection Voltage VTP 2.8 2.9 3.0 V
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 5 10 pF
I nput/Output Ca pacit ance CI/O 5 10 pF
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AC ELECTRICAL CHARACTERI STICS (TA: See Note 10) (VCC = 3.3V ±0.3V)
PARAMETER SYMBOL DS1250W-100 UNITS NOTES
MIN MAX
Re a d C ycle Time tRC 100 ns
Access Time tACC 100 ns
OE
to O utput Valid tOE 50 ns
CE
to O utput Valid tCO 100 ns
OE
or
CE
to O utput Active tCOE 5 ns 5
Out put High-Z fro m Deselection tOD 35 ns 5
Output Hold fr om Address Change tOH 5 ns
Write Cycle Time tWC 100 ns
Writ e P ulse Widt h tWP 75 ns 3
A ddress Setup Time tAW 0 ns
Writ e Recovery Time tWR1
tWR2
5
20
ns 12
13
Out put High-Z from
WE
tODW 35 ns 5
Output Active from
WE
tOEW 5 ns 5
Da ta Setu p Time tDS 40 ns 4
Da ta Ho ld Time tDH1
tDH2
0
20
ns 12
13
READ CYCLE
SEE NOTE 1
DS1250W
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WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8, AND 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8, AND 12
DS1250W
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POWER-DOWN/POWER-UP CONDITION
POWER-DOWN/POWER-UP TIMING (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC Fail Detect to
CE
and
WE
Inactive tPD 1.5 µs 11
VCC sl ew from VTP to 0V tF 150 µs
VCC slew from 0V to VTP tR 150 µs
VCC Valid to
CE
and
WE
Inactive tPU 2 ms
VCC Valid to E nd o f Wr it e Protection tREC 125 ms
(TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expect ed Data Ret ent io n Time tDR 10 years 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mo de.
NOTES:
1.
WE
is high for a Read Cycle.
2.
OE
= VIH o r V IL. If
OE
= VIH d ur ing write cyc le, the output buf f e rs remain in a high-impedance stat e.
3. tWP is specified as the logical AND of
CE
and
WE
. tWP is measured from the latter of
CE
or
WE
go ing lo w t o t he ear lier o f
CE
or
WE
go ing h ig h.
4. tDH, tDS are measured from the earlier o f
CE
or
WE
go ing h ig h.
5. T hese para met er s ar e sampled with a 5 pF load and ar e not 100% tested.
6. I f the
CE
low transit io n occurs simultaneously with or latt er than the
WE
low transit ion, t he output
buffers re ma in in a high-impedance state during t his period.
7. If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
bu ffe r s r e ma in in h ig h-impedance state during this period.
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8. If
WE
is low or th e
WE
lo w t rans ition oc cur s pr io r t o or s imult a neo usl y wit h t he
CE
lo w t rans ition,
the output buffe rs remain in a h i gh-impedance state during this period.
9. Each DS1250W has a built-in sw it ch t hat d isco nnect s t he lit hiu m so ur ce until VCC is fir st app lied by
the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the
t ime power is first applied by the user.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this ran ge is 0°C t o +70°C. Fo r industrial product s (IND), this range is -40°C to
+85°C.
11. In a power-dow n cond itio n the voltag e on an y pin may not exc eed the voltag e on VCC.
12. tWR1 and tDH1 are measured fr om
WE
go ing h ig h.
13. tWR2 and tDH2 are measured fr om
CE
go ing h ig h.
14. DS1250 modules are reco gnized by Underwrit ers Laborator ies (UL) under file E 99151.
DC TEST CONDITIONS AC TEST CONDITIONS
Output s Open Output Load: 100 pF + 1TTL Gate
Cycle = 200ns for operating current Input P ulse Levels: 0 to 2.7V
All voltag es are r eferenced to ground Timing Measur eme nt Reference Le ve ls
Input: 1.5V
Output : 1.5V
Input pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
PART TEMP RANGE
SUPPLY
TOLERANCE
PIN-PACKAGE
SPEED
GRADE (ns)
DS1250W-100+
0°C to +70°C
3.3V ± 0.3V
32 740 EDIP
100
DS1250WP-100+
0°C to +70°C
3.3V
±
0.3V
34 PowerCap*
100
DS1250W-100IND+
-40°C to +85°C
3.3V
±
0.3V
32 740 EDIP
100
DS1250WP-100IND+
-40°C to +85°C
3.3V
±
0.3V
34 PowerCap*
100
+Denotes a lead(Pb)-free/RoHS-compliant package.
*DS9034PC+ or D S9034PCI+ (PowerCap) required. Must be order ed separat e ly.
PACKAGE INFORMATION
For the latest package outline infor mation a nd land patterns, go to www.maxim-ic.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix
chara c ter , b ut t he drawing p ert ains t o the p ackag e regardless of RoHS status.
PACKAGE TYPE PACK AG E CODE OUTLINE NO. LAND PATTERN NO.
32 EDIP MDT32+6 —
21-0245
34 PCAP PC2+5 —
21-0246
DS1250W
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REVISION HIST ORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
121907
Added the Package Information table; re move d the DIP module
package drawing and dimension t able
7, 8
12/10
Updated t he storag e information, solder ing temp erat u r e, and lead
t emperat ur e info rmation in t he Absolute Maximum Ratings
section; removed the -150 MIN/MAX information from the AC
Electrical Characteristics t able; updat ed the Ordering
Information t able (r emo ved -150 parts and leaded -100 parts);
updated th e Package Information table
1, 4, 5, 8