DS1250W
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DESCRIPTION
The DS1250W 3.3V 4096k Nonvolatile SRAM is a 4,194,304-bit, fully static, nonvolatile SRAM
organized as 524,288 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and
control circuitry, whi ch constantly monitors VCC for an o ut-of-tolerance cond it io n. Whe n such a co ndition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. DIP-package DS1250W devices can be used in place of exist ing 512k
x 8 stat ic R AMs d irect ly confor ming to the popular byt ewide 32-pin DIP standard. DS1250W devices i n
t he Power Cap Mod ule pack age ar e d ir ect ly sur fac e mo unt able and are nor mally p aired w it h a DS9034 PC
PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write
cycles that can be executed and no additional support circuitry is requir ed for microp r ocessor int er fac ing.
READ MODE
The DS1250W executes a read cycle whenever
(Write Enable) is inactive (high) and
(Chip
Enable) and
(Output Enable) are active (low). The unique address specified by the 19 address inputs
(A0 - A18) de fines which o f the 524,288 bytes o f data is to be accessed. Valid dat a will be av ailable t o t he
e ig ht dat a output drivers w it hin tACC (Access T ime) after the last address input sig na l is stable, pro viding
that
and
(Output Enable) access times are also satisfied. If
and
access times are not
sat isfied, t he n dat a access must be measured fro m t he later -occurring s ig nal (
or
) and t he li mitin g
paramet er is either t CO for
or tOE for
rather than ad dr ess acces s.
WRITE MODE
The DS1250W executes a write cycle whenever the
and
signals are active (low) after address
input s are stable. The lat er -o ccurring falling edge of
or
w ill det ermine t he st art o f the write cycle.
The write cycle is terminated by the earlier rising edge of
or
. All address inputs must be kept
valid throughout the write cycle.
must return to the high state for a minimum recovery time (tWR)
before another cycle can be init iated. The
control signal should be kept inactive (high) during writ e
c ycles t o avo id bus content io n. H oweve r, if t he o ut p ut drivers are e nab led (
and
ac tive) then
wil l dis ab l e the outputs in tODW fro m it s fal ling edge.
DATA RETENTION MODE
The DS1250W provides full functional capabilit y fo r VCC great er t han 3.0 vo lts a nd wr ite p rot ect s by 2 .8
vo lt s. Dat a is ma inta ined in t he abse nce o f VCC w ithout any add itional support cir cuitr y. The nonvo latile
static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically
write prot ect t hemselves, all inputs become “do n’t car e,” and a ll outputs become high-impedance. A s VCC
falls below approximately 2.5 volts, a power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when VCC rises above approximately 2.5 volts, the power
switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal
RAM op er ation can resu me a fter VCC exceeds 3.0 v olts .
FRESH NESS SEAL
Each DS1250 W device is shipped fro m Maxim with its l it h iu m energy so ur ce disconnected, gu ar ant eeing
fu ll e ne r g y c ap acity. W he n V CC is first app lied at a le ve l great er tha n 3.0 vo lts, t he lit hiu m energy so urce
is enabled for bat tery back-up o per ation.
PACKAGES
The DS1250W is available in two packages: 32-pin DIP and 34-pin PowerCap Module (PCM). The 32-
pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single
package with a JEDEC-standard 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM