®
August 2003 1/21
STV7619DU
Scan Driver for Plasma Display Panels
Main Features
■64-output Scan Driver
■120 V Absolute Maximum Supply
■5 V Logic Supply
■Optional 12 V Supply for driving the output
stage
■150mA/1A Source/Sink Output
■1 A Source/Sink Output Diode
■64-bit Bi-directional Shift Register (8 MHz)
■BCD Technology
■100-pin TQFP package with integrated
heatsink
Description
Th e ST V7619 is a scan drive r f or plasm a dis play
panels (PDP) implemented in ST’s proprietary BCD
(Bi-polar CMOS DMOS) technology. Using a 64-bit
cascadable 8 MHz shift register, it drives 64 high-
current and high-voltage outputs.
By co nnec t ing se v eral STV7619 devic es in se ries ,
any v ert ic al pix el def inition c an be perf ormed. Th e
ST V7619 is su pplied w it h s eparate 110V power
out put a nd 5 V logic su pplies . T he logic se c tio n of
the out put stage is s uppli ed eith er ex te rnally by a
5V or 12V su pply or int erna lly by a c harge pump
cell. The choice of the supply value is related to the
PDP size. All command inputs are CMOS
compatible.
Th e ST V7619 pack age is a 100-pin TQF P with
inte grat ed heatsink loc ate d on th e botto m
(ST V7619D ) of the pack age. It is also av ailable
without heat s ink (STV7619).
TQFP100 (14 x 14 x 1.4 mm Slug-down)
(Thin Plastic Quad Flat Pack)
ORDER CODE: STV7619D
TQ FP100 (14 x 14 x 1.4 mm)
(Thin Plastic Quad Flat Pack )
ORDER CODE: STV7619
2/21
STV7619DU
Table of Contents
Chapter 1 Pin Allocation and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Pinout Diagrams ...............................................................................................................3
Chapter 2 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Chapter 3 Application Hints: Charge Pump Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.1 Power Supply ............. ........... ........... ........ ........... ........... ....... ........... ........... ........... ...... ........9
3.2 Sink Current Characteristics ..............................................................................................10
3.3 Recommendations .............................................................................................................10
Chapter 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1 Absolute Maximum Ratings ..............................................................................................11
4.2 Thermal Data ....................................................................................................................12
4.3 Supply Characteristics .......................................................................................................12
4.4 Power Output Characteristics ...........................................................................................13
4.5 SOUT Characteristics .......................................................................................................14
4.6 Input (CLK, STB, BLK, POC, SIN, CLR, F/R and ENABLE) Characteristics ....................14
4.7 AC Timin g Requirement s ... ....... ....... ........... ........... ........... ........ ........... ........... ........... ....... .14
4.8 AC Timin g Characteri sti cs .... ........ ........... ....... ........... ........... ........... ....... ........... ........... .....15
Chapter 5 Input/Output Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Chapter 6 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Chapter 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Pin Allocation and Descriptions STV7619DU
3/21
1 Pin Allocation and Descriptions
1.1 Pinout Diagrams
Figure 1: STV7 619 and STV76 19D (TQF P100)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
OUT61
OUT60
OUT59
OUT58
OUT57
OUT56
OUT55
OUT54
OUT53
OUT52
OUT51
OUT50
OUT49
OUT48
OUT47
OUT46
OUT45
OUT44
OUT43
OUT42
OUT41
OUT40
OUT39
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
OUT17
OUT18
OUT19
OUT20
OUT21
OUT22
OUT23
OUT24
OUT25
OUT26
OUT27
OUT28
OUT32
OUT64
NC*
SOUT
CLK
STB
BLK
POC
CLR
NC*
OUT2
OUT3
TQFP100
(Top View)
OUT1
OUT63
OUT62
OUT38
OUT37
OUT36
OUT33
OUT34
OUT35
OUT31
OUT30
OUT29
VPP
VSSP
VSSP
NC*
NC*
VSSLOG
VSSLOG
VSSSUB
VPP
VPP
NC*
VSSP
VSSP
VPP
VPP
VSSP
VSSP
VDD
SIN
VCC
F/R
VSSLOG
VSSP
VSSP
*NC: Not Connected
ENABLE
VSSSUB
VPP
NC*
4/21
STV7619DU Pin Allocation and Descriptions
Table 1: Supply Pins
Pin No. Pin Name Pin Description
88 VCC 5V Logic Supply
84 VDD 5/12V Internal/External Logic Supply
33 VPP High Voltage Supply for Power Outputs
34 VPP High Voltage Supply for Power Outputs
42 VPP High Voltage Supply for Power Outputs
43 VPP High Voltage Supply for Power Outputs
79 VPP High Voltage Supply for Power Outputs
97 VPP High Voltage Supply for Power Outputs
36 VSSLOG Logic Ground
40 VSSLOG Logic Ground
83 VSSLOG Logic Ground
30 VS SP Ground for Power Output s
31 VS SP Ground for Power Output s
45 VS SP Ground for Power Output s
46 VS SP Ground for Power Output s
81 VS SP Ground for Power Output s
82 VS SP Ground for Power Output s
94 VS SP Ground for Power Output s
95 VS SP Ground for Power Output s
37 VSSSUB Substrate Ground
39 VSSSUB Substrate Ground
Table 2: Shift Register and Input Pins
Pin No. Pin Name Pin Description
38 ENABLE Enable Charge Pump mode
85 SOUT Shif t Register Dat a Output
86 CLK Clock for Shift Register Data
87 STB Latch for Shift Register Data (Str obe Input )
89 BLK Blanking Control for Power Outputs
90 PO C Polarity Output Control
91 SIN Shift Regist er Dat a Input
92 CLR Clear for Shift Regi ster Data
93 F/R Foward/Reser ve m odes for selecting Shift Regi ster
Pin Allocation and Descriptions STV7619DU
5/21
Table 3: Power Output Pins
Pin No. Pin Name Pin Description Pin No. Pin Name Pin Description
98 OUT1 Power Output 1 47 OUT33 Power Output 33
99 OUT2 Power Output 2 48 OUT34 Power Output 34
100 OUT3 Power Output 3 49 OUT35 Power Outp ut 35
1 OUT4 Power Output 4 50 OUT36 Power Output 36
2 OUT5 Power Output 5 51 OUT37 Power Output 37
3 OUT6 Power Output 6 52 OUT38 Power Output 38
4 OUT7 Power Output 7 53 OUT39 Power Output 39
5 OUT8 Power Output 8 54 OUT40 Power Output 40
6 OUT9 Power Output 9 55 OUT41 Power Output 41
7 OUT10 Power Output 10 56 OUT42 Power Output 42
8 OUT11 Power Output 11 57 OUT43 Po wer Output 43
9 OUT12 Power Output 12 58 OUT44 Power Output 44
10 OUT13 Power Output 13 59 OUT45 Power Output 45
11 OUT 14 Power Output 14 60 OUT46 Power Output 46
12 OUT15 Power Output 15 61 OUT47 Power Output 47
13 OUT16 Power Output 16 62 OUT48 Power Output 48
14 OUT17 Power Output 17 63 OUT49 Power Output 49
15 OUT18 Power Output 18 64 OUT50 Power Output 50
16 OUT19 Power Output 19 65 OUT51 Power Output 51
17 OUT20 Power Output 20 66 OUT52 Power Output 52
18 OUT21 Power Output 21 67 OUT53 Power Output 53
19 OUT22 Power Output 22 68 OUT54 Power Output 54
20 OUT23 Power Output 23 69 OUT55 Power Output 55
21 OUT24 Power Output 24 70 OUT56 Power Output 56
22 OUT25 Power Output 25 71 OUT57 Power Output 57
23 OUT26 Power Output 26 72 OUT58 Power Output 58
24 OUT27 Power Output 27 73 OUT59 Power Output 59
25 OUT28 Power Output 28 74 OUT60 Power Output 60
26 OUT29 Power Output 29 75 OUT61 Power Output 61
27 OUT30 Power Output 30 76 OUT62 Power Output 62
28 OUT31 Power Output 31 77 OUT63 Power Output 63
29 OUT32 Power Output 32 78 OUT64 Power Output 64
6/21
STV7619DU Pin Allocation and Descriptions
Table 4: Miscellaneo us Pins
Pin No. Pin Name Pin Description
32 NC Not connected
35 NC Not connected
41 NC Not connected
44 NC Not connected
80 NC Not connected
96 NC Not connected
Circuit Description STV7619DU
7/21
2 Circuit Description
Th e ST V7619 includes all th e neces s ary lo gic and pow er circ uit s to driv e th e row s of elec t rodes of
a plasma displ ay panel (PDP). Da ta i s sh if ted a t e ach l ow t o hi gh tr ansi ti o n of th e (CLK) sh i ft cl o ck.
After 64 shifts, the first bit presented at the serial input (SIN) is available at the serial output (SOUT).
Th is out put is us ed t o c as c ade sev eral driv ers to perfo rm any ve rt ic al res olut ion (Table 5). CLK,
ST B, SI N and SOU T inputs are Sc hmitt trigger inpu t s.
In reverse mode (F/R = lo w ), dat a is input on the SOU T pin and ou tp ut on the SI N pin.
Th e c lear s ignal (C LR) s et s th e s hif t regis t er dat a to low.
Shift register outputs (P1, ... P64) are transferred from the shift register to the latch stage when the
lat c h input (ST B) is at low level.
All the data is kept memorized in the latch stage when the strobe input (STB) is pulled high.
Figure 2: Block Diagram
Table 5: Shift Register Truth Table
F/R CLK SIN SOUT Comments
H Rise In Out Forward Shift
H L or H In Out Steady
L Rise Out In Reverse Shift
L L or H Out In Steady
P1
Q64
S1
VCC
SIN (S OUT)
POC
S64
64
P
Q63
STV7619
F/R
CLR
Q2Q1
BLK
SOUT (SIN)
VSSSUB
VSSP
VSSLOG
VPP
VDD
ENABLE
Voltage
Generator Vcc
64-bi t Shift R egi ste r
Latch
VPP
VSSP
OUT64
OUT1
VPP
VSSP
STB
CLK
8/21
STV7619DU Circuit Description
Driver outputs can be simultaneously polarized at high or low level depending on the biasing of the
POC input signal (Table 6).
Th e ST V7619 integrat es a ch arge p um p ce ll to m anage th e c urren t driv e c apabilit ies of the out put
sin k tra ns is t or, as expl ained in Table 7. M ore details are giv en in Chapter 3.
Table 6: Output State Configuration
STB CLR POC BLK Comments
* * L * All at low level
* * H H All at high level
L H H L All at high level
L L H L Inverted copy of i nput data
H * H L Inverted copy of l atched dat a
Tabl e 7: Voltage Genera tor Tab le
ENA B LE VD D Outp ut Perf ormanc es
LExternal Power Supply (VDD = 5V) Minimum Sink Current mode
External Power Supply (VDD = 12V) Maximum Sink Current mode
HInternal Power Supply (Charge Pump mode)
VDD connected to an ext ernal capacitance
(CVDD = 100nF (20V)) Medium Sink Current mode
Application Hints: Charge Pump Function STV7619DU
9/21
3 Application Hints: Charge Pump Function
3.1 Power Supp ly
Th e ST V7619 is des igned to driv e pan els u p t o 42” w it h low v olta ge logi c su pplies (pins VC C and
VD D ). In th is ca s e, pin VD D m us t be co nnect ed to p in VC C . The dri vi ng of la rge panels (50”, 6 0”)
requires a 100 nF capacitor connected between pin VDD and the ground. An internal charge pump
prov ides a higher driv ing volta ge for the low stage. If requeste d, higher perf orm ances are obta ined
wh en a 12V power s upply is direct ly c onnec t ed to pin VD D .
Th e logic sup ply ma nagement of the out put sta ge m ainly depends on the wri te cur rent value of the
plas m a ce lls . T he w rite cu rrent is r elated t o t he size of th e PD P. The f ollow ing f igures illus t rat e t he
different possibilities to supply the STV7619 according to the current drive performances requested
by th e plas m a panel.
Figure 3 : External Pow er Supply (Small-size PDP)
Figure 4: External Power Supply (Large-size PDP)
Fi gure 5: Internal Pow er Supp ly, Charg e Pump mod e (Med ium - or Large-size PD P)
STV7619
110V
ENABLE
VPP
VCC
VDD
5V
110V
V
PP
V
CC
V
DD
5V
12V
STV7619
ENABLE
STV7619
110V
ENABLE
VPP
VCC
VDD
5V
100nF
(16V)
10/21
STV7619DU Application Hints: Charge Pump Function
3.2 Sink Current Characteristics
3.3 Recommendations
Th e Sus ta in cu rrent must not be su nk in t he pow er ou t put s to VPP w hen t he power s upply is
applied. VSSSUB and VSSLO G m us t be co nnec t ed clos e t o t he logic al ref eren c e ground of t he
logic cont rol signal buffers .
Figure 6: Typical Sink Stag e Chara cteri stics (Peak current and TAMB = 25 °C)
0
200
400
600
800
1000
1200
1400
0 5 10 15 20 25 30
Vpoutl(V)
Idoutl(mA)
Vgs=5V
Vgs=chpum p
Vgs=12V
Electrical Characteristics STV7619DU
11/21
4 Elec tri cal Char acte ristic s
4.1 Absol ute Max imum Ratings
No te : 1. All pins in relat ion to V
CC
= -1500V
2. Throu gh one power ou t put .
3. Throu gh one diode
4. Through all power outputs (see test diagram): with power dissipation lower than or equal to Ptot and
Ju nc t ion te m perat ure lower t han or equal t o T
jmax
and
V
PP =
V
SSP.
5. Th es e param et ers are meas ured during ST’s in te rnal qualification wh ic h incl udes te m pera tu re
characterisation on standard batches and on corners batches of the process. These parameters are
not tested on the parts.
6. For V
DD
= 9 V, I
POUT
= 1.0 A, fo r V
DD
= 5 V, I
POUT
= 0.5 A
Symbol Parameter Value Units
VCC Logic Suppl y -0.3 , + 7 V
VDD Logic suppl y of power part -0.3, +14 V
OUTi Output Pins -0.3, +120 V
VIN Logic Inp u t Volta ge -0.3, VCC +0.3 V
VOUT L ogic Output Voltage -0 .3 , V CC + 0.3 V
VPOUT Driver Output Voltage (scanning mode) -0.3, +120 V
VESD ES D Susceptibil ity (Human Body m odel: 100 pF capacitor di scharged through
1.5 kΩ serial resistor) (See Note 1)±2200 V
IPOUT Driver Output Current (See Note 2, Note 5 and Note 6) -150 mA/+1.2 A
IDOUT1 Diode Output Current (See Note 3 and Note 5)±1A
I
DOUT2 Diode Output Current (See Note 4 and Note 5) ±700 mA
TJMAX Juncti on Temperature +150 °C
TOPER Operating Temperature -20, +85 °C
TSTG Storage Temperature -20, +150 °C
12/21
STV7619DU Electrical Characteristics
4.2 The rmal Data
No te : 1. Fo r T QF P100 pac k aging with slu g s oldered on pr int ed c irc uit board.
2. TQFP s oldered on 4-layer print ed cir cu it board .
3. For TQF P100 pac k aging with slu g not so ldered on printe d c irc uit board.
4.3 Supply Chara cteristics
(VSSP = 0 V, VSSLOG = 0 V, VSSSUB = 0 V, TAMB = 25 °C and fCLK = 8 MHz, unless otherwise
specified)
Symbol Parameter Value Units
TJOPER Maximum Operating Junction 125 °C
RthJA Junct ion-am bient Therm al Resistance (See Note 1)20°C/W
R
thJA Junct ion-am bient Therm al Resistance (See Note 2)40°C/W
R
thJA Junct ion-am bient Therm al Resistance (See Note 3)29°C/W
Sym b o l Para m et e r Test Co n di t io ns Min. Ty p. Ma x. Uni ts
VCC Logic Suppl y Voltage 4.5 5 5.5 V
VDD Logic Supply Voltage for Output Stage VCC 13 V
VPP Power Output Supply Voltage 20 110 V
ICCH Logic Supply Current
with VDD=5 or 12 V
(ENABLE=L)
wit h pump charge capac itor
(ENABLE=H) 0.3
100
2
µA
mA
ICCL Dynami c Logic Supply Current fCLK = 8 MHz TBD mA
IPPH Power Output Supply Current (steady outputs) 100 µA
Electrical Characteristics STV7619DU
13/21
4.4 Power Output Charac teristics
Note:1. Peak current - Pulse mode 720 Hz - 0.2%. Duty cycle.
2. C om pat ible w ith power dis si pat ion and T
JOPER
≤
125°C .
3. See
Figure 8: Test Configuration on page 17
.
Sym b o l Para m et e r Test Co n di t io ns Min. Ty p. Ma x. Uni ts
VPOUTH Power Output High Level
(Vol tage dro p versus VPP)IPOUTH = - 60 mA TBD 4.2 V
VPOUTL Power Output Low Level voltage drop
IPOUTL= +400 mA
VDD=12V (ENABLE = L) 2.5 TBD V
VDD=5V (ENABLE = L) 3.4 TBD V
pump charge capacitor on
VDD (ENABLE = H) 2.8 TBD V
IPOULP
Power Output Low Level Peak current
VPOUTL=12 V (See Note 1)
(Pulse ≤ 500ns)
VDD=12 V (ENABLE = L) TBD 1100 mA
VDD= 5V (ENABLE= L) TBD 530 mA
pump charge capacitor on
VDD (ENABLE = H) TBD 1000 mA
VDOUTH Output Diode High Level (See Note 2 and Note 3)IDOUTH = +400 mA 1.8 3.0 V
VDOUTL O utput Diode Low Level (See Note 2 and Note 3)IDOUTL = - 400 mA -1.25 -3.00 V
14/21
STV7619DU Electrical Characteristics
4.5 SOUT Characteristics
4.6 I nput (CL K, ST B, BLK, POC, SIN, CLR, F/R and ENABLE) Characteristics
4.7 AC Timing Require ments
VCC = 4.5 V to 5.5 V, TAMB = -20 to +85°C, max. leading/trailing edge for input signals (tr, tf) = 10 ns
Sym b o l Para m et e r Test Co n di t io ns Min. Ty p. Ma x. Uni ts
VOH Logic Output High Level IOH = -1 mA 4.2 4.6 V
VOL Logic Output Low Level IOL = +1 mA 0.1 0.4 V
Sym b o l Para m et e r Test Co n di t io ns Min. Ty p. Ma x. Uni ts
VIH Input High Level 0.8 VCC V
VIL Input Low Level 0.2VCC V
IIH High Level Input Current VIH = VCC ±10 µA
IIL Low Level Input Current for pins CLK, SIN, STB,
CLR, BLK and POC VIL = 0 V ±10 µA
IIL Low Level Input Current for ENABLE pin VIL = 0 V -25 µA
Symbol Parameter Min. Typ. Max. Units
tWHCLK Duration of clock (CLK) pulse at high level 40 ns
tWLCLK Durat ion of clock (CLK) pulse at low level 40 ns
tSDAT Set-up Time of data input before clock (low to high) transition 10 ns
tHDAT Hold Time of data input after clock (low to high) transition 20 ns
tDSTB Minimum Delay to latch STB after clo ck (l ow to high) transiti on 25 ns
tSSTB Set-up T ime STB before clock (low to high) transition 10 ns
tSTB Latch STB Low Level Pulse Duration 20 ns
tBLK Blanking (BLK) Pulse Duration 100 ns
Electrical Characteristics STV7619DU
15/21
4.8 AC Timing Characteristics
No te : 1. One out put am ong 64, loading c apac it or C
OUT
= 200 pF, ot her out puts at low or high lev el.
Symbol Parameter Min. Typ. Max. Units
tCLK Data Clock Period 125
tRDAT Logical Data Output Rise Time 25
tFDAT Logi cal Data Output Fall Ti me 1 5
tPHL1 Delay of logic data output (high to low transition) after clock (CLK) transition
(CL=10pF) 45
tPLH1 Delay of logic data output (low to high transition) after clock (CLK) transition
( C L =10 pF ) 50 ns
tPHL2 Delay of power output change (high to low transition) after clock (CLK) t ransi ti on TBD 180 ns
tPLH2 Delay of power output change (low to hi gh tr ansition) after c lock (C LK) t ransi ti on TBD 180 ns
tPHL3 Delay of power output cha nge (high t o low trans iti on) afte r Latch (STB) t ransition TBD 165 ns
tPLH3 Delay of power output cha nge (low to hi gh trans iti on) afte r Latch (STB) t ransi ti on TBD 165 ns
tPHL4 Delay of power output change (high to low transition) to POC trans it ion 105 160 ns
tPLH4 Delay of power output change (low to hi gh trans ition) t o POC transition 100 160 ns
tROUT Power Output Rise Time (See Note 1) 100 ns
tFOUT Power Output Fall Time (See Note 1)30ns
16/21
STV7619DU Electrical Characteristics
Figure 7: AC Charac teristics Waveform
POC
OUTn
tBLK
tPHL4
tPLH4
50% 50%
10%
90%
"1"
"0"
"1"
"0"
CLK
SIN
SOUT
tWLCLK
tCLK
tWHCLK
tSDAT tHDAT
tPHL1
tFDAT
tRDAT
50% 50% 50%
90%
90%
10%
10% 50%
50% 50%
"1"
"0"
"1"
"0"
"1"
"0"
tPLH1
tROUT tFOUT
90%
10%
STB
OUTn
STB
tDSTB
tPHL3
tPLH3
tPHL2
tPLH2
90% 10% 90% 10%
"1"
"0"
"1"
"0"
50%
tSSTB
50%
Electrical Characteristics STV7619DU
17/21
Figure 8: Test Configuration
VDOUTH IDOUTH
VSSP
VDOUTL IDOUTL
VSSP
VPP=VSSP
VPP=VSSP
Out put sinking current as positive value, sourcing current as negative value.
18/21
STV7619DU Input/Output Schematic Diagrams
5 Input/Output Schematic Diagrams
Figure 9: ENABLE Input
Fi gure 10 : F/ R , CLR, CLK, STB, BLK and POC I nputs
VSSLOG
VCC
VSSLOG
ENABLE
VCC
VCC VCC
VSSLOG
VSSLOG
BLK, POC, F/R
CLK, STB, CLR
Fi gure 11: S I N , S OUT I npu t
Figu re 1 2: Po we r Ou t pu ts
VCC VCC
VCC
VSSLOG
VSSLOG
VSSLOG
SIN, SOUT
OUT1 to OUT64
VPP
VSSP
Package Mechanical Data STV7619DU
19/21
6 Package Mechanical Data
Figure 13: TQFP 100 P ackag e
Dimensions Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
B 0.17 0.22 0.27 0.007 0.009 0.011
C 0.09 0.20 0.004 0.008
D 16.00 0.630
D1 14.00 0.551
D3 12.00 0.472
e 0.50 0.20
E 16.00 0.630
E1 14.00 0.551
E3 12.00 0.472
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
K0° (Min.), 7° (Max.)
Slug Dimension For L/Frame Pad Size 10.00 x 10.00 mm
H9.85 0.388
S 8.80 0.346
S1 8.80 0.346
A
A2
A1
ccc
Seating
Plane
C
C
C
2526
50
51
76
100
D3
D1
D
e
1
B
S1
S
H
TQFP100M
Gage Plane
0.25mm
.010 inch
Pin 1
Identification
K
L
L1
E3 E1 E
75
20/21
STV7619 DU Revisio n Histo ry
7 Revision History
Table 8: Su mm ary of Modifications
Version Date Description
Target Specification
1.0 Apri l 2001
First version issued
1.1 Apri l 2001
Corrections from the design
1.2 May 200 1
Corr ection s in Table 1 and text added in Circuit description
1.3 May 200 1
Inversion of BLK and POC pinsin block diagram and Table 1.
Product Preview
2.0 September
2001
Pin conn ect ions - pins 30 to 50 corrected, Pin assignem en ts: com pleted, Block diagr am : voltage
gener ator added , Circuit description: text modified, Application hints chapter adde d, Electrical
char acteristics: few precisio ns, Input/outp ut schem atics : corrections
2.1 October
2001
Pin conn ect ions - pins 38 added to pin description, Electrica l characteristics : I
IH
and I
IL,
typic al
valu e is ±10, AC timing charac teristics: t
PHL4
and t
PLH4
: (BLK) replaced with (POC), Figure 5: AC
char acteristics w avef orm: S TB and OU Tn wav eforms rep laced, BLK renam ed with PO C .
2.2 November
2001
Page 10 - C
VDD
value replaced with 100 nF (1 previously), Page 11 - figure 3 - C
VDD
value
replace d with 100 nF, Page 12 - Figure 4 replaced. Sentenc e mod ified in subsection 7.3
recommendations: the logical reference ground “
of the application”
replaced with “
of t he logi c
cont rol signal buffers
”. Page 13 - absolute maxim um ratings - Ioutput value replaced w ith -150mA/
+1.2A. N ote removed. Page 14- Electrical characteristics: values replaced. Page 15 - AC timing
char acters itics: values replac ed
2.3 January
2002
Elec trical charact eristics: First se ntence: Vpp and Vdd remov ed, in the tab le: Vp p m ove d aft er V dd.
Preliminary Data
2.4 24 July
2002
Refor m atted datashe et. Deletion of STV7 619U (Slug-up) device and related informat ion.
Mod ification of values in
Note 6 on page 11
. Ad dit ion of
Note3onpage12
. Update of typical
v a lues in
Secti on 4
.
2.5 13 Ja nuary
2003
Ad dition of V
ESD
information in
Section 4.1: Absolute Maximum Rating s on page 11
.
Datasheet
3.0 August
2003
Published on internet.
STV7619DU
21/21
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