Rev.2.00, Jul.16.2004, page 1 of 9
HD74AC283/HD74ACT283
4-bit Binary Full Adder with Fast Carry REJ03D0267–0200Z
(Previous ADE-205-3 88 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74AC283/HD74ACT283 high-speed 4-bit binary full adder with internal carry lookahead accepts two 4-bit
binary works (A0 – A3, B0 – B3) and a Carry input (C0). It generates the binary Sum output s (S0 – S3) and the Carry
output (C4) from the most significant bit. The HD74AC283/HD74ACT283 will operate with either active High or
acti ve Low operands (positive or negative logic).
Features
• Outputs Source/Sink 24 mA
• HD74ACT283 has TTL-Cmpatible Inputs
• Ord ering Information: Ex. HD74AC283
Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity)
HD74AC283AP DIP-16 pin DP-16E, -16FV P —
HD74AC283AFPEL SOP-16 pin (JEITA) FP-16DAV FP EL (2,000 pcs/reel)
HD74AC283ARPEL SOP-16 pin (JEDEC) FP-16DNV RP EL (2,500 pcs/reel)
HD74AC283TELL TSSOP-16 pin TTP-16DAV T ELL(2,000 pcs/reel)
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Pin Arrangement
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S
1
B
1
A
1
S
0
A
0
C
0
B
0
GND
V
CC
B
2
A
2
S
2
A
3
B
3
S
3
C
4
(Top view)
HD74AC283/HD74ACT283
Rev.2.00, Jul.16.2004, page 2 of 9
Logic Symbol
C0C4
A0
S0S1S2S3
A1A2A3
B1B2B3
B0
Pin Names
A0 – A3A Operand Inputs
B0 – B3B Operand Inputs
C0Carry Input
S0 – S3Sum Outp uts
C4Carr y Output
Functional Description
The HD74AC283/HD74ACT283 adds two 4-bit binary words (A plus B) plus the incoming Carry (C0). The binary sum
appears on the Sum (S0 – S3) and outgoing carry (C4) outputs. The binary weight of the various inputs and outputs is
indicated by the subscript numbers, representing powers of two.
20 (A0 + B0 + C0) + 21 (A1 + B1) + 22 (A2 + B2) + 23 (A3 + B3) = S0 + 2S1 + 4S2 + 8S3 + 16C4
Where (+) = plus
Interchanging inputs of eq ual weight d oes not affect the o peration. Thus C0, A0, B0 can be arbitrarily assigned to pins 5,
6 and 7 for DIPS. Due to the symmetry of the binary add function, the HD74AC283/HD74ACT283 can be used either
with all inputs and outputs active Hi gh (positive logic) or with all inputs and outputs active Low (negative logic). See
Figure a. Note that if C0 is not used it must be tied Low for active High logic or tied High for active Low logic.
Due to pin limitations, the intermediate carries of the HD74AC283/HD74ACT283 are not brought out for use a s inputs
or outputs. However, other means can be used to effectively insert a carry into, or bring a carry out from, an
intermediate stage. Figure b shows how to make a 3-bit adder. Tying the operand inputs of the fourth adder (A3, B3)
Lo w makes S3 dependent only on, and equal to, the carry from the third adder. Using somewhat the same principle
Figure c shows a way of dividing the HD74AC283/HD74ACT283 into a 2-bit and a 1-bit adder. The third stage adder
(A2, B2, S2) is used merely as a means of getting a carry (C10) signal into the fourth stage (via A2 and B2) and bringing
out the carry from the second stage on S2. Note that as long as A2 and B2 are the same, whether High or Low, they do
not influence S 2. Similarly, when A2 and B2 are the same the carry into the third stage does not influence the carry out
of the third stage. Figure d shows a method of implementing a 5-input encoder, where the inputs are equally weighted.
The outputs S0, S1 and S2 present a binary number equal to the number of inputs I1 – I5 that are true. Figure e shows one
method of implementing a 5-input majority gate. When three or more of the inputs I1 – I5 are true, the output M5 is true.
Fig. a Active HIGH varsus Active LOW Interpretation
C0A0A1A2A3B0B1B2B3S0S1S2S3C4
Logic levels L L H L H H L L H H H L L H
Active HIGH00101100111001
Active LOW11010011000110
Active HIGH: 0 + 10 + 9 = 3 + 16
Active LOW: 1 + 5 + 6 = 12 + 0
HD74AC283/HD74ACT283
Rev.2.00, Jul.16.2004, page 3 of 9
C0
C3
L
C4
A0
S0S1S2S3
A1A2A3
B1B2B3
B0
Fig. b 3-bit Adder
C0C0C4C11
A0
S0S1S2S3
S0S1C2S10
A1A2A3
B1B2
C10
B3
B0
A0A1A10
B1B10
B0
Fig. c 2-bit and 1-bit adders
C
0
C
4
A
0
I
1
I
2
LI
4
I
5
I
3
S
0
2
0
2
1
2
2
S
1
S
2
S
3
A
1
A
2
A
3
B
1
B
2
B
3
B
0
Fig. d 5-Input Encoder
HD74AC283/HD74ACT283
Rev.2.00, Jul.16.2004, page 4 of 9
C0C4
A0
I1I2I4I5
I3
S0S1S2
M5
S3
A1A2A3B1B2B3B0
Fig. e 5-Input Majority Gate
Logic Diagram
C0
S0S1S2S3C4
A0A1B0B1A2B2A3B3
Please note that this diagram is provided only for the understanding of logic operations and shoudl not be
used to estimate propagation delays.
HD74AC283/HD74ACT283
Rev.2.00, Jul.16.2004, page 5 of 9
Absolute Maximum Ratings
Item Symbol Ratings Unit Condition
Supply voltage VCC –0.5 to 7 V
–20 mA VI = –0.5VDC input diode current IIK 20 mA VI = Vcc+0.5V
DC input voltage VI–0.5 to Vcc+0.5 V
–50 mA VO = –0.5VDC output diode current IOK 50 mA VO = Vcc+0.5V
DC output voltage VO–0.5 to Vcc+0.5 V
DC output source or sink current IO±50 mA
DC VCC or ground current per output pin ICC, IGND ±50 mA
Storage temperature Tstg –65 to +150 °C
Recommended Operating Conditions: HD74AC283
Item Symbol Ratings Unit Condition
Supply voltage VCC 2 to 6 V
Input and output voltage VI, VO0 to VCC V
Operating temperature Ta –40 to +85 °CVCC = 3.0V
VCC = 4.5 V
Input rise and fall time
(except Schmitt inputs)
VIN 30% to 70% VCC
tr, tf 8 ns/V
VCC = 5.5 V
DC Characteristics: HD74AC283
Ta = 25°
°°
°C Ta = –40 to
+85°
°°
°C
Item Sym-
bol Vcc
(V) min. typ. max. min. max.
Unit Condition
3.0 2.1 1.5 — 2.1 —
4.5 3.15 2.25 — 3.15 —
VIH
5.5 3.85 2.75 — 3.85 —
VOUT = 0.1 V or VCC –0.1 V
3.0 — 1.50 0.9 — 0.9
4.5 — 2.25 1.35 — 1.35
Input Voltage
VIL
5.5 — 2.75 1.65 — 1.65
V
VOUT = 0.1 V or VCC –0.1 V
3.0 2.9 2.99 — 2.9 —
4.5 4.4 4.49 — 4.4 —
5.5 5.4 5.49 — 5.4 —
VIN = VIL or VIH
IOUT = –50 µA
3.0 2.58 — — 2.48 — IOH = –12 mA
4.5 3.94 — — 3.80 — IOH = –24 mA
VOH
5.5 4.94 — — 4.80 —
VIN = VIL or VIH
IOH = –24 mA
3.0 — 0.002 0.1 — 0.1
4.5 — 0.001 0.1 — 0.1
5.5 — 0.001 0.1 — 0.1
VIN = VIL or VIH
IOUT = 50 µA
3.0 — — 0.32 — 0.37 IOL = 12 mA
4.5 — — 0.32 — 0.37 IOL = 24 mA
Output voltage
VOL
5.5 — — 0.32 — 0.37
V
VIN = VIL or VIH
IOL = 24 mA
Input leakage
current IIN 5.5 — — ±0.1 — ±1.0 µAV
IN = VCC or GND
IOLD 5.5———86—mAV
OLD = 1.1 V
Dynamic outp ut
current*IOHD 5.5 — — — –75 — mA VOHD = 3.85 V
Quiescent su pply
current ICC 5.5 — — 8.0 — 80 µAV
IN = VCC or ground
*Maximum test duration 2.0 ms, one output loaded at a time.
HD74AC283/HD74ACT283
Rev.2.00, Jul.16.2004, page 6 of 9
Recommended Operating Conditions: HD74ACT283
Item Symbol Ratings Unit Condition
Supply voltage VCC 2 to 6 V
Input and output voltage VI, VO0 to VCC V
Operating temperature Ta –40 to +85 °C
Input rise and fall time
(except Schmitt inputs)
VIN 0.8 to 2.0 V
tr, tf 8 ns/V VCC = 4.5V
VCC = 5.5V
DC Characteristics: HD74ACT283
Ta = 25°
°°
°C Ta = –40 to
+85°
°°
°C
Item Sym-
bol VCC
(V) min. typ. max. min. max.
Unit Condition
4.5 2.0 1.5 — 2.0 —VIH 5.5 2.0 1.5 — 2.0 — VOUT = 0.1 V or Vcc–0.1 V
4.5 — 1.5 0.8 — 0.8
Input voltage
VIL 5.5 — 1.5 0.8 — 0.8
V
VOUT = 0.1 V or Vcc–0.1 V
4.5 4.4 4.49 — 4.4 —
5.5 5.4 5.49 — 5.4 — VIN = VIL or VIH
IOUT = –50 µA
4.5 3.94 — — 3.80 — IOH = –24 mA
VOH
5.5 4.94 — — 4.80 — VIN = VIL IOH = –24 mA
4.5 — 0.001 0.1 — 0.1
5.5 — 0.001 0.1 — 0.1 VIN = VIL or VIH
IOUT = 50 µA
4.5 — — 0.32 — 0.37 IOL = 24 mA
Output voltage
VOL
5.5 — — 0.32 — 0.37
V
VIN = VIL IOL = 24 mA
Input current IIN 5.5 — — ±0.1 — ±1.0 µAV
IN = VCC or GND
ICC/input current ICCT 5.5 — 0.6 — — 1.5 mA VIN = VCC–2.1 V
IOLD 5.5 — — — 86 — mA VOLD = 1.1 VDynamic outp ut
current*IOHD 5.5 — — — –75 — mA VOHD = 3.85 V
Quiescent su pply
current ICC 5.5 — — 8.0 — 80 µAV
IN = VCC or ground
*Maximum test duration 2.0 ms, one output loaded at a time.
HD74AC283/HD74ACT283
Rev.2.00, Jul.16.2004, page 7 of 9
AC Characteristics: HD74AC283
Ta = +25°C
CL = 50 pF Ta = –40°C to +85°C
CL = 50 pF
Item Symbol VCC (V)*1Min Typ Max Min Max Unit
Propagation delay tPLH 3.3 1.0 11.5 15.0 1.0 16.5 ns
C0 to Sn5.0 1.0 9.5 11.5 1.0 12.5
Propagation delay tPHL 3.3 1.0 10.5 14.0 1.0 15.5 ns
C0 to Sn5.0 1.0 8.5 10.5 1.0 11.5
Propagation delay tPLH 3.3 1.0 14.0 17.0 1.0 18.5 ns
An or Bn to Sn5.0 1.0 11.5 13.5 1.0 14.5
Propagation delay tPHL 3.3 1.0 13.5 16.5 1.0 18.0 ns
An or Bn to Sn5.0 1.0 11.0 13.0 1.0 14.0
Propagation delay tPLH 3.3 1.0 9.5 12.5 1.0 15.5 ns
C0 to C45.0 1.0 7.5 9.5 1.0 10.5
Propagation delay tPHL 3.3 1.0 10.0 13.0 1.0 14.0 ns
C0 to C45.0 1.0 8.0 10.0 1.0 11.0
Propagation delay tPLH 3.3 1.0 11.5 14.5 1.0 16.0 ns
An or Bn to C45.0 1.0 9.5 11.5 1.0 12.5
Propagation delay tPHL 3.3 1.0 12.0 15.0 1.0 16.5 ns
An or Bn to C45.0 1.0 10.0 12.0 1.0 13.0
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Characteristics: HD74ACT283
Ta = +25°C
CL = 50 pF Ta = –40°C to +85°C
CL = 50 pF
Item Symbol VCC (V)*1Min Typ Max Min Max Unit
Propagation delay
C0 to Sn
tPLH 5.0 1.0 11.5 13.5 1.0 14.5 ns
Propagation delay
C0 to Sn
tPHL 5.0 1.0 10.0 12.0 1.0 13.0 ns
Propagation delay
An or Bn to Sn
tPLH 5.0 1.0 13.0 15.0 1.0 16.5 ns
Propagation delay
An or Bn to Sn
tPHL 5.0 1.0 12.0 14.0 1.0 15.5 ns
Propagation delay
C0 to C4
tPLH 5.0 1.0 9.0 11.0 1.0 12.0 ns
Propagation delay
C0 to C4
tPHL 5.0 1.0 10.0 12.0 1.0 13.0 ns
Propagation delay
An or Bn to C4
tPLH 5.0 1.0 11.0 13.0 1.0 14.0 ns
Propagation delay
An or Bn to C4
tPHL 5.0 1.0 11.5 13.5 1.0 14.5 ns
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item Symbol Typ Unit Condition
Input capacitan ce CIN 4.5 pF VCC = 5.5 V
Power dissipation capacitance CPD 60.0 pF VCC = 5.0 V
HD74AC283/HD74ACT283
Rev.2.00, Jul.16.2004, page 8 of 9
Package Dime nsions
16
18
9
19.2
20.32 Max
6.3
7.4 Max
5.06 Max2.54 Min
0.51 Min
Package Code
JEDEC
JEITA
Mass
(reference value)
DP-16E
Conforms
Conforms
1.05 g
2.54 ± 0.25 0.48 ± 0.1
0.89 1.3 7.62
0.25+ 0.1
– 0.05
0˚ – 15˚
As of January, 2003
Unit: mm
16
18
9
19.2
20.32 Max
6.3
7.4 Max
5.06 Max2.54 Min
0.51 Min
Package Code
JEDEC
JEITA
Mass
(reference value)
DP-16FV
Conforms
Conforms
1.05 g
2.54 ± 0.25
*NI/Pd/AU Plating
*0.48 ± 0.08
0.89 1.3 7.62
*0.25
± 0.06
0˚ – 15˚
Unit: mm
HD74AC283/HD74ACT283
Rev.2.00, Jul.16.2004, page 9 of 9
Package Code
JEDEC
JEITA
Mass
(reference value)
FP-16DAV
—
Conforms
0.24 g
*Ni/Pd/Au plating
*0.20 ± 0.05
*0.40 ± 0.06
0.12
0.15
M
2.20 Max
5.5
10.06
0.80 Max
16 9
18
10.5 Max
+ 0.20
– 0.30
7.80
0.70 ± 0.20
0˚ – 8˚
0.10 ± 0.10
1.15
1.27
As of January, 2003
Unit: mm
Package Code
JEDEC
JEITA
Mass
(reference value)
FP-16DNV
Conforms
Conforms
0.15 g
*Ni/Pd/Au plating
1.27
16 9
18
0.15
0.25
M
1.75 Max 3.95
*0.20 ± 0.05
9.9
0˚ – 8˚
10.3 Max
+ 0.10
– 0.30
6.10
+ 0.67
– 0.20
0.60
+ 0.11
– 0.04
0.14
*0.40 ± 0.06
0.635 Max
1.08
As of January, 2003
Unit: mm
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
http://www.renesas.com
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501
Renesas Technology Europe Limited.
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom
Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900
Renesas Technology Europe GmbH
Dornacher Str. 3, D-85622 Feldkirchen, Germany
Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11
Renesas Technology Hong Kong Ltd.
7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2375-6836
Renesas Technology Taiwan Co., Ltd.
FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
RENESAS SALES OFFICES
© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .1.0
