5962-9952302QZC(E2VCYPRESS) - e2v Aerospace & Defense

REVISIONS

LTR DESCRIPTION DATE (YR-MO-DA) APPROVED

A

Table I changes; CIN, fMAX2 for device 02, fMAX3 for device 01, fMAX4 for

devices 01 and 02, tHPT, tSPT, tIHPT, tISPT and tSLEW for devices 01 and

02, editorial changes Table I and Terminal connections. ksr

01 - 06 - 05

Raymond Monnin

B Boilerplate update and part of five year review. tcr 05-12-29 Raymond Monnin

REV

SHEET

REV B B B B B B B B B B

SHEET 15 16 17 18 19 20 21 22 23 24

REV STATUS

REV B B B B B B B B B B B B B B

OF SHEETS

SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14

PMIC N/A

PREPARED BY

Kenneth Rice

STANDARD

MICROCIRCUIT

DRAWING

CHECKED BY

Jeff Bowling

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

http://www.dscc.dla.mil

APPROVED BY

Raymond Monnin

THIS DRAWING IS

AVAILABLE

FOR USE BY All

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

DRAWING APPROVAL DATE

00-03-09

MICROCIRCUIT, MEMORY, DIGITAL, CMOS, ELECT RICALLY

ALTERABLE (IN-SYS REPROGRAMMABLE), 256

MACROCELL, PROGRAMMABLE LOGIC DEVICE,

MONOLITHIC SILICON

AMSC N/A REVISION LEVEL

B

SIZE

A CAGE CODE

67268

5962-99523

SHEET

1 OF

23

DSCC FORM 2233

APR 97 5962- E164-06

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

2

DSCC FORM 2234

APR 97

1. SCOPE

1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)

and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or

Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

1.2 PIN. The PIN is as shown in the following example:

5962 - 99523 01 Q X X

Federal

stock class

designator

RHA

designator

(see 1.2.1)

Device

type

(see 1.2.2)

Device

class

designator

Case

outline

(see 1.2.4)

Lead

finish

(see 1.2.5)

\ / (see 1.2.3)

\/

Drawing number

1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are

marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A

specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.

1.2.2 Device type(s). The device type(s) identify the circuit function as follows:

Device type Generic number Circuit function Toggle Speed (Mhz)

01 CY37256 256 Macrocell CPLD 83

02 CY37256 256 Macrocell CPLD 125

1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as

follows:

Device class Device requirements documentation

M Vendor self-certification to the requirements for MIL-STD-883 compliant,

non-JAN class level B microcircuits in accordance with MIL-PRF-38535,

appendix A

Q or V Certification and qualification to MIL-PRF-38535

1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:

Outline letter Descriptive designator Terminals Package style

Z See figure 1 160 Quad flat package

1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,

appendix A for device class M.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

3

DSCC FORM 2234

APR 97

1.3 Absolute maximum ratings. 1/

Supply voltage range (VCC)--------------------------------------- -0.5 V dc to +7.0 V dc

Programming supply voltage range (VPP)--------------------- 4.5 V dc to 5.5 V dc

DC input voltage range ------------------------------------------- -0.5 V dc to +7.0 V dc

Maximum power dissipation-------------------------------------- 2.0 W 2/

Lead temperature (soldering, 10 seconds) ------------------ +260°C

Thermal resistance, junction-to-case (θJC):

Case outline Z------------------------------------------------------ 7.2° C/W

Junction temperature (TJ)----------------------------------------- +150°C 3/

Storage temperature range--------------------------------------- -65°C to +150°C

Endurance ---------------------------------------------------------- 25 erase/write cycles (minimum)

Data retention-------------------------------------------------------- 10 years (minimum)

1.4 Recommended operating conditions. 4/

Case operating temperature Range(TC)----------------------- -55°C to +125°C

Supply voltage relative to ground(VCC) ------------------------ +4.5 V dc minimum to +5.5 V dc maximum

Ground voltage (GND)--------------------------------------------- 0 V dc

Input high voltage (VIH) -------------------------------------------- 2.0 V dc minimum

Input low voltage (VIL)---------------------------------------------- 0.8 V dc maximum

2. APPLICABLE DOCUMENTS

2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part

of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the

solicitation or contract.

DEPARTMENT OF DEFENSE SPECIFICATION

MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.

DEPARTMENT OF DEFENSE STANDARDS

MIL-STD-883 - Test Method Standard Microcircuits.

MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.

DEPARTMENT OF DEFENSE HANDBOOKS

MIL-HDBK-103 - List of Standard Microcircuit Drawings.

MIL-HDBK-780 - Standard Microcircuit Drawings.

(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from

the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the

maximum levels may degrade performance and affect reliability.

2/ Must withstand the added PD due to short circuit test (e.g., IOS).

3/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in

accordance with method 5004 of MIL-STD-883.

4/ All voltage values in this drawing are with respect to VSS.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

4

DSCC FORM 2234

APR 97

2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.

Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation.

AMERICAN SOCIETY FOR TEST ING AND MATERIALS (ASTM)

ASTM Standard F1192M-95 - Standard Guide for the Measurement of Single Event Phenomena from

Heavy Ion Irradiation of Semiconductor Devices.

(Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr

Harbor Drive, West Conshohocken, PA 19428-2959; http://www.astm.org.)

ELECTRONICS INDUSTRIES ASSOCIATION (EIA)

JEDEC Standard EIA/JESD78 - IC Latch-Up Test.

(Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA

22201; http://www.jedec.org.)

(Non-Government standards and other publications are normally available from the organizations that prepare or distribute the

documents. These documents also may be available in or through libraries or other informational services.)

2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of

this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a

specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with

MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The

modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for

device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified

herein.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in

MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.

3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full

case operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical

tests for each subgroup are defined in table I.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer

has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be

marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be

in accordance with MIL-PRF-38535, appendix A.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

5

DSCC FORM 2234

APR 97

3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in

MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.

3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535

listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of

compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see

6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this

drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and

herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.

3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in

MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to

this drawing.

3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2

herein) involving devices acquired to this drawing is required for any change that affects this drawing.

3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the

option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made

available onshore at the option of the reviewer.

3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in

microcircuit group number 42 (see MIL-PRF-38535, appendix A).

3.11 Processing CPLDs. All testing requirements and quality assurance provisions herein shall be satisfied by the

manufacturer prior to delivery.

3.11.1 Erasure of CPLDs. When specified, devices shall be erased in accordance with the procedures and characteristics

specified in 4.6 herein.

3.11.2 Programmability of CPLDs. When specified, devices shall be programmed to the specified pattern using the

procedures and characteristics specified in 4.7 herein.

3.11.3 Verification of erasure or programmed CPLDs. When specified, devices shall be verified as either programmed (see

4.7 herein) to the specified pattern or erased (see 4.6 herein). As a minimum, verification shall consist of performing a func tional

test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute

a device failure, and shall be removed from the lot.

3.12 Endurance. A reprogrammability test shall be completed as part of the vendor's reliability monitor. This

reprogrammability test shall be done only for initial characterization and after any design or process changes which may affect

the reprogrammability of the device. The methods and procedures may be vendor specific, but shall be under document control

and shall be made available upon request.

3.13 Data retention. A data retention stress test shall be completed as part of the vendor's reliability monitors. This test

shall be done for initial characterization and after any design or process change which may affect data retention. The methods

and procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein, over the full military

temperature range. The vendor's procedure shall be kept under document control and shall be made available upon request by

the preparing or acquiring activity, along with the test data.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

6

DSCC FORM 2234

APR 97

TABLE I. Electrical performance characteristics.

Limits

Test

Symbol

Conditions

4.5 V < VCC < 5.5 V

-55oC < TC < +125oC

unless otherwise specified

Group A

Subgroups

Device

type

Min

Max

Unit

High Level output

voltage

V

OH

VCC = 4.5 V, VIL = 0.8V

IOH = -2.0 mA, VIH = 2.0 V 1/

2.4

V

VCC = 5.5 V, VIL = 0.8V

IOH = 0 µA, VIH = 2.0 V 3/

4.5

V

High Level output

voltage with Output

Disabled 2/

V

OHZ

VCC = 5.5 V, VIL = 0.8V

IOH = -150 µA, VIH = 2.0 V 3/

3.6

V

Low level output

voltage

V

OL

VCC = 4.5 V, IOL = 12.0 mA

VIL = 0.8 V, VIH = 2.0 V 1/

0.5

V

High level input voltage

4/

V

IH

2

VCC+

0.5 V

V

Low level input voltage

4/

V

IL

-0.5

0.8

V

Input load current

I

IX

VIN = 0 V or VCC, with

Busshold off

-10

+10

µA

Output leakage current

I

OZ

VCC = 5.5 V

VO = GND or VCC,

Output disabled, Busshold off

-50

+50

µA

Output short circuit

current 2/ 5/

I

OS

VCC = 5.5 V, VOUT = 0.5 V

-30

-160

mA

Power supply current

6/

I

CC

VCC = 5.5 V, IOUT = 0 mA,

VIN = 0 V and 5.5 V

f = 1.0 MHz

300

mA

Input bus hold low

sustained current 2/

IBHL

VCC = 4.5 V,VIL = 0.8 V

+75

µA

Input bus hold high

sustained current 2/

IBHH

VCC = 4.5 V,VIH = 2.0 V

-75

µA

Input bus hold low

sustained overdrive

current 2/

IBHLO

VCC = 5.5 V

+500

µA

Input bus hold high

sustained overdrive

current 2/

IBHHO

VCC = 5.5 V

1, 2, 3

All

-500

µA

See footnotes at end of table.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

7

DSCC FORM 2234

APR 97

TABLE I. Electrical performance characteristics - Continued.

Limits

Test

Symbol

Conditions

4.5 V < VCC < 5.5 V

-55oC < TC < +125oC

unless otherwise specified

Group A

Subgroups

Device

type

Min

Max

Unit

Input capacitance 2/

C

IN

10

Output capacitance 2/

C

OUT

12

Dual functional pin

capacitance 2/

C

DP

See 4.4.1e, VIN = 5.0 V,

f = 1 Mhz, TA = 25°C

4

All

16

pF

Functional test

See 4.4.1c

7,8A,8B

All

01

15

Input to combinatorial

output 7/ 8/ 9/ 10/

t

PD

See figures 3 and 4

(circuit A)

9, 10, 11

02

10

01

19

Input to output through

transparent input or

output latch 2/ 7/ 8/ 9/10/

t

PDL

02

16.5

01

20

Input to output through

transparent input and

output latch 2/ 7/ 8/ 9/

10/

t

PDLL

See figures 3 and 4

(circuit A)

02

17.5

01

19

Input to output enable

see figure 3 test

waveforms 2/ 7/ 8/ 9/10/

t

EA

02

14

01

19

Input to output disable

see figure 3 test

waveforms 2/ 7/ 8/

t

ER

See figures 3 and 4

(circuit B)

02

14

01

4

Clock or Latch enable

input High time 2/ 7/

t

WH

02

3

01

4

Clock or latch enable

input low time 2/ 7/

t

WL

02

3

01

3

Input register or latch

set-up time 2/ 7/

t

IS

02

2

01

3

Input register or latch

hold time 2/ 7/

t

IH

02

2

01

19

Input register clock or

latch enable to

combinatorial output

2/ 7/ 8/ 9/10/

t

ICO

See figures 3 and 4

(circuit A)

9, 10, 11

02

12.5

ns

See footnotes at end of table.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

8

DSCC FORM 2234

APR 97

TABLE I. Electrical performance characteristics - Continued.

Limits

Test

Symbol

Conditions

4.5 V < VCC < 5.5 V

-55oC < TC < +125oC

unless otherwise specified

Group A

Subgroups

Device

type

Min

Max

Unit

01

21

Input register clock or

latch enable to output

through transparent

output latch 2/ 7/ 8/

9/10/

t

ICOL

02

16

ns

01

8

Synchronous clock or

latch enable to output 7/

9/10/

t

CO

02

6.5

ns

Register or latch data

hold time 7/

t

H

All

0

ns

01

8

Set-up time from input to

synchronous clock or

latch enable 7/ 8/

t

S

02

5.5

ns

01

15

Set-up time from input

through transparent latch

to output register

Synchronous clock or

latch enable 2/ 7/ 8/

t

SL

02

10

ns

01

19

Output Synchronous

clock or latch enable to

combinatorial output

delay (through memory

array)

2/ 7/ 8/ 9/ 10/

t

CO2

02

14

ns

01

12

Output Synchronous

clock or latch enable to

output synchronous

clock or latch enable

(through logic array)

7/ 8/

t

SCS

02

8

ns

Hold time for input

through transparent latch

from output register

Synchronous clock or

latch enable

2/ 7/

t

HL

All

0

ns

01

83

Maximum frequency with

internal feedback (lesser

of 1/tSCS, 1/(tS + tH), or

1/tCO) 2/ 7/

f

MAX1

See figures 3 and 4

(circuit A)

9, 10, 11

02

125

Mhz

See footnotes at end of table.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

9

DSCC FORM 2234

APR 97

TABLE I. Electrical performance characteristics - Continued.

Limits

Test

Symbol

Conditions

4.5 V < VCC < 5.5 V

-55oC < TC < +125oC

unless otherwise specified

Group A

Subgroups

Device

type

Min

Max

Unit

01

125

Maximum frequency data

path in output

register/latched mode

(lesser of 1/(tWL + tWH),

1/(tS + tH), or 1/tCO) 2/ 7/

f

MAX2 02

154

01

62.5

Maximum frequency with

external feedback (lesser

of 1/(tCO + tS),or 1/(tWL +

tWH) 2/ 7/

f

MAX3 02

83

01

83

Maximum frequency in

pipelined mode (lesser of

1/(tCO + tIS), 1/tICS, 1/(tWL +

tWH), 1/(tIS + tIH),or 1/tSCS

2/ 7/

f

MAX4 02

118

MHz

01

12

Input register

Synchronous clock to

output register clock 2/ 7/

8/

t

ICS 02

8

01

15

Asynchronous preset

width 2/ 7/

t

PW 02

10

01

17

Asynchronous preset

recovery time 2/ 7/ 8/

t

PR 02

12

01

21

Asynchronous preset to

output 2/ 7/ 8/ 9/10/

t

PO 02

15

01

15

Asynchronous reset width

2/ 7/

t

RW 02

10

01

17

Asynchronous reset

recovery time 2/ 7/ 8/

t

RR 02

12

01

21

Asynchronous reset to

output 2/ 7/ 8/ 9/ 10/

t

RO 02

15

01

15

Product term clock or

latch enable (PTCLK) to

output 2/ 7/ 8/ 9/ 10/

tCOPT 02

13

01

6.0

Register or latch data hold

time 2/ 7/

tHPT 02

5.0

01

6.0

Set-up time from input to

product term clock or

latch enable(PTCLK) 2/ 7/

tSPT

See figures 3 and 4

(circuit A)

9, 10, 11

02

5.0

ns

See footnotes at the end of table.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

10

DSCC FORM 2234

APR 97

TABLE I. Electrical performance characteristics - Continued.

Limits

Test

Symbol

Conditions

4.5 V < VCC < 5.5 V

-55oC < TC < +125oC

unless otherwise specified

Group A

Subgroups

Device

type

Min

Max

Unit

Set-up time for buried

register used as an input

register from input to

product term clock or

latch enable (PTCLK)

2/ 7/ 8/

tISPT All

0

01

14

Buried register used as

an input register or latch

data hold time 2/ 7/

tIHPT 02

9

01

24

Product term clock or

latch enable (PTCLK) to

output delay (through

logic array) 2/ 7/ 8/ 9/10/

tCO2PT 02

19

Low power adder 2/ 7/

t

LP All

2.5

Slow output slew rate

adder 2/ 7/

t

SLEW All

3.0

3.3 V I/O mode timing

adder 2/ 7/

t

3.3IO All

0.3

Set-up time from TDI

and TMS to TCK 2/ 7/

t

S JTAG All

0

Hold time on TDI and

TMS 2/ 7/

t

H JTAG All

20

Falling edge of TCK to

TDO 2/ 7/

tCO JTAG All

20

ns

Maximum JTAG tap

controller frequency 2/

7/

f

JTAG

See figures 3 and 4

(circuit A)

9, 10, 11

All

20

MHz

1/ IOH = -2 mA, IOL = +2 mA for TDO.

2/ Tested initially and after any design or process changes that affect this parameter.

3/ When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to a maximum of 3.6 V if no leakage current is

allowed. This voltage is lowered significantly by a small leakage current. Note that all I/Os are output disabled during ISR

programming. Contact manufacturer for additional information.

4/ These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.

5/ Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5

V has been chosen to avoid test problems caused by tester ground degradation.

6/ Measured under AC conditions. Program pattern using 16-bit counter per logic block or equivalent.

7/ All AC parameters are measured with 2 outputs switching, and 35 pF AC test load, unless otherwise specified.

8/ Logic blocks operating in low power mode, add tLP to this spec.

9/ Outputs using slow output slew rate, add tSLEW to this spec.

10/ When VCCO = 3.3 V add t3.3IO to this spec.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

11

DSCC FORM 2234

APR 97

Case Z

FIGURE 1. Case outline.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

12

DSCC FORM 2234

APR 97

Case outline Z

Device

type

All

Device

type

All

Device

type

All

Terminal

number

Terminal

symbol

Terminal

number

Terminal

symbol

Terminal

number

Terminal

symbol

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

GND

I/O

I/O/TCK

I/O

GND

I/O

CLK/I

VCC0

GND

CLK/I

I/O

GND

I/O

VCC0

GND

I/O

I/O/TMS

I/O

GND

I/O

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

I/O

I

VCC0

GND

VCC

I/O

GND

I/O

I/O/TDO

I/O

VCC0

GND

I/O

GND

I/O

CLK/I

VCC0

GND

CLK/I

I/O

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

I/O

GND

I/O

I/O/TD1

I/O

VCC0

GND

I/O

GND

I/O

JTAGEN

VCC

GND

VCC0

I/O

GND

I/O

VCC0

FIGURE 2. Terminal connections.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

13

DSCC FORM 2234

APR 97

FIGURE 3. Output load circuits and test conditions.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

14

DSCC FORM 2234

APR 97

FIGURE 3. Output load circuits and test conditions - Continued.

1.5 V

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

15

DSCC FORM 2234

APR 97

FIGURE 4. Switching waveforms.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

16

DSCC FORM 2234

APR 97

FIGURE 4. Switching waveforms - Continued.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

17

DSCC FORM 2234

APR 97

FIGURE 4. Switching waveforms - Continued.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

18

DSCC FORM 2234

APR 97

FIGURE 4. Switching waveforms - Continued.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

19

DSCC FORM 2234

APR 97

FIGURE 4. Switching waveforms - Continued.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

20

DSCC FORM 2234

APR 97

FIGURE 4. Switching waveforms - Continued.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

21

DSCC FORM 2234

APR 97

TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7/

Subgroups

(in accordance

with MIL-STD-883,

method 5005, table I)

Subgroups

(in accordance with

MIL-PRF-38535, table III)

Line

no.

Test

requirements

Device

class M

Device

class Q

Device

class V

1

Interim electrical

Parameters

(see 4.2)

1,7,9

or

2,8A,10

2

Static burn-in

(method 1015)

Not

Required

Not

Required

3 Same as line 1 1*,7* ∆

4 Dynamic burn-in

(method 1015) Required Required Required

5 Final electrical

parameters 1*,2,3,7*,

8A,8B,9,10,

11

1*,2,3,7*,

8A,8B,9,10,

11

1*,2,3,7*,

8A,8B,9,10,

11

6 Group A test

requirements 1,2,3,4**,7,

8A,8B,9,10,

11

1,2,3,4**,7,

8A,8B,9,10,

11

1,2,3,4**,7,

8A,8B,9,10,

11

7 Group C end-point

electrical

parameters 2,3,7,

8A,8B 2,3,7,

8A,8B 1,2,3,7,

8A,8B,9,

10,11 ∆

8 Group D end-point

electrical

parameters 2,3,

8A,8B 2,3,

8A,8B

9 Group E end-point

electrical

parameters 1,7,9 1,7,9 1,7,9

1/ Blank spaces indicate tests are not applicable.

2/ Any or all subgroups may be combined when using high-speed testers.

3/ Subgroups 7 and 8 functional tests shall verify the truth table.

4/ * indicates PDA applies to subgroup 1 and 7.

5/ ** see 4.4.1e.

6/ ∆ indicates delta limit (see table IIB) shall be required where specified, and the delta values shall be

computed with reference to the previous interim electrical parameters (see line 1).

7/ See 4.4.1d.

TABLE IIB. Delta limits at +25°C.

1/ The above parameter shall be recorded before

and after the required burn-in and life tests

to determine the delta ∆.

Device types

Parameter 1/ All

IOZ ±10% of the specified

value in table I

IIX ±10% of the specified

value in table I

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

22

DSCC FORM 2234

APR 97

4. VERIFICATION

4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with

MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan

shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in

accordance with MIL-PRF-38535, appendix A.

4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted

on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in

accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.

4.2.1 Additional criteria for device class M.

a. Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in)

electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.

b. Prior to burn-in, the devices shall be programmed (see 4.7 herein) with a checkerboard pattern or equivalent

(manufacturers at their option may employ an equivalent pattern provided it is topologically true alternating bit pattern).

The pattern shall be read before and after burn-in. Devices having bits not in the proper state after burn-in shall

constitute a device failure and shall be removed from the lot. The manufacturer as an option may use built-in test

circuitry by testing the entire lot to verify programmability and AC performance without programming the user array.

c. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made

available to the preparing or acquiring activity upon request. For device class M the test circuit shall specify the inputs,

outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015.

d. Interim and final electrical parameters shall be as specified in table IIA herein.

4.2.2 Additional criteria for device classes Q and V.

a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the

device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under

document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with

MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall

specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in

method 1015 of MIL-STD-883.

b. Interim and final electrical test parameters shall be as specified in table IIA herein.

c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in

MIL-PRF-38535, appendix B.

4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in

accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups

A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).

4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with

MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for

device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed

for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections

(see 4.4.1 through 4.4.4).

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

23

DSCC FORM 2234

APR 97

4.4.1 Group A inspection.

a. Tests shall be as specified in table IIA herein.

b. Subgroups 5 and 6 of table I of method 5005 of MIL-STD-883 shall be omitted.

c. For device class M subgroups 7, 8A and 8B tests shall consist of verifying functionality of the device. These tests form

a part of the vendors test tape and shall be maintained and available upon request. For device classes Q and V

subgroups 7, 8A and 8B shall include verifying the functionality of the device.

d. O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may

affect the performance of the device. For device class M, procedures and circuits shall be maintained under document

revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity upon

request. For device classes Q and V, the procedures and circuits shall be under the control of the device

manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or

acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be

considered destructive. Information contained in JEDEC Standard EIA/JESD78 may be used for reference.

e. Subgroup 4 (CIN, COUT, and CDP measurements) shall be measured only for initial qualification and after any process

or design changes which may affect capacitance. Capacitance shall be measured between the designated terminal and

GND at a frequency of 1 MHz. Sample size is three devices with no failures, and all input and output terminals tested.

4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.

4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005:

a. Test condition D . The test circuit shall be maintained by the manufacturer under document revision level control and

shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs,

outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-

STD-883.

b. TA = +125°C, minimum.

c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.

4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,

or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The

test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with

MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the

inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-

883.

4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.

4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured

(see 3.5 herein).

a. End-point electrical parameters shall be as specified in table IIA herein.

b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as

specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to

radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device

classes must meet the postirradiation end-point electrical parameter limits as defined in table I at

T

A = +25ºC ±5ºC, after exposure, to the subgroups specified in table IIA herein.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

5962-99523

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

B SHEET

24

DSCC FORM 2234

APR 97

4.5 Delta measurements for device class V. Delta measurements, as specified in table IIA, shall be made and recorded

before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical

parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option,

either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7, and

9.

4.6 Erasure procedures. Erasure procedures shall be as specified by the device manufacturer and shall be made available

upon request.

4.7 Programming procedures. The programming procedures shall be as specified by the device manufacturer and shall be

made available upon request.

5. PACKAGING

5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes

Q and V or MIL-PRF-38535, appendix A for device class M.

6. NOTES

6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications

(original equipment), design applications, and logistics purposes.

6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor

prepared specification or drawing.

6.1.2 Substitutability. Device class Q devices will replace device class M devices.

6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for

the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.

6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system

application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users

and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic

devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.

6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43218-3990, or telephone

(614) 692-0547.

6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in

MIL-PRF-38535 and MIL-HDBK-1331.

6.6 Sources of supply.

6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.

The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to

this drawing.

6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.

The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been

submitted to and accepted by DSCC-VA.

STANDARD MICROCIRCUIT DRAWING BULLETIN

DATE: 05-12-29

Approved sources of supply for SMD 5962-99523 are listed below for immediate acquisition information only and shall

be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised

to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate

of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next

dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of

supply at http://www.dscc.dla.mil/Programs/Smcr/.

Standard

microcircuit

drawing PIN 1/

Vendor

CAGE

number

Vendor

similar

PIN 2/

5962-9952301QZC

65786

CY37256P160-83UMB

5962-9952302QZC

65786

CY37256P160-125UMB

1/ T he lead finish shown for each PIN representing

a hermetic package is the most readily available

from the manufacturer listed for that part. If the

desired lead finish is not listed, contact the vendor

to determine its availability.

2/ Caution. Do not use this number for item

acquisition. Items acquired to this number may not

satisfy the performance requirements of this drawing.

Vendor CAGE Vendor name

number and address

65786 Cypress Semiconductor

3901 North First Street

San Jose, CA 95134

The information contained herein is disseminated for convenience only and the

Government assumes no liability whatsoever for any inaccuracies in the

information bulletin.