0 XC1700E Family of Serial Configuration PROMs R December 7, 1998 (Version 1.4) 0 8* Product Specification Features Description * The XC1700 family of serial configuration PROMs (SPROMs) provides an easy-to-use, cost-effective method for storing Xilinx FPGA configuration bitstreams. * * * * * * * * * Serial Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices Simple interface to the FPGA requires only one user I/O pin Cascadable for storing longer or multiple bitstreams Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions The XC17128E/EL and XC17256E/EL devices support the XC4000EX/XL/XLA/XV fast configuration mode (15.0 MHz) Low-power CMOS floating gate process Available in 5 V and 3.3 V versions Available in compact plastic 8-pin DIP, 8-pin SOIC, 8-pin VOIC, or 20-pin PLCC packages. Programming support by leading programmer manufacturers. Design support using the Xilinx Alliance and Foundation series software packages. VCC VPP When the FPGA is in Master Serial mode, it generates a configuration clock that drives the SPROM. A short access time after the rising clock edge, data appears on the SPROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the SPROM. When the FPGA is in Slave Serial mode, the SPROM and the FPGA must both be clocked by an incoming signal. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all SPROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance or the Foundation series development systems compiles the FPGA design file into a standard HEX format which is then transferred to most commercial PROM programmers. GND CEO CE RESET/ OE or OE/ RESET CLK Address Counter EPROM Cell Matrix TC Output OE DATA X3185 Figure 1: Simplified Block Diagram (does not show programming circuit) December 7, 1998 (Version 1.4) 8-13 8 R XC1700E Family of Serial Configuration PROMs Pin Description Serial PROM Pinouts Pin Name 8-Pin 20-Pin DATA 1 2 CLK 2 4 RESET/OE (OE/RESET) 3 6 CLK CE 4 8 Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active. GND 5 10 CEO 6 14 RESET/OE VPP 7 17 When High, this input holds the address counter reset and 3-states the DATA output. The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at zero, and the DATA output is 3-stated. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can be driven by the FPGA's INIT pin. VCC 8 20 DATA Data output, 3-stated when either CE or OE are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active Low. The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW-130 programmer software. Third-party programmers have different methods to invert this pin. Capacity Device Configuration Bits XC1736E 36,288 XC1765E or EL 65,536 XC17128E or EL 131,072 XC17256E or EL 262,144 XC17512L 524,288 XC1701, XC1701L or XQ1701L 1,048,576 XC1702L 2,097,152 XC1704L 4,194,304 Note: The XC17512L and larger SPROMs are specified in a separate datasheet. CE When High, this pin disables the internal address counter, 3-states the DATA output, and forces the device into low-ICC standby mode. CEO Chip Enable output, to be connected to the CE input of the next SPROM in the daisy chain. This output is Low when the CE and OE inputs are both active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. In other words: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEO stays High until the PROM is reset. Note that OE can be programmed to be either active High or active Low. VPP Programming voltage. No overshoot above the specified max voltage is permitted on this pin. For normal read operation, this pin must be connected to VCC. Failure to do so may lead to unpredictable, temperature-dependent operation and severe problems in circuit debugging. Do not leave VPP floating! VCC and GND VCC is positive supply pin and GND is ground pin. 8-14 December 7, 1998 (Version 1.4) R XC1700E Family of Serial Configuration PROMs Number of Configuration Bits, Including Header for Xilinx FPGAs and Compatible SPROMs Controlling Serial PROMs Device XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4002XL XC4005XL XC4010XL XC4013XL/XLA XC4020XL/XLA XC4028XL/XLA XC4028EX XC4036EX/XL/XLA XC4036EX XC4044XL/XLA XC4052XL/XLA XC4062XL/XLA XC4085XL/XLA XC40110XV XC40150XV XC40200XV * XC5202 XC5204 XC5206 XC5210 XC5215 XCV50 42,416 70,704 106,288 165,488 237,744 559,232 SPROM XC17128E1 XC17128E XC17128E XC17256E XC17256E XC17256E XC1701 XC1701 XC17128EL1 XC17256EL XC17512L XC17512L XC17512L XC1701L XC1701 XC1701L XC1701 XC1701L XC1702L XC1702L XC1702L XC1704L XC1704L XC1704L + XC17512L XC1704L+ XC1702L XC1765E XC17128E XC17128E XC17256E XC17256E XC1701L XCV100 XCV150 781,248 1,041,128 XC1701L XC1701L XCV200 XCV300 1,335,872 1,751,840 XC1702L XC1702L XCV400 XCV600 XCV800 2,546,080 3,608,000 4,715,648 XCV1000 6,127,776 XC1704L XC1704L XC1704L + XC1701L XC1704L + XC1702L XC40250XV Note: Configuration Bits 53,984 95,008 119,840 147,552 178,144 247,968 329,312 422,176 61,100 151,960 283,424 393,632 521,880 668,184 668,184 832,528 832,528 1,014,928 1,215,368 1,433,864 1,924,992 2,686,136 3,373,448 4,551,056 5,433,888 1. The suggested SPROM is determined by compatibility with the higher configuration frequency of the Xilinx FPGA CCLK. Designers using the default slow configuration frequency (CCLK) can use the XC1765E or XC1765EL for the noted FPGA devices. 2. The XC1701, XC1701L, XC1702L, XC1704L & XC17512L are specified in a separate XC1700L High Density datasheet. December 7, 1998 (Version 1.4) Connecting the FPGA device with the SPROM. * * * * * The DATA output(s) of the SPROM(s) drives the DIN input of the lead FPGA device. The Master FPGA CCLK output drives the CLK input(s) of the SPROM(s). The CEO output of a SPROM drives the CE input of the next SPROM in a daisy chain (if any). The RESET/OE input of all SPROMs is best driven by the INIT output of the lead FPGA device. This connection assures that the SPROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. Other methods - such as driving RESET/OE from LDC or system reset - assume the SPROM internal power-on-reset is always in step with the FPGA's internal power-on-reset. This may not be a safe assumption. The SPROM CE input can be driven from either the LDC or DONE pins. Using LDC avoids potential contention on the DIN pin. The CE input of the lead (or only) SPROM is driven by the DONE output of the lead FPGA device, provided that DONE is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum. FPGA Master Serial Mode Summary The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an external memory. The Xilinx SPROMs have been designed for compatibility with the Master Serial mode. Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA mode-select pins are Low (M0=0, M1=0, M2=0). Data is read from the SPROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during configuration. Master Serial Mode provides a simple configuration interface. Only a serial data line and two control lines are required to configure an FPGA. Data from the SPROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK. 8-15 8 R XC1700E Family of Serial Configuration PROMs If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. Xilinx FPGAs take care of this automatically with an on-chip default pull-up resistor. Programming the FPGA With Counters Unchanged Upon Completion When multiple FPGA-configurations for a single FPGA are stored in a SPROM, the OE pin should be tied Low. Upon power-up, the internal address counters are reset and configuration begins with the first program stored in memory. Since the OE pin is held Low, the address counters are left unchanged after configuration is complete. Therefore, to reprogram the FPGA with another program, the DONE line is pulled Low and configuration begins at the last value of the address counters. This method fails if a user applies RESET during the FPGA configuration process. The FPGA aborts the configuration and then restarts a new configuration, as intended, but the SPROM does not reset its address counter, since it never saw a High level on its OE input. The new configuration, therefore, reads the remaining data in the PROM and interprets it as preamble, length count etc. Since the FPGA is 8-16 the master, it issues the necessary number of CCLK pulses, up to 16 million (224) and DONE goes High. However, the FPGA configuration will be completely wrong, with potential contentions inside the FPGA and on its output pins. This method must, therefore, never be used when there is any chance of external reset during configuration. Cascading Serial Configuration PROMs For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded SPROMs provide additional memory. After the last bit from the first SPROM is read, the next clock signal to the SPROM asserts its CEO output Low and disables its DATA line. The second SPROM recognizes the Low level on its CE input and enables its DATA output. See Figure 2. After configuration is complete, the address counters of all cascaded SPROMs are reset if the FPGA RESET pin goes Low, assuming the SPROM reset polarity option has been inverted. To reprogram the FPGA with another program, the DONE line goes Low and configuration begins where the address counters had stopped. In this case, avoid contention between DATA and the configured I/O use of DIN. December 7, 1998 (Version 1.4) R XC1700E Family of Serial Configuration PROMs Vcc OPTIONAL Daisy-chained FPGAs with Different Configurations DOUT FPGA OPTIONAL Slave FPGAs with Identical Configurations MODES Vcc RESET RESET DIN CCLK DONE INIT VCC DATA CLK VPP Cascaded Serial CE Memory OE/RESET CLK SPROM CE DATA CEO OE/RESET (Low Resets the Address Pointer) CCLK (OUTPUT) 8 DIN DOUT (OUTPUT) X8256_01 Figure 2: Master Serial Mode. The one-time-programmable SPROM supports automatic loading of configuration programs. Multiple devices can be cascaded to support additional FPGAs. An early DONE inhibits the SPROM data output one CCLK cycle before the FPGA I/Os become active. December 7, 1998 (Version 1.4) 8-17 R XC1700E Family of Serial Configuration PROMs Standby Mode Programming The SPROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high impedance state regardless of the state of the OE input. The devices can be programmed on programmers supplied by Xilinx or qualified third-party vendors. The user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice can permanently damage the device. Table 1: Truth Table for XC1700 Control Inputs Control Inputs RESET Inactive CE Low Active Inactive Active Low High High Internal Address if address < TC: increment if address > TC: don't change Held reset Not changing Held reset Outputs DATA active 3-state 3-state 3-state 3-state CEO High Low High High High Icc active reduced active standby standby Notes: 1. The XC1700 RESET input has programmable polarity 2. TC = Terminal Count = highest address value. TC+1 = address 0. Important: Always tie the VPP pin to VCC in your application. Never leave VPP floating. 8-18 December 7, 1998 (Version 1.4) R XC1700E Family of Serial Configuration PROMs XC1736E, XC1765E, XC17128E and XC17256E Absolute Maximum Ratings Symbol Description Units VCC Supply voltage relative to GND -0.5 to +7.0 V VPP Supply voltage relative to GND -0.5 to +12.5 V VIN Input voltage relative to GND -0.5 to VCC +0.5 V VTS Voltage applied to 3-state output -0.5 to VCC +0.5 V TSTG Storage temperature (ambient) -65 to +150 C TSOL Maximum soldering temperature (10 s @ 1/16 in.) +260 C Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions Symbol VCC Note: Description Min Max Units Commercial Supply voltage relative to GND (TA = 0C to +70C) 4.75 5.25 V Industrial Supply voltage relative to GND (TA = -40C to +85C) 4.50 5.50 V During normal read operation VPP must be connected to VCC DC Characteristics Over Operating Condition Symbol Description 8 Min Max Units VIH High-level input voltage 2.0 VCC V VIL Low-level input voltage 0 0.8 V VOH High-level output voltage (IOH = -4 mA) VOL Low-level output voltage (IOL = +4 mA) VOH High-level output voltage (IOH = -4 mA) VOL Low-level output voltage (IOL = +4 mA) 0.37 V ICCA Supply current, active mode (at maximum frequency) 10.0 mA ICCS Supply current, standby mode 50.0 A IL Input or output leakage current 10.0 A CIN Input Capacitance (VIN = GND, f = 1.0MHz) 10.0 pF COUT Output Capacitance (VIN = GND, f = 1.0MHz) 10.0 pF December 7, 1998 (Version 1.4) 3.86 V Commercial 0.32 3.76 V V Industrial -10.0 8-19 R XC1700E Family of Serial Configuration PROMs XC1765EL, XC17128EL and XC17256EL Absolute Maximum Ratings Symbol Description Units VCC Supply voltage relative to GND -0.5 to +4.0 V VPP Supply voltage relative to GND -0.5 to +12.5 V VIN Input voltage with respect to GND -0.5 to VCC +0.5 V VTS Voltage applied to 3-state output -0.5 to VCC +0.5 V TSTG Storage temperature (ambient) -65 to +150 C TSOL Maximum soldering temperature (10 s @ 1/16 in.) +260 C Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions Symbol VCC Note: Description Min Max Units Commercial Supply voltage relative to GND (TA = 0C to +70C) 3.0 3.6 V Industrial Supply voltage relative to GND (TA = -40C to +85C ) 3.0 3.6 V During normal read operation VPP must be connected to VCC DC Characteristics Over Operating Condition Symbol Description Min Max Units VIH High-level input voltage 2.0 VCC V VIL Low-level input voltage 0 0.8 V VOH High-level output voltage (IOH = -3 mA) VOL Low-level output voltage (IOL = +3 mA) 0.4 V ICCA Supply current, active mode (at maximum frequency) 5.0 mA ICCS Supply current, standby mode 50.0 A IL Input or output leakage current 10.0 A CIN Input Capacitance (VIN = GND, f = 1.0MHz) 10.0 pF COUT Output Capacitance (VIN = GND, f = 1.0MHz) 10.0 pF 8-20 2.4 -10.0 V December 7, 1998 (Version 1.4) R XC1700E Family of Serial Configuration PROMs AC Characteristics Over Operating Condition CE 9 9 TSCE TSCE 10 THCE RESET/OE 11 THOE TLC 8 THC 6 TCYC 7 CLK TOE 2 3 TCAC 1 4 TOH 5 TDF TCE DATA 4 TOH X2634 Symbol Description XC1736E XC1765E Min Max XC1765EL XC17128E XC17256E XC17128EL XC17256EL Min Min Min Max Max Units Max 1 TOE OE to Data Delay 45 45 25 30 ns 2 TCE CE to Data Delay 60 60 45 45 ns 3 TCAC CLK to Data Delay 80 200 45 45 ns 4 TOH Data Hold From CE, OE, or CLK3 5 TDF CE or OE to Data Float Delay2 & 3 6 TCYC Clock Periods 7 TLC CLK Low Time3 3 0 0 50 0 50 0 50 ns 50 ns 100 400 67 67 ns 50 100 20 25 ns 8 THC CLK High Time 50 100 20 25 ns 9 TSCE CE Setup Time to CLK (to guarantee proper counting) 25 40 20 25 ns 10 THCE CE Hold Time to CLK (to guarantee proper counting) 0 0 0 0 ns 11 THOE OE Hold Time (guarantees counters are reset) 100 100 20 25 ns Notes: 1. AC test load = 50 pF 2. Float delays are measured with 5 pF AC loads. Transition is measured at +/- 200mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V. December 7, 1998 (Version 1.4) 8-21 8 R XC1700E Family of Serial Configuration PROMs AC Characteristics Over Operating Condition When Cascading RESET/OE CE CLK 12 TCDF Last Bit DATA First Bit 13 TOCK 15 TOOE CEO 14 TOCE 14 TOCE X3183 Symbol Description Min Max Units 12 TCDF CLK to Data Float Delay2, 3 50 ns 13 TOCK CLK to CEO Delay3 30 ns 35 ns 30 ns 3 14 TOCE CE to CEO Delay 15 TOOE RESET/OE to CEO Delay3 Notes: 1. AC test load = 50 pF 2. Float delays are measured with 5 pF AC loads. Transition is measured at +/- 200mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V. 8-22 December 7, 1998 (Version 1.4) R XC1700E Family of Serial Configuration PROMs Ordering Information XC17256E VO8 C Device Number Operating Range/Processing XC1736E XC1765E XC1765EL XC17128E XC17128EL XC17256E XC17256EL C = Commercial (TA = 0C to +70C) I = Industrial (TA = -40C to +85C) Package Type PD8 SO8 VO8 PC20 = = = = 8-Pin Plastic DIP 8-Pin Plastic Small-Outline Package 8-Pin Plastic Small-Outline Thin Package 20-Pin Plastic Leaded Chip Carrier Valid Ordering Combinations XC17128EPD8C XC17128EVO8C XC17128EPC20C XC17128EPD8I XC17128EVO8I XC17128EPC20I XC17256EPD8C XC17256EVO8C XC17256EPC20C XC17256EPD8I XC17256EVO8I XC17256EPC20I XC17128ELPD8C XC17128ELVO8C XC17128ELPC20C XC17128ELPD8I XC17128ELVO8I XC17128ELPC20I XC17256ELPD8C XC17256ELVO8C XC17256ELPC20C XC17256ELPD8I XC17256ELVO8I XC17256ELPC20I XC1736EPD8C XC1736ESO8C XC1736EVO8C XC1736EPC20C XC1736EPD8I XC1736ESO8I XC1736EVO8I XC1736EPC20I XC1765EPD8C XC1765ESO8C XC1765EVO8C XC1765EPC20C XC1765EPD8I XC1765ESO8I XC1765EVO8I XC1765EPC20I XC1701PD8C XC1701PC20C XC1701SO20C XC1701PD8I XC1701PC20I XC1701SO20I XC1702LVQ44C XC1702LPC44C XC1704LVQ44C XC1704LPC44C XC1702LVQ44I XC1702LPC44I XC1704LVQ44I XC1704LPC44I XC1765ELPD8C XC1765ELSO8C XC1765ELVO8C XC1765ELPC20C XC1765ELPD8I XC1765ELSO8I XC1765ELVO8I XC1765ELPC20I XC1701LPD8C XC1701LPC20C XC1701LSO20C XC1701LPD8I XC1701LPC20I XC1701LSO20I XQ1701LCC44M XQ1701LCC44B XQ1701LS020N XC17512LPD8C XC17512LPC20C XC17512LSO20C XC17512LPD8I XC17512LPC20I XC17512LSO20I Note: The XC1701, XC1701L, XQ1701L, XC1702L, XC1704L and XC17512L products are specified in the XC1700L High Density datasheet. Marking Information Due to the small size of the serial PROM package, the complete ordering part number cannot be marked on the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows. 17256E V C Device Number XC1736E XC1765E XC1765X XC17128E XC17128X XC17256E XC17256X Operating Range/Processing Package Type P S V J = = = = C = Commercial (TA = 0C to +70C) I = Industrial (TA = -40C to +85C) 8-Pin Plastic DIP 8-Pin Plastic Small-Outline Package 8-Pin Plastic Small-Outline Thin Package 20-Pin Plastic Leaded Chip Carrier Note: When marking the device number on the EL parts, an X is used in place of an EL. December 7, 1998 (Version 1.4) 8-23 8 R XC1700E Family of Serial Configuration PROMs Revision Control Date 7/14/98 9/8/98 9/30/98 12/7/98 8-24 Revision Revised ICCS on page 19 and page 20; revised VCC specifications for TA on page 19 and page 20; revised VCC on page 19; revised Note 2 on page 20 and page 21; added TA to operating range specifications on page 23. Revised the references to FPGAs to include the XC4000XLA and XC4000XV families. Updated the Valid Ordering Combinations onpage 23 to include high density products. Updated the references to compatible FPGAs to include the Virtex family. December 7, 1998 (Version 1.4)