XC1701LPC20I0280 - Xilinx, Inc.

December 7, 1998 (Version 1.4) 8-13

Features

• Serial Conﬁguration one-time programmable (OTP)

read-only memory designed to store conﬁguration

bitstreams of Xilinx FPGA devices

• Simple interface to the FPGA requires only one user

I/O pin

• Cascadable for storing longer or multiple bitstreams

• Programmab le reset polarity (active High or activ e Low)

for compatibility with different FPGA solutions

• The XC17128E/EL and XC17256E/EL devices support

the XC4000EX/XL/XLA/XV fast conﬁguration mode

(15.0 MHz)

• Low-power CMOS ﬂoating gate process

• Available in 5 V and 3.3 V versions

• A vailab le in compact plastic 8-pin DIP, 8-pin SOIC , 8-pin

VOIC, or 20-pin PLCC packages.

• Programming support by leading programmer

manufacturers.

• Design support using the Xilinx Alliance and

Foundation series software packages.

Description

The XC1700 family of serial conﬁguration PROMs

(SPROMs) provides an easy-to-use, cost-effective method

for storing Xilinx FPGA conﬁguration bitstreams.

When the FPGA is in Master Serial mode, it generates a

conﬁguration clock that drives the SPROM. A short access

time after the rising clock edge, data appears on the

SPROM DATA output pin that is connected to the FPGA

DIN pin. The FPGA generates the appropriate number of

clock pulses to complete the conﬁguration. Once conﬁg-

ured, it disables the SPROM. When the FPGA is in Slave

Serial mode, the SPROM and the FPGA must both be

clocked by an incoming signal.

Multiple devices can be concatenated by using the CEO

output to drive the CE input of the following device. The

clock inputs and the DATA outputs of all SPROMs in this

chain are interconnected. All devices are compatible and

can be cascaded with other members of the family.

For device programming, either the Xilinx Alliance or the

Foundation series development systems compiles the

FPGA design ﬁle into a standard HEX format which is then

transferred to most commercial PROM programmers.

XC1700E Family of

Serial Conﬁguration PROMs

December 7, 1998 (Version 1.4) 08*

Product Specification

Figure 1: Simpliﬁed Block Diagram (does not show programming circuit)

EPROM

Cell

Matrix

Address Counter

RESET/

OE or

OE/

RESET

DATA

CEO

Output

CLK

VCC VPP GND

X3185

XC1700E Family of Serial Conﬁguration PROMs

8-14 December 7, 1998 (Version 1.4)

Pin Description

DATA

Data output, 3-stated when either CE or OE are inactive.

During programming, the D ATA pin is I/O. Note that OE can

be programmed to be either active High or active Low.

CLK

Each rising edge on the CLK input increments the inter nal

address counter, if both CE and OE are active.

RESET/OE

When High, this input holds the address counter reset and

3-states the DATA output. The polarity of this input pin is

programmable as either RESET/OE or OE/RESET. To

avoid confusion, this document describes the pin as

RESET/OE, although the opposite polarity is possible on all

devices. When RESET is active, the address counter is

held at zero, and the DATA output is 3-stated. The polar ity

of this input is programmable. The default is active High

RESET, but the preferred option is active Low RESET,

because it can be driven by the FPGA’s INIT pin.

The polarity of this pin is controlled in the programmer inter-

face. This input pin is easily inverted using the Xilinx

HW-130 programmer software. Third-party programmers

have different methods to invert this pin.

When High, this pin disables the internal address counter,

3-states the D ATA output, and forces the de vice into low-ICC

standby mode.

CEO

Chip Enable output, to be connected to the CE input of the

next SPROM in the daisy chain. This output is Low when

the CE and OE inputs are both active AND the internal

address counter has been incremented bey ond its Terminal

Count (TC) value. In other words: when the PROM has

been read, CEO will follow CE as long as OE is active.

When OE goes inactive , CEO sta ys High until the PR OM is

reset. Note that OE can be programmed to be either active

High or active Low.

VPP

Programming voltage. No overshoot above the speciﬁed

max voltage is permitted on this pin. F or normal read oper-

ation, this pin

must

be connected to VCC. Failure to do so

may lead to unpredictable, temperature-dependent opera-

tion and se v ere problems in circuit deb ugging.

Do not leav e

VPP ﬂoating!

VCC and GND

VCC is positive supply pin and GND is ground pin.

Serial PROM Pinouts

Capacity

Pin Name 8-Pin 20-Pin

DATA 1 2

CLK 2 4

RESET/OE (OE/RESET) 3 6

CE 4 8

GND 5 10

CEO 6 14

VPP 717

VCC 820

Device Conﬁguration Bits

XC1736E 36,288

XC1765E or EL 65,536

XC17128E or EL 131,072

XC17256E or EL 262,144

XC17512L 524,288

XC1701, XC1701L or XQ1701L 1,048,576

XC1702L 2,097,152

XC1704L 4,194,304

Note: The XC17512L and larger SPROMs are speciﬁed in a sep-

arate datasheet.

December 7, 1998 (Version 1.4) 8-15

XC1700E Family of Serial Conﬁguration PROMs

Number of Conﬁguration Bits, Including Header

for Xilinx FPGAs and Compatible SPROMs

Note: 1. The suggested SPROM is determined by compatibility with

the higher conﬁguration frequency of the Xilinx FPGA

CCLK. Designers using the default slow conﬁguration

frequency (CCLK) can use the XC1765E or XC1765EL for

the noted FPGA devices.

2. The XC1701, XC1701L, XC1702L, XC1704L & XC17512L

are speciﬁed in a separate XC1700L High Density

datasheet.

Controlling Serial PROMs

Connecting the FPGA device with the SPROM.

• The DATA output(s) of the SPROM(s) drives the DIN

input of the lead FPGA device.

• The Master FPGA CCLK output drives the CLK input(s)

of the SPROM(s).

• The CEO output of a SPROM driv es the CE input of the

next SPROM in a daisy chain (if any).

• The RESET/OE input of all SPROMs is best driven by

the INIT output of the lead FPGA device. This

connection assures that the SPROM address counter is

reset before the start of any (re)conﬁguration, even

when a reconﬁguration is initiated b y a VCC glitch. Other

methods – such as driving RESET/OE from LDC or

system reset – assume the SPROM internal

power-on-reset is always in step with the FPGA’s

internal power-on-reset. This may not be a safe

assumption.

• The SPROM CE input can be driven from either the

LDC or DONE pins. Using LDC avoids potential

contention on the DIN pin.

• The CE input of the lead (or only) SPROM is driven by

the DONE output of the lead FPGA device, provided

that DONE is not permanently grounded. Otherwise,

LDC can be used to drive CE, but must then be

unconditionally High during user operation. CE can also

be permanently tied Low, but this keeps the DATA

output active and causes an unnecessary supply

current of 10 mA maximum.

FPGA Master Serial Mode Summary

The I/O and logic functions of the Conﬁgurab le Logic Block

(CLB) and their associated interconnections are estab-

lished by a conﬁguration program. The program is loaded

either automatically upon power up, or on command,

depending on the state of the three FPGA mode pins. In

Master Serial mode, the FPGA automatically loads the con-

ﬁguration program from an external memory. The Xilinx

SPROMs have been designed for compatibility with the

Master Serial mode.

Upon power-up or reconﬁguration, an FPGA enters the

Master Serial mode whenever all three of the FPGA

mode-select pins are Low (M0=0, M1=0, M2=0). Data is

read from the SPROM sequentially on a single data line.

Synchronization is provided by the rising edge of the tem-

porary signal CCLK, which is generated during conﬁgura-

tion.

Master Serial Mode provides a simple conﬁguration inter-

face. Only a serial data line and two control lines are

required to conﬁgure an FPGA. Data from the SPROM is

read sequentially, accessed via the internal address and bit

counters which are incremented on every valid rising edge

of CCLK.

Device Conﬁguration Bits SPROM

XC4003E 53,984 XC17128E1

XC4005E 95,008 XC17128E

XC4006E 119,840 XC17128E

XC4008E 147,552 XC17256E

XC4010E 178,144 XC17256E

XC4013E 247,968 XC17256E

XC4020E 329,312 XC1701

XC4025E 422,176 XC1701

XC4002XL 61,100 XC17128EL1

XC4005XL 151,960 XC17256EL

XC4010XL 283,424 XC17512L

XC4013XL/XLA 393,632 XC17512L

XC4020XL/XLA 521,880 XC17512L

XC4028XL/XLA 668,184 XC1701L

XC4028EX 668,184 XC1701

XC4036EX/XL/XLA 832,528 XC1701L

XC4036EX 832,528 XC1701

XC4044XL/XLA 1,014,928 XC1701L

XC4052XL/XLA 1,215,368 XC1702L

XC4062XL/XLA 1,433,864 XC1702L

XC4085XL/XLA 1,924,992 XC1702L

XC40110XV 2,686,136 XC1704L

XC40150XV 3,373,448 XC1704L

XC40200XV 4,551,056 XC1704L +

XC17512L

XC40250XV 5,433,888 XC1704L+

XC1702L

XC5202 42,416 XC1765E

XC5204 70,704 XC17128E

XC5206 106,288 XC17128E

XC5210 165,488 XC17256E

XC5215 237,744 XC17256E

XCV50 559,232 XC1701L

XCV100 781,248 XC1701L

XCV150 1,041,128 XC1701L

XCV200 1,335,872 XC1702L

XCV300 1,751,840 XC1702L

XCV400 2,546,080 XC1704L

XCV600 3,608,000 XC1704L

XCV800 4,715,648 XC1704L +

XC1701L

XCV1000 6,127,776 XC1704L +

XC1702L

XC1700E Family of Serial Conﬁguration PROMs

8-16 December 7, 1998 (Version 1.4)

If the user-programmable, dual-function DIN pin on the

FPGA is used only for conﬁguration, it must still be held at

a deﬁned level during normal operation. Xilinx FPGAs take

care of this automatically with an on-chip default pull-up

resistor.

Programming the FPGA With Counters

Unchanged Upon Completion

When multiple FPGA-conﬁgurations for a single FPGA are

stored in a SPROM, the OE pin should be tied Low. Upon

power-up, the internal address counters are reset and con-

ﬁguration begins with the ﬁrst program stored in memory.

Since the OE pin is held Low, the address counters are left

unchanged after conﬁguration is complete. Therefore, to

reprogram the FPGA with another prog ram, the DONE line

is pulled Low and conﬁguration begins at the last value of

the address counters.

This method f ails if a user applies RESET during the FPGA

conﬁguration process. The FPGA aborts the conﬁguration

and then restarts a new conﬁguration, as intended, but the

SPROM does not reset its address counter, since it never

saw a High level on its OE input. The new conﬁguration,

theref ore, reads the remaining data in the PROM and inter-

prets it as preamble, length count etc. Since the FPGA is

the master, it issues the necessary number of CCLK

pulses, up to 16 million (224) and DONE goes High. How-

e ver , the FPGA conﬁgur ation will be completely wrong, with

potential contentions inside the FPGA and on its output

pins. This method must, therefore, never be used when

there is any chance of external reset during conﬁguration.

Cascading Serial Conﬁguration PROMs

For multiple FPGAs conﬁgured as a daisy-chain, or for

future FPGAs requiring larger conﬁguration memories, cas-

caded SPROMs provide additional memory. After the last

bit from the ﬁrst SPROM is read, the ne xt cloc k signal to the

SPROM asserts its CEO output Low and disables its DATA

line. The second SPROM recognizes the Low level on its

CE input and enables its DATA output. See Figure 2.

After conﬁguration is complete, the address counters of all

cascaded SPROMs are reset if the FPGA RESET pin goes

Low, assuming the SPROM reset polarity option has been

inverted.

To reprogram the FPGA with another program, the DONE

line goes Low and conﬁguration begins where the address

counters had stopped. In this case, avoid contention

between DATA and the conﬁgured I/O use of DIN.

December 7, 1998 (Version 1.4) 8-17

XC1700E Family of Serial Conﬁguration PROMs

RESET

DIN

CCLK

INIT

DONE SPROM

DATA

CEO

CLK

OPTIONAL

Slave FPGAs

with Identical

Configurations

Vcc

FPGA

(Low Resets the Address Pointer)

Vcc

VCC VPP

RESET

X8256_01

Cascaded

Serial

Memory

DATA

CLK

OPTIONAL

Daisy-chained

FPGAs with

Different

Configurations

CCLK

(OUTPUT)

DIN

DOUT

(OUTPUT)

OE/RESET OE/RESET

OUT

MODES

Figure 2: Master Serial Mode. The one-time-programmable SPROM supports automatic loading of conﬁguration

programs . Multiple de vices can be cascaded to support additional FPGAs. An early DONE inhibits the SPROM data output

one CCLK cycle before the FPGA I/Os become active.

XC1700E Family of Serial Conﬁguration PROMs

8-18 December 7, 1998 (Version 1.4)

Standby Mode

The SPROM enters a low-power standby mode whenever

CE is asser ted High. The output remains in a high imped-

ance state regardless of the state of the OE input.

Programming

The de vices can be programmed on programmers supplied

by Xilinx or qualiﬁed third-party vendors. The user must

ensure that the appropriate programming algorithm and the

latest version of the programmer software are used. The

wrong choice can permanently damage the device.

Notes: 1. The XC1700 RESET input has programmable polarity

2. TC = Terminal Count = highest address value. TC+1 = address 0.

Important: Always tie the VPP pin to VCC in your application. Never leave VPP ﬂoating.

Table 1: Truth Table for XC1700 Control Inputs

Control Inputs Internal Address Outputs

RESET CE DATA CEO Icc

Inactive Low if address < TC: increment

if address > TC: don’t change active

3-state High

Low active

reduced

Active Low Held reset 3-state High active

Inactive High Not changing 3-state High standby

Active High Held reset 3-state High standby

December 7, 1998 (Version 1.4) 8-19

XC1700E Family of Serial Conﬁguration PROMs

XC1736E, XC1765E, XC17128E and XC17256E

Absolute Maximum Ratings

Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under

Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may

affect device reliability.

Operating Conditions

Note: During normal read operation VPP

must

be connected to VCC

DC Characteristics Over Operating Condition

Symbol Description Units

VCC Supply voltage relative to GND -0.5 to +7.0 V

VPP Supply voltage relative to GND -0.5 to +12.5 V

VIN Input voltage relative to GND -0.5 to VCC +0.5 V

VTS Voltage applied to 3-state output -0.5 to VCC +0.5 V

TSTG Storage temperature (ambient) -65 to +150 °C

TSOL Maximum soldering temperature (10 s @ 1/16 in.) +260 °C

Symbol Description Min Max Units

VCC Commercial Supply voltage relative to GND (TA = 0°C to +70°C) 4.75 5.25 V

Industrial Supply voltage relative to GND (TA = -40°C to +85°C) 4.50 5.50 V

Symbol Description Min Max Units

VIH High-level input voltage 2.0 VCC V

VIL Low-level input voltage 0 0.8 V

VOH High-level output voltage (IOH = -4 mA) Commercial 3.86 V

VOL Low-level output voltage (IOL = +4 mA) 0.32 V

VOH High-level output voltage (IOH = -4 mA) Industrial 3.76 V

VOL Low-level output voltage (IOL = +4 mA) 0.37 V

ICCA Supply current, active mode (at maximum frequency) 10.0 mA

ICCS Supply current, standby mode 50.0 µA

ILInput or output leakage current -10.0 10.0 µA

CIN Input Capacitance (VIN = GND, f = 1.0MHz) 10.0 pF

COUT Output Capacitance (VIN = GND, f = 1.0MHz) 10.0 pF

XC1700E Family of Serial Conﬁguration PROMs

8-20 December 7, 1998 (Version 1.4)

XC1765EL, XC17128EL and XC17256EL

Absolute Maximum Ratings

Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating

Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device

reliability.

Operating Conditions

Note: During normal read operation VPP

must

be connected to VCC

DC Characteristics Over Operating Condition

Symbol Description Units

VCC Supply voltage relative to GND -0.5 to +4.0 V

VPP Supply voltage relative to GND -0.5 to +12.5 V

VIN Input voltage with respect to GND -0.5 to VCC +0.5 V

VTS Voltage applied to 3-state output -0.5 to VCC +0.5 V

TSTG Storage temperature (ambient) -65 to +150 °C

TSOL Maximum soldering temperature (10 s @ 1/16 in.) +260 °C

Symbol Description Min Max Units

VCC Commercial Supply voltage relative to GND (TA = 0°C to +70°C) 3.0 3.6 V

Industrial Supply voltage relative to GND (TA = -40°C to +85°C ) 3.0 3.6 V

Symbol Description Min Max Units

VIH High-level input voltage 2.0 VCC V

VIL Low-level input voltage 0 0.8 V

VOH High-level output voltage (IOH = -3 mA) 2.4 V

VOL Low-level output voltage (IOL = +3 mA) 0.4 V

ICCA Supply current, active mode (at maximum frequency) 5.0 mA

ICCS Supply current, standby mode 50.0 µA

ILInput or output leakage current -10.0 10.0 µA

CIN Input Capacitance (VIN = GND, f = 1.0MHz) 10.0 pF

COUT Output Capacitance (VIN = GND, f = 1.0MHz) 10.0 pF

December 7, 1998 (Version 1.4) 8-21

XC1700E Family of Serial Conﬁguration PROMs

AC Characteristics Over Operating Condition

Notes: 1. AC test load = 50 pF

2. Float delays are measured with 5 pF AC loads. Transition is measured at +/- 200mV from steady state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V.

RESET/OE

CLK

DATA

TCE

TOE

TLC

9 TSCE TSCE THCE

THOE

TCAC TOH TDF

TOH

910

THC

X2634

TCYC

Symbol Description XC1736E

XC1765E XC1765EL XC17128E

XC17256E XC17128EL

XC17256EL Units

Min Max Min Max Min Max Min Max

OE OE to Data Delay 45 45 25 30 ns

CE CE to Data Delay 60 60 45 45 ns

CAC CLK to Data Delay 80 200 45 45 ns

OH Data Hold From CE, OE, or CLK30000ns

DF CE or OE to Data Float Delay2 & 3 50 50 50 50 ns

CYC Clock Periods 100 400 67 67 ns

LC CLK Low Time350 100 20 25 ns

8 THC CLK High Time350 100 20 25 ns

9 TSCE CE Setup Time to CLK (to guarantee

proper counting) 25 40 20 25 ns

10 THCE CE Hold Time to CLK (to guarantee

proper counting) 0000ns

11 THOE OE Hold Time (guarantees counters

are reset) 100 100 20 25 ns

XC1700E Family of Serial Conﬁguration PROMs

8-22 December 7, 1998 (Version 1.4)

AC Characteristics Over Operating Condition When Cascading

Notes: 1. AC test load = 50 pF

2. Float delays are measured with 5 pF AC loads. Transition is measured at +/- 200mV from steady state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V.

Symbol Description Min Max Units

12 TCDF CLK to Data Float Delay2, 3 50 ns

13 TOCK CLK to CEO Delay330 ns

14 TOCE CE to CEO Delay335 ns

15 TOOE RESET/OE to CEO Delay330 ns

RESET/OE

CLK

DATA

15 TOOE

CEO

First Bit Last Bit

TOCE

13 TOCK

12 TCDF

X3183

TOCE

December 7, 1998 (Version 1.4) 8-23

XC1700E Family of Serial Conﬁguration PROMs

Ordering Information

Valid Ordering Combinations

Note: The XC1701, XC1701L, XQ1701L, XC1702L, XC1704L and XC17512L products are speciﬁed in the XC1700L High Density

datasheet.

Marking Information

Due to the small size of the serial PROM package, the complete ordering par t number cannot be marked on the package.

The XC preﬁx is deleted and the package code is simpliﬁed. Device marking is as follows.

Note: When marking the device number on the EL parts, an X is used in place of an EL.

XC17128EPD8C XC17256EPD8C XC1736EPD8C XC1765EPD8C XC1701PD8C XC1702LVQ44C

XC17128EVO8C XC17256EVO8C XC1736ESO8C XC1765ESO8C XC1701PC20C XC1702LPC44C

XC17128EPC20C XC17256EPC20C XC1736EVO8C XC1765EVO8C XC1701SO20C XC1704LVQ44C

XC17128EPD8I XC17256EPD8I XC1736EPC20C XC1765EPC20C XC1701PD8I XC1704LPC44C

XC17128EVO8I XC17256EVO8I XC1736EPD8I XC1765EPD8I XC1701PC20I XC1702LVQ44I

XC17128EPC20I XC17256EPC20I XC1736ESO8I XC1765ESO8I XC1701SO20I XC1702LPC44I

XC1736EVO8I XC1765EVO8I XC1704LVQ44I

XC1736EPC20I XC1765EPC20I XC1704LPC44I

XC17128ELPD8C XC17256ELPD8C XC1765ELPD8C XC1701LPD8C XC17512LPD8C

XC17128ELVO8C XC17256ELVO8C XC1765ELSO8C XC1701LPC20C XC17512LPC20C

XC17128ELPC20C XC17256ELPC20C XC1765ELVO8C XC1701LSO20C XC17512LSO20C

XC17128ELPD8I XC17256ELPD8I XC1765ELPC20C XC1701LPD8I XC17512LPD8I

XC17128ELVO8I XC17256ELVO8I XC1765ELPD8I XC1701LPC20I XC17512LPC20I

XC17128ELPC20I XC17256ELPC20I XC1765ELSO8I XC1701LSO20I XC17512LSO20I

XC1765ELVO8I XQ1701LCC44M

XC1765ELPC20I XQ1701LCC44B

XQ1701LS020N

XC17256E VO8 C

Operating Range/Processing

C = Commercial (TA = 0°C to +70°C)

I = Industrial (TA = –40°C to +85°C)

Package Type

PD8 = 8-Pin Plastic DIP

SO8 = 8-Pin Plastic Small-Outline Package

VO8 = 8-Pin Plastic Small-Outline Thin Package

PC20 = 20-Pin Plastic Leaded Chip Carrier

Device Number

XC1736E

XC1765E

XC1765EL

XC17128E

XC17128EL

XC17256E

XC17256EL

17256E V C

Operating Range/Processing

C = Commercial (TA = 0°C to +70°C)

I = Industrial (TA = –40°C to +85°C)

Package Type

P = 8-Pin Plastic DIP

S = 8-Pin Plastic Small-Outline Package

V = 8-Pin Plastic Small-Outline Thin Package

J = 20-Pin Plastic Leaded Chip Carrier

Device Number

XC1736E

XC1765E

XC1765X

XC17128E

XC17128X

XC17256E

XC17256X

R
XC1700E Family of Serial Conﬁguration PROMs
8-24 December 7, 1998 (Version 1.4)
Revision Control
Date Revision
7/14/98 Revised ICCS on page 19 and page 20; revised VCC specifications for TA on page 19 and page 20; re-
vised VCC on page 19; revised Note 2 on page 20 and page 21; added TA to operating range specifica-
tions on page 23.
9/8/98 Revised the references to FPGAs to include the XC4000XLA and XC4000XV families.
9/30/98 Updated the Valid Ordering Combinations onpage 23 to include high density products.
12/7/98 Updated the references to compatible FPGAs to include the Virtex family.