[AK4430]
MS1196-E-01 2011/03
- 1 -
AK4430
192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output
GENERAL DESCRIPTION
The AK4430 is 3.3V 24-bit stereo DAC with an integrated 2Vrms output buffer. A charge pump in the
buffer develops an internal negative power supply rail that enables a ground-referenced 2Vrms output.
Using AKM’s multi bit modulator architecture, the AK4430 delivers a wide dynamic range while preserving
linearity for improved THD+N performance. The AK4430 integrates a combination of switched-capacitor
and continuous-time filters, increasing performance for systems with excessive clock jitter. The 24-bit
word length and 192kHz sampling rate make this part ideal for a wide range of consumer audio
applications, such as portable A/V players, set-top boxes, and digital televisions. The AK4430 is offered in
a space saving 16pin TSSOP package.
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz
128 times Oversampling (Normal Speed Mode)
64 times Oversampling (Double Speed Mode)
32 times Oversampling (Quad Speed Mode)
24-Bit 8 times FIR Digital Filter
Switched-Capacitor Filter with High Tolerance to Clock Jitter
Single Ended 2Vrms Output Buffer
Soft mute
I/F format: 24-bit MSB justified, I2S
Master clock: 512fs, 768fs or 1152fs (Normal Speed Mode)
256fs or 384fs (Double Speed Mode)
128fs or 192fs (Quad Speed Mode)
THD+N: -91dB
Dynamic Range: 104dB
Automatic Power-on Reset Circuit
Power supply: +3.0 ∼ +3.6V
Ta = -20 to 85°C
Small Package: 16pin TSSOP (6.4mm x 5.0mm)
LRCK
BICK
SDTI
Audio
Data
Interface
MCLK
ΔΣ
Modulator AOUTL
8X
Interpolator
SCF
LPF
AOUTR
VDD
VSS1
Control
Interface
Clock
Divider
ΔΣ
8X
Interpolator SCF
LPF
Charge
Pump
CP CN VEE VSS2 CVDD
1μ 1μ
VREFH
SMUTE
DIF
Modulator
2.2μ
[AK4430]
■ Ordering Guide
AK4430ET -20 ∼ +85°C 16pin TSSOP (0.65mm pitch)
AKD4430 Evaluation Board for AK4430
■ Pin Layout
6
5
4
3
2
1 CN
CP
MCLK
SMUTE
BICK
SDTI
7
DIF 8
VEE
VSS2
CVDD
VREFH
VSS1
VDD
AOUTL
AOUTR
AK4430
Top
View
11
12
13
14
15
16
10
9
LRCK
■ Compatibility with the AK4420, AK4424, AK4421 and AK4421A
AK4420 AK4424 AK4421 AK4421A AK4430
Power Supply +4.5 ∼ +5.5V +4.5 ∼ +5.5V +3.0 ∼ +3.6V +3.0 ∼ +3.6V +3.0 ∼ +3.6V
Digital de-emphasis - X - - -
I/F format 24-bit MSB/I²S I²S 24-bit MSB/I²S 24-bit MSB/I²S 24-bit MSB/I²S
Pin out Pin#3 SMUTE DEM SMUTE SMUTE SMUTE
Pin#8 DIF SMUTE DIF DIF* DIF*
Pin#13 DZF DZF DZF DZF VREFH
THD+N -92dB -92dB -92dB (-3dBFS) -92dB -91dB
DR 105dB 105dB 102dB 102dB 104dB
Operating
Temperature
ET: -20 ∼ +85°C
VT: -40 ∼ +85°C ET: -20 ∼ +85°C ET: -20 ∼ +85°C ET: -20 ∼ +85°C ET: -20 ∼ +85°C
(-: Not available, X: Available)
*: Internal pull up (100kΩ)
MS1196-E-01 2011/03
- 2 -
[AK4430]
PIN/FUNCTION
No. Pin Name I/O Function
1 CN I
Negative Charge Pump Capacitor Terminal Pin
Connect to CP with a 1.0μF low ESR (Equivalent Series Resistance) capacitor
over temperature. When this capacitor is polarized, the positive polarity pin
should be connected to the CP pin. Non-polarized capacitors can also be
used.
2 CP I
Positive Charge Pump Capacitor Terminal Pin
Connect to CN with a 1.0μF low ESR (Equivalent Series Resistance)
capacitor over temperature. When this capacitor is polarized, the positive
polarity pin should be connected to the CP pin. Non-polarized capacitors can
also be used.
3 SMUTE I Soft Mute Enable Pin (Internal pull down: 100kΩ)
“H”: Enable, “L”: Disable
4 MCLK I Master Clock Input Pin
5 BICK I Audio Serial Data Clock Pin
6 SDTI I Audio Serial Data Input Pin
7 LRCK I L/R Clock Pin
8 DIF I Audio Data Interface Format Pin (Internal pull up: 100kΩ)
“L”: 24-bit MSB Justified, “H”: I2S,
9 AOUTR O Right channel Analog Output Pin
When MCLK or LRCK or BICK stops, outputs VSS(0V, typ).
10 AOUTL O Left channel Analog Output Pin
When MCLK or LRCK or BICK stops, outputs VSS(0V, typ).
11 VDD - Power Supply Pin, 3.0V∼3.6V
12 VSS1 - Ground Pin 1
13 VREFH O Reference Output Pin
Connect to VSS with a 2.2μF low ESR capacitor over all temperature.
14 CVDD - Charge Pump Power Supply Pin
15 VSS2 - Ground Pin 2
16 VEE O
Negative Voltage Output Pin
Connect to VSS2 with a 1.0μF low ESR capacitor over temperature. When
this capacitor is polarized, the positive polarity pin should be connected to
the VSS2 pin. Non-polarized capacitors can also be used.
Note: All input pins except for the CN, CP, SMUTE and DIF pins should not be left floating.
MS1196-E-01 2011/03
- 3 -
[AK4430]
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=0V; Note 1)
Parameter Symbol min max Units
Power Supply VDD
CVDD
-0.3
-0.3
+4.0
+4.0
V
V
Input Current (any pins except for supplies) IIN - ±10 mA
Input Voltage (Note 3) VIND -0.3 VDD+0.3 V
Ambient Operating Temperature Ta -20 85 °C
Storage Temperature Tstg -65 150 °C
Note 1. All voltages with respect to ground.
Note 2. VSS1, VSS2 connect to the same analog ground.
Note 3. SMUTE, MCLK, BICK, LRCK, SDTI and DIF pins
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=0V; Note 1)
Parameter Symbol min typ max Units
Power Supply
VDD
CVDD
+3.0
+3.3
VDD
+3.6
V
Note 4. CVDD should be equal to VDD.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS1196-E-01 2011/03
- 4 -
[AK4430]
ANALOG CHARACTERISTICS
(Ta = 25°C; VDD=CVDD = +3.3V; fs = 44.1 kHz; BICK = 64fs; Signal Frequency = 1 kHz;
24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥5kΩ, unless otherwise specified)
Parameter min typ max Units
Resolution 24 Bits
Dynamic Characteristics (Note 5)
fs=44.1kHz, BW=20kHz - -91 -82 dB
fs=96kHz, BW=40kHz - -91 - dB
THD+N
fs=192kHz, BW=40kHz - -89 - dB
Dynamic Range (-60dBFS with A-weighted, Note 6) 96 104 - dB
S/N (A-weighted, Note 7) 96 104 - dB
Interchannel Isolation (1kHz) 90 104 - dB
Interchannel Gain Mismatch - 0.2 0.5 dB
PSRR (Note 9) 62 dB
DC Accuracy
DC Offset (at output pin) -5 0 +5 mV
Gain Drift - 100 -
ppm/°C
Output Voltage (Note 8) 1.85 2.0 2.15 Vrms
Load Capacitance (Note 10) - - 25 pF
Load Resistance 5 - - kΩ
Power Supplies
Power Supply Current: (Note 11)
Normal Operation (fs≤96kHz)
Normal Operation (fs=192kHz)
Power-Down Mode (Note 12)
20
22
10
28
31
100
mA
mA
μA
Note 5. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
Note 6. 98dB for 16-bit input data
Note 7. S/N does not depend on input data length.
Note 8. Full-scale voltage (0dB). Output voltage is proportional to the voltage of VDD
AOUT (typ.@0dB) = 2Vrms × VDD/3.3.
Note 9. PSRR is applied to VDD and CVDD with 1kHz, 50mVpp.
Note 10. In case of driving capacitive load, inset a resistor between the output pin and the capacitive load.
Note 11. The current into VDD and CVDD.
Note 12. All digital inputs including clock pins (MCLK, BICK and LRCK) are fixed to VSS or VDD.
MS1196-E-01 2011/03
- 5 -
[AK4430]
FILTER CHARACTERISTICS
(Ta = 25°C; VDD=CVDD = +3.0 ∼ +3.6V; fs = 44.1 kHz)
Parameter Symbol min typ max Units
Digital filter
Passband ±0.05dB (Note 13)
-6.0dB
PB 0
-
22.05
20.0
-
kHz
kHz
Stopband (Note 13) SB 24.1 kHz
Passband Ripple PR ± 0.01 dB
Stopband Attenuation SA 64 dB
Group Delay (Note 14) GD - 24 - 1/fs
De-emphasis Filter
Digital Filter + LPF
Frequency Response(1kHz reference)
fs=44.1kHz, 20Hz ~ 20.0kHz
fs=96kHz, 20Hz ~ 40.0kHz
fs=192kHz, 20Hz ~ 80.0kHz
FR
FR
FR
-
-
-
± 0.05
± 0.05
± 0.05
-
-
-
dB
dB
dB
Note 13. The passband and stopband frequencies scale with fs (system sampling rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
Note 14. Calculated delay time caused by the digital filter. This time is measured from setting the 16/24bit data
of both channels to input register to the output of the analog signal.
DC CHARACTERISTICS
(Ta = 25°C; VDD=CVDD = +3.0 ∼ +3.6V)
Parameter Symbol min typ max Units
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
70%VDD
-
-
-
-
30%VDD
V
V
Input Leakage Current (Note 15) Iin - -
± 10 μA
Note 15. The SMUTE pin and DIF pin are not included. The SMUTE pin has an internal pull-down resistor (typ.100kΩ)
and the DIF pin has an internal pull-up resistor (typ. 100kΩ).
MS1196-E-01 2011/03
- 6 -
[AK4430]
SWITCHING CHARACTERISTICS
(Ta = 25°C; VDD=CVDD = +3.0 ∼ +3.6V)
Parameter Symbol min typ max Units
Master Clock Frequency
Duty Cycle
fCLK
dCLK
4.096
40
- 36.864
60
MHz
%
LRCK Frequency
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
fsn
fsd
fsq
Duty
8
32
120
45
48
96
192
55
kHz
kHz
kHz
%
Audio Interface Timing
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge (Note 16)
LRCK Edge to BICK “↑” (Note 16)
SDTI Hold Time
SDTI Setup Time
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fsn
1/64fsd
1/64fsq
30
30
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 16. BICK rising edge must not occur at the same time as LRCK edge.
MS1196-E-01 2011/03
- 7 -
[AK4430]
■ Timing Diagram
1/fCLK
tCLKL
VIH
tCLKH
MCLK VIL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK VIL
tBCK
tBCKL
VIH
tBCKH
BICK VIL
Figure 1. Clock Timing
tLRB
LRCK
VIH
BICK VIL
tSDS
VIH
SDTI VIL
tSDH
VIH
VIL
tBLR
Figure 2. Serial Interface Timing
MS1196-E-01 2011/03
- 8 -
[AK4430]
OPERATION OVERVIEW
■ System Clock
The external clocks required to operate the AK4430 are MCLK, LRCK, and BICK. The master clock (MCLK) should be
synchronized with LRCK, but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. Sampling speed and MCLK frequency are detected automatically, and then the internal master
clock is set to the appropriate frequency (Table 1).
The AK4430 is automatically placed in power saving mode when MCLK, LRCK and BICK stop during normal operation
mode, and the analog output goes to 0V(typ). When MCLK, LRCK and BICK are input again, the AK4430 is powered
up. After exiting reset following power-up, the AK4430 is not fully operational until MCLK, LRCK and BICK are input.
LRCK MCLK (MHz)
fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs
Sampling
Speed
32.0kHz - - - - 16.3840 24.5760 36.8640
44.1kHz - - - - 22.5792 33.8688 -
48.0kHz - - - - 24.5760 36.8640 -
Normal
32.0kHz 8.192 12.288
44.1kHz 11.2896 16.9344
48.0kHz 12.288 18.432
88.2kHz - - 22.5792 33.8688 - - -
96.0kHz - - 24.5760 36.8640 - - -
Double
176.4kHz 22.5792 33.8688 - - - - - Quad
192.0kHz 24.5760 36.8640 - - - - -
Table 1. System Clock Example
When MCLK= 256fs/384fs, the Auto Setting Mode supports sampling rate of 32kHz~96kHz (Table 1). However, when
the sampling rate is 32kHz~48kHz, DR and S/N will degrade as compared to when MCLK= 512fs/768fs (Table 2).
MCLK DR,S/N
256fs/384fs 101dB
512fs/768fs 104dB
Table 2. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)
■ Audio Serial Interface Format
The audio data is shifted in via the SDTI pin using the BICK and LRCK inputs. The AK4430 supports two formats as
shown in Table 3. The serial data is MSB-first, two’s complement format and it is latched on the rising edge of BICK. It
can be used for 16/20 bit I2S formats by zeroing the unused LSBs.
Mode DIF pin SDTI Format BICK Figure
0 L
24bit MSB justified ≥48fs Figure 3
1 H 24bit I2S Figure 4
≥48fs
Table 3. Audio Data Format
MS1196-E-01 2011/03
- 9 -
[AK4430]
LRCK
BICK
(
64fs
)
SDTI
0221 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 1 0 Don’t care23
Lch Data Rch Data
23 30 2222423 30
22 1 0 Don’t care
23 2223
Figure 3. Mode 0 Timing
LRCK
BICK
(
64fs
)
SDTI
031 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 10Don’t care
23
Lch Data Rch Data
23 25 322423 25
22 1 0Don’t care23 23
Figure 4. Mode 1 Timing
■ Analog Output Block
The internal negative power supply generation circuit (Figure 5) provides a negative power supply for the internal 2Vrms
amplifier. It allows the AK4430 to output an audio signal centered at VSS (0V, typ) as shown in Figure 6. The negative
power generation circuit (Figure 5) needs 1.0uF capacitors (Ca, Cb) with low ESR (Equivalent Series Resistance). If this
capacitor is polarized, the positive polarity pin should be connected to the CP and VSS2 pins. This circuit operates by
clocks generated from MCLK. When MCLK stops, the AK4430 is placed in reset mode automatically and the analog
outputs settle to VSS (0V, typ).
CVDD Charge
Pump
CP CN VSS2 VEE
1uF
1uF
Negative Power
A
K4
4
30
(+) Cb
Ca (+)
Figure 5. Negative Power Generation Circuit
MS1196-E-01 2011/03
- 10 -
[AK4430]
A
OUTR
A
K4430
(
AOUTL
)
0V 2Vrms
Figure 6. Audio Signal Output
■ Soft Mute Operation
Soft mute operation is performed in the digital domain. When the SMUTE pin is set “H”, the output signal is attenuated to
-∞ in 1024 LRCK cycles. When the SMUTE pin is returned to “L”, the mute is cancelled and the output attenuation
gradually changes to 0dB in 1024 LRCK cycles. If the soft mute is cancelled within the 1024 LRCK cycles after starting
this operation, the attenuation is discontinued and it is returned to 0dB by the same cycle. Soft mute is effective for
changing the signal source without stopping the signal transmission. In one cycle of LRCK, eight “H” pulses or more
must not be input to the SMUTE pin.
SMUTE pin
A ttenuation
1024/fs
0dB
-∞
AOUT
1024/fs
GD GD
(1)
(2)
(3)
Notes:
(1) The time for input data attenuation to -∞ is :
Normal Speed Mode: 1024 LRCK cycles (1024/fs).
Double Speed Mode: 2048 LRCK cycles (2048/fs).
Quad Speed Mode : 4096 LRCK cycles (4096/fs).
(2) The analog output corresponding to a specific digital input has a group delay, GD.
(3) If soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to 0dB in the same cycle.
Figure 7. Soft Mute Function
MS1196-E-01 2011/03
- 11 -
[AK4430]
■ System Reset
The AK4430 is in power down mode upon power-up. The MLCK should be input after the power supplies are ramped up.
The AK4430 is in power-down mode until LRCK are input.
D/A Out
(Analog)
MCLK
20 us
Low
Power Supply
(VDD, CVDD)
2, 3
LRCK
Digital
Circuit
Analog
Circuit
Charge Pump
Circuit
Charge Pump
Counter circuit
Time A
(1)
(2)
(3)
Power-up
Power-up
“0” data
D/A In
(
Di
g
ital
)
MUTE
(
D/A Out
)
(4)
(5)
Power down
Power down
Power-up Power down
Notes:
(1) Approximately 20us after a MCLK input is detected, the internal analog circuit is powered-up.
(2) The digital circuit is powered-up after 2 or 3 LRCK cycles following the detection of MCLK.
(3) The charge pump counter starts after the charge pump circuit is powered-up. The DAC outputs a valid analog signal
after Time A.
Time A =176/fs: Normal speed mode
Time A =352/fs: Double speed mode
Time A =704/fs: Quad speed mode
(4) No audible click noise occurs under normal conditions.
(5) The power supply must be powered-up when the MCLK pin is “L”. MCLK must be input after 20us when the power
supply voltage achieves 80% of VDD. If not, click noise may occur at different time from this figure.
Figure 8. System Reset Diagram
MS1196-E-01 2011/03
- 12 -
[AK4430]
■ Reset Function
When the MCLK or LRCK or BICK stops, the AK4430 is placed in reset mode and its analog outputs are set to VSS (0V,
typ). When the MCLK and LRCK, BICK are restarted, the AK4430 returns to normal operation mode.
Normal Operation
Internal
State Reset Normal Operation
D/A Ou t
(Analog)
D/A In
(Digital)
Cl ock In
MCLK, BICK, LRCK
(2)
VSS
(3)
MCLK or BICK or LRCK
Stop
(4) (4)
(1)
Notes:
(1) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK, LRCK or BICK is stopped).
(2) Digital data can be stopped. The click noise after MCLK, LRCK and BICK are input again can be reduced by
inputting the “0” data during this period.
(3) Digital data is muted for about 180/fs (in Normal speed mode) from the timing when a clock starts, and then the
analog data is output after GD.
(4) No audible click noise occurs under normal conditions.
Figure 9. Reset Timing Example
MS1196-E-01 2011/03
- 13 -
[AK4430]
SYSTEM DESIGN
Figure 10 shows the system connection diagram. An evaluation board (AKD4430) is available for fast evaluation as well
as suggestions for peripheral circuitry.
Analog
3.3V
24bit Audio Data
1u (1)
64fs
Master Clock
Analog Ground
Digital Ground
Mode-
Setting
AK4430
DIF
SDTI
BICK
MCLK
SMUTE
CP
CN
LRCK
AOUTR
AOUTL
VDD
VSS1
VREFH
CVDD
VSS2
VEE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
+
fs
1u (1)
0.1u 10u
+
0.1u 10u
Lch Out
Rch Out
+
2.2u (1)
+
Figure 10. Typical Connection Diagram
Note:
(1) Use low ESR (Equivalent Series Resistance) capacitors. When using polarized capacitors, the positive polarity
pin should be connected to the CP, VSS2 and VREFH pins.
(2) VSS1 and VSS2 should be separated from digital system ground.
(3) Digital input pins should not be allowed to float.
MS1196-E-01 2011/03
- 14 -
[AK4430]
1. Grounding and Power Supply Decoupling
VDD and CVDD are supplied from the analog supply and should be separated from the system digital supply. Decoupling
capacitors, especially 0.1μF ceramic capacitors for high frequency bypass, should be placed as near to VDD and CVDD
as possible. The VSS1 and VSS2 must be connected to the same analog ground plane. Power-up sequence between
VDD and CVDD is not critical.
2. Analog Outputs
The analog outputs are single-ended and centered at the VSS (ground) voltage. The output signal range is typically
2.0Vrms (typ @VDD=3.3V). The internal switched-capacitor filter (SCF) and continuous-time filter (CTF) attenuate the
noise generated by the delta-sigma modulator beyond the audio passband. Using single a 1st-order LPF (Figure 11) can
reduce noise beyond the audio passband.
The output voltage is a positive full scale for 7FFFFFH (@24bit data) and a negative full scale for 800000H (@24bit
data). The ideal output is 0V (VSS) voltage for 000000H (@24bit data). The DC offset is ±5mV or less.
AOUT 470
2.2nF
AK4430
2.0V rm s (typ)
Analog
Out
(fc = 154kHz, gain = -0.28dB @ 40kHz, gain = -1.04dB @ 80kHz)
Figure 11. External 1st order LPF Circuit Example
MS1196-E-01 2011/03
- 15 -
[AK4430]
PACKAGE
0-10°
Detail A
Seating Plane
0.10
0.17±0.05
0.22±0.1 0.65
*5.0±0.1 1.1 (max )
A
1 8
9 16
16pin TSSOP (Unit: mm)
*4.4±0.1
6.4±0.2
0.5±0.2
0.1±0.1
NOTE: Dimension "*" does not include mold flash.
0.13 M
■ Package & Lead frame material
Package molding compound: Epoxy, Halogen (bromine and chlorine) free
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
MS1196-E-01 2011/03
- 16 -
[AK4430]
MARKING
AKM
4430ET
XXYYY
1) Pin #1 indication
2) Date Code : XXYYY (5 digits)
XX: Lot#
YYY: Date Code
3) Marketing Code : 4430ET
4) Asahi Kasei Logo
Date (YY/MM/DD)
REVISION HISTORY
Revision Reason Page Contents
10/05/31 00 First Edition
11/03/01 01 Error Correction 15 1. Grounding and Power Supply Decoupling
The description was changed.
MS1196-E-01 2011/03
- 17 -
[AK4430]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
MS1196-E-01 2011/03
- 18 -
