1/4 inch 330k pixel Primary color filter
CMOS Image Sensor with A/D converter
TCM5043G
Technical data sheet
(Tentative Ver. 1.2)
January 22nd, 2001
TOSHIBA Corporation
Semiconductor Company, System LSI Division
Marketing & Engineering Group
Digital Consumer System LSI & Image Sensor
Feature
Item Contents
Optical format 1/4 inch
Total pixel numbers 698(H) x 502(V) (350k pixels)
Signal pixel numbers 660(H) x 492(V) (330k pixels)
Pixel pitch 5.4um(H) x 5.4um(V)
Image size 3.564mm(H) x 2.657mm(V)
Aspect ratio 4(H) : 3(V)
Power current consumption 21mA(typ) @30fps
Master clock frequency 24.54545MHz
Signal output Progressive scanning
Color filter array RGB primary color filter
Bayer arrangement(G checked, R/B in line sequence)
Output format 10bit digital and proportional output in parallel
Frame rate 30fps @12.27272MHz data rate
Package 32pin TOG(=Tab on glass)
Additional functions - Variable electronic shutter
Internal synchronization mode (serial command setting):
From 2H to 524H by 1H
From 1V to 16V by 1H
External synchronization mode:
From 1H to 524H and from 1V to 16V by 1H
From 1H to 524H, 1V and 4V combined with camera DSP
TC90A70F
- Variable gain control
- Built-in feed back clamp: Optical black level is fixed to 64LSB
- Synchronization generator is implemented
- Command setting by micro wire
- 2.3 to 3.6V digital input/output is available
Maximum Ratings (Vss=0V)
Characteristics Symbol Rating Unit
Vdvddio -0.5 to 4.4 V Power supply voltage Vavdd, Vdvdd -0.5 to 3.7
Input voltage Vin -0.3 to Vdd +0.3
Input current of protection diode Iin +/- 20 mA
Storage temperature Tstg -30 to 85 Centigrade
Recommended operating conditions (Vss=0V)
Characteristics Symbol Rating Unit
Min Typ Max
Vdvddio 2.3 2.8 3.6
Power supply voltage Vavdd,Vdvdd 2.6 2.8 3.0 V
Input voltage Vin 0 to Vdvddio
Operating temperature Topr -20 to 60 Centigrade
1
Block Diagram
Input of SGMODE controls synchronization mode between external synchronization mode and
internal. In the case of ext. sync. mode, HPA, VRR and ESR pulse should be supplied to sensor. On
the other hand, HD, VD and data clock is generated from sensor on int. sync. In that case electronic
shutter speed is controlled by command setting.
External synchronization mode
Internal synchronization mode
2
COMMAND
DECODER VREF
TG &
SG
10bit
Digital Output
DATA9
〜
DATA0(LSB)
IMAGE
AREA A/D
GCA
CDS
MPU
EN,SCLK,SDATA
HPA,VRR,ESR
SGMODE=L
or
OPEN
COMMAND
DECODER VREF
TG &
SG
10bit
Digital Output
DATA9
〜
DATA0(LSB)
DATACLK
IMAGE
AREA A/D
GCA CDS
MPU
EN,SCLK,SDATA
HD,VD
SGMODE=H
Pixel Arrangement
3
Signal pixels;
492 pixels
Signal pixels; 660 pixels
(*) Light shielded dummy pixels; 6 pixels
Dummy
pixels for
test;
6 pixels
Light shielded
pixels for optical
bralck; 26 pixels
(*) Light
shielded
dummy
pixels;
2 pixels
B
G
G
R
G
R
B
G
G
B
R
G
R
G
G
B
(*) Light shielded dummy pixels; 2 pixels
(*) Light
shielded
dummy
pixels;
2 pixels
(*) Light
shielded
dummy
pixels;
2 pixels
Pin Configuration
Pin No. Symbol Function Pin management
1 DVSS Digital GND (VSS) 0V
2 MCK Master clock input 24.54545 MHz
3 DVDD Digital power supply (VDD)
2.8V +/- 0.2V. Bi-
passed condenser(4.7uF
and 0.1uF) is preferable. Output impedance
of power supply is
recommended to be
under 0.5 ohm @10kHz.
4 SOUT0 Sensor out(LSB)
5 SOUT1 Sensor out
6 SOUT2 Sensor out
7 SOUT3 Sensor out
8 SOUT4 Sensor out
9 SOUT5 Sensor out
10 SOUT6 Sensor out
11 SOUT7 Sensor out
12 SOUT8 Sensor out
13 SOUT9 Sensor out(MSB)
14 DVSSIO Digital I/O GND (VSS) 0V
15 DATACLK Data clock output
(a half of master clock)
16 DVDDIO Digital I/O power supply (VDD) 2.3 to 3.6V. Bi-
passed condenser(2.2uF
and 0.1uF) is preferable.
17 TEST4 Test terminal (pull-up) No connection or connected to VDD
18 DSTOP Read stop control input (pull-up) 1: Active / 0: Halt
19 VRR(VD)
Vertical timing pulse start pulse
input / VD pulse output
20 ESR(STR） Electrical shutter start pulse input
21 HPA(HD)
Horizontal timing start pulse input
/ HD pulse output
22 SGMODE
Internal / external synchronization
mode (pull-down) 0: External sync (HPA,VRR and ESR input)
1: Internal sync (HD,VD output)
23 TEST5 Test terminal Connected to AVSS
24 RESET Reset for parameter setting Connected to DVDDIO via 100k to 1M ohm.
Connected to GND via 0.1uF
25 SCLK Serial clock input
26 SDATA Serial data input
27 EN Data enable input
28 TEST1 Test terminal Connected to
GND(AVSS) via a capacitor
of 2.2uF
29 TEST2 Test terminal
Connected to GND(AVSS) via a capacitor
of 0.1uF
30 AVSS Analog GND (VSS) 0V
31 TEST3 Test terminal No connection
32 AVDD Analog power supply (VDD) 2.8V +/- 0.2V. Bi-
passed condenser(2.2uF
and 0.1uF) is preferable.
*Aluminum electrolytic capacitor or Tantalum capacitor are desirable for power line.
4
Application circuit
5
TEST4
DSTOP
VRR(VD)
ESR(STR)
HPA(HD)
SGMODE
TEST5
TEST2
SDATA
TEST1
TEST3
AVSS
SCLK
AVDD
EN
DATACLK
DVSSIO
(LSB)SOUT0
DVDD
DVSS
DVDDIO
MCK
24
23
22
21
28
27
26
25
20
19
18
17
32
31
30
29
1
2
3
4
16
15
14
12
11
10
9
8
7
6
5
13
SOUT1
SOUT2
SOUT3
SOUT4
SOUT5
SOUT6
SOUT7
SOUT8
(MSB)SOUT9
RESET
C1:4.7uF
C3 C1 C3
C2 C3
C2:2.2uF
C3:0.1uF
C2
C3
R1
DVDDIO
C3
C2
R1:100k to 1Mohm
DVDD
AVDD
DVDDIO
AVSS
Optical and electrical characteristics
Item Symbol
Conditions Min Typ Max Unit
Sensitivity
(G output) R(G) Condition *1 150
(287 LSB)
200
(383 LSB)
- mV
Saturation voltage VSAT 350
(671 LSB)
- - mV
Blooming margin BLM
500 times as standard
condition No blooming
S/N (dark) S/N Standard condition - 57 - dB
Decay lag LAG G output; over 20mV - 3
(6 LSB) 7
(14 LSB) mV
Power current ＩＤＤ Frame rate; 30fps - 21 - mA
- Setting value of internal gain amplifier; once (0dB)
- (***LSB) means 10 bit digital output not include 64LSB for black level.
- Signal output includes 64 LSB for black level.
Standard conditions (Tc=60 degrees Centigrade)
- Driving conditions:
Frame rate; 30fps, Electronics shutter; Off (1/30s), VDD=2.8+/-0.2V
Parameter setting value; Default
- Light source: Color temperature; 3200K, Tangusten light
- Optical filter: IR cut filter (50%; 650nm)
- Optical lens; Fujinon CF25L (F0.85, f=25mm), F2.8
- Standard signal level: G output (average) 250mV
Condition *1
- Luminance of object; 100nt
- Driving and optical conditions are same as standard conditions.
Relation between analog and digital output
- Setting value of internal gain amplifier; once (0dB)
- Assumption of DAC(500mVp-p) with linear gain
Digital output
(10bit)
1023
479
Black level = 64
0
250 500 Analog output [mV]
(standard) (Saturation)
6
DC/AC characteristics
DC characteristics (Vdd=2.8+/-0.2V, Tc=-20 to 60 degrees Centigrade)
Symbol Item Conditions Min Typ Max Unit Note
VIH High level input voltage
2 - - V Note1
VIL Low level input voltage
- - 0.8 V Note1
IIH High level input current VIN=VDD -1 - 1 uA Note1
IIL Low level input current VIN=VSS -1 - 1 uA Note1
VOH High level output voltage IOH=-4mA 2.2 - - V Note2
VOL Low level output voltage IOL= 4mA - - 0.4 V Note2
IDD Current consumption VDD=2.8V - 21 - mA
Note1 DSTOP, VRR, ESR, HPA, SGMODE, RESET, SCLK, SDATA, EN and MCK
Note2 VD, STR, HD, DATACLK, DATA0 to DATA9
AC characteristics (Vdd=2.8+/-0.2V, Tc=-20 to 60 degrees Centigrade)
Item Symbol Conditions Min Typ Max Unit Note
Set-up time for input
ts Based on MCK 10 ns Note1
Hold time for input th Based on MCK 10 ns Note1
Output delay time tpd Based on MCK
(C=15pF) 10 ns Note2
Command clock
frequency fsclk
6 Note3
Note1 DSTOP, VRR, ESR and HPA,
Note2 DATACLK, DATA0 to DATA9
Note3 SCLK
7
ts th
Vdd/2
Vdd/2
tpd
Data
OUT
Data
IN
MCK
40nS
Command setting table
(2) Command setting
Setting item
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Note
Gain setting 0 0 0 0 MSB Setting data(10bit) LSB
Electronic shutter 1 0 1 0 MSB Setting data(10bit) LSB 2H to 16V
Monitoring mode 1 1 1 1 * 0: 30fps(default)
1: 60fps
FBC mode 1 1 1 1 * 0: Auto(default)
1: Manual(OFF)
* Default value setting is available w/o sending command. Gain value should be set after
power on reset.
* In the case of internal synchronization mode, command setting of electronic shutter speed
is available. ESR pulse need to be input on external synchronization mode.
(3) Typical setting value
1) Gain setting table (typical value) Setting value
Gain level (dB) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
-2.4 (Min) 1 1 1 1 1 1 1 1 1 1
0 (Standard) 1 1 0 0 0 0 0 0 0 0
3 1 0 0 0 1 0 0 0 0 0
6 0 1 1 0 0 0 0 0 0 1
9 0 1 0 0 0 1 0 0 0 0
12 0 0 1 1 0 0 0 0 0 1
18 0 0 0 1 1 0 0 0 0 1
20
(Recommended max value) 0 0 0 1 0 0 1 1 0 1
 2) Electronic shutter setting (internal synchronization mode)
Setting value
Electronic shutter
speed (Storage time) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
Shutter Off (525H) 0 0 0 0 0 0 0 0 0 0
2 (H) 0 0 0 0 0 0 0 0 0 1
3 (H) 0 0 0 0 0 0 0 0 1 0
: : : : : : : : : : :
523 (H) 1 0 0 0 0 0 1 0 1 0
524 (H) 1 0 0 0 0 0 1 0 1 1
8
(1) Timing chart
D
0D
1D
2D
3D
4D
5D
6D
7D
8D
9D
1
0
D
1
1
D
1
2
D
1
3
D
1
4
D
1
5
SCLK
SDATA
EN
There is D0 data at 15 data before EN raise
max:1/4MCK (6MHz)
More than 16 SCLK
9
Horizontal period
HPA
MCK
VRR
ESR
4CK
8CK
8CK
Light shielded pixels Invalid periodEffective signal
660 pixels Effective pixels
660 pixels
30 pixels 88 pixels
Output
Signal output format (external sync in normal mode) 1V=525H
Light shielded
dummy pixels
2 pixels
Light shielded
dummy pixels
2 pixels
Light shielded
dummy pixels
2 pixels
Vertical period
2H
SCLK
EN
SDATA
Output
Invalid period Light shielded
dummy period Effective signal
2H 492H
Effective signal
492H 31H
VRR
ESR
(storage time)
524H
523H
522H
521H
520H
519H
518H
517H
516H
515H
514H
513H
512H
511H
510H
509H
508H
507H
506H
505H
504H
503H
502H
501H
500H
499H
498H
497H
496H
495H
494H
1H
2H
3H
4H
5H
6H
7H
8H
9H
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
30H
31H
32H
33H
34H
35H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
494
493
492
491
490
489
662
661
660
659
658
657
656
655
654
653
652
651
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
HPA
Not to coincide with VRR 178.5CK
10
Sgnal output format (external sync in monitoring mode) 1V=263H
Vertical pieoid
2H
SCLK
EN
SDATA
Output
Invalid period Light shielded
dummy period
Effective signal
244H 17H
VRR
ESR
262H
261H
260H
259H
258H
257H
256H
255H
254H
253H
252H
251H
250H
249H
248H
247H
246H
245H
244H
243H
242H
241H
240H
239H
238H
237H
236H
235H
234H
233H
232H
1H
2H
3H
4H
5H
6H
7H
8H
9H
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
30H
31H
32H
33H
34H
35H
492
491
484
488
487
483
480
479
476
475
472
471
Horizontal period
HPA
MCK
VRR
ESR
4CK
8CK
8CK
Light shielded pixels Invalid periodEffective signal
660 pixels
Effective pixels
660 pixels
30 pixels 88 pixels
2 pixels
Output
Light shielded
dummy pixels
2 pixels
Light shielded
dummy pixels
2 pixels
Light shielded
dummy pixels
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
662
661
660
659
658
657
656
655
654
653
652
651
2H
1
2
Effective signal
244H
5
6
9
10
13
14
17
18
21
22
25
26
29
30
33
34
37
38
41
42
45
46
49
HPA
(Storage time)
Not to coincide with VRR
468
467
464
463
231H
50
53
54
57
58
61
36H
460
459
456
178.5CK
11
Horizontal period
HD
MCK
VD
Light shielded pixels Invalid periodEffective pixels
660 pixels
Effective pixels
660 pixels
30 pixels 88 pixels
2 pixels
Output
Signal output format (Internal sync in normal mode) 1V=525H
Light shielded
dummy pixels
2 pixels
Light shielded
dummy pixels
2 pixels
Light shielded
dummy pixels
Vertical period
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
662
661
660
659
658
657
656
655
654
653
652
651
174CK
141CK
39CK
2H
SCLK
EN
SDATA
Output
Invalid periodEffective signal
492H 31H
VD
ESR; N/A
26H4H
HD
Light shielded
dummy period Effective pixels
2H 492H
494
493
492
491
490
489
488
487
486
485
484
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
12
Horizontal period
HD
MCK
VD
Light shielded pixels Invalid periodEffective pixels
660 pixels
Effective pixels
660 pixels
30 pixels 88 pixels
2 pixels
Output
Signal output format (internal sync in monitoring mode) 1V=263H
Light shielded
dummy pixels
2 pixels
Light shielded
dummy pixels
2 pixels
Light shielded
dummy pixels
Vertical period
2H
SCLK
EN
SDATA
Output
Invalid pixelsEffective signal
244H 17H
VD
ESR; N/A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
490
489
486
485
482
481
478
477
474
473
470
469
662
661
660
659
658
657
656
655
654
653
652
651
13H3H
174CK
141CK
39CK
HD
Light shielded
dummy period
466
Effective signal
2H 244H
1
2
5
6
9
10
13
14
17
18
21
22
25
26
29
30
33
34
37
38
41
42
45
46
49
50
53
54
Long storage time mode
1) Setting mode
(1) External sync mode
Intermittent mode by skipping VRR input
Electronic shutter can be set by 1H from 1V to 16V
(2) Internal sync mode Setting value Electronic shutter
speed (storage time) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
Long storage 2V 1 1 0 0 0 0 0 0 0 1
3V 1 1 0 0 0 0 0 0 1 0
: : : : : : : : : : :
15V 1 1 0 0 0 0 1 1 1 0
16V 1 1 0 0 0 0 1 1 1 1
13
Timing diagram for long storage mode
14
Long strorage mode on internal sync mode
Signaloutput
VD
WhenElectricalshutterspeedissetto262H
(assumedasanalogoutput)
1V
2V
3V
4V
5V
6V
10V
11V
12V
13V
14V
15V
16V
16V
1V
Signaloutput
(assumedasanalogoutput)
Signaloutput
(assumedasanalogoutput)
Normalstorageoperation
Longstoragemodefrom2Vto16Vby1V
VD
STR
STR
VD
STR
Example1
Example2
Storagetime=2V
Storagetime=16V
Commandsetting FBC_OFF
Commandsetting FBC_OFF
Long storage mode on external sync mode
Signaloutput
VRR
ESR Storagetime=262H
(assumedasanalogoutput)
VRR
ESR
1V
2V
3V
4V
5V
6V
10V
11V
12V
13V
14V
15V
16V
VRR
ESR
16V
1V
Storagetime=1V+262H
Storagetime=15V+262H
Signaloutput
(assumedasanalogoutput)
Signaloutput
(assumedasanalogoutput)
Normalstorageoperation
Longstoragemodefrom1Vto16Vby1H
Note:ESRcanbesetfrom1Hto524H,orsettoOFF(HI)
Example1
Example2
Commandsetting
Commandsetting
FBC_OFF
FBC_OFF
Package outline
15
IC socket(tentative)
The cover is not available for this socket.
１６