Serial Input, Voltage Output 12-/14-Bit Digital-to-Analog Converters AD5530/AD5531 FUNCTIONAL BLOCK DIAGRAM Pin-compatible 12-, 14-bit digital-to-analog converters Serial input, voltage output Maximum output voltage range of 10 V Data readback 3-wire serial interface Clear function to a user-defined voltage Power-down function Serial data output for daisy-chaining 16-lead TSSOP APPLICATIONS Industrial automation Automatic test equipment Process control General-purpose instrumentation VSS VDD AD5530/AD5531 REFIN R 12-/14-BIT DAC R VOUT R REFAGND R LDAC DUTGND DAC REGISTER RBEN CLR SDIN POWER-DOWN CONTROL LOGIC SHIFT REGISTER GND SCLK SYNC PD SDO 00938-001 FEATURES Figure 1. GENERAL DESCRIPTION The AD5530/AD5531 are single 12- and 14-bit (respectively) serial input, voltage output digital-to-analog converters (DAC). They utilize a versatile 3-wire interface that is compatible with SPI(R), QSPITM, MICROWIRETM, and DSP interface standards. Data is presented to the part in a 16-bit serial word format. Serial data is available on the SDO pin for daisy-chaining purposes. Data readback allows the user to read the contents of the DAC register via the SDO pin. The DAC output is buffered by a gain of two amplifier and referenced to the potential at DUTGND. LDAC can be used to update the output of the DAC asynchronously. A power-down pin (PD) allows the DAC to be put into a low power state, and a CLR pin allows the output to be cleared to a user-defined voltage, the potential at DUTGND. The AD5530/AD5531 are available in 16-lead TSSOP. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved. AD5530/AD5531 TABLE OF CONTENTS Features .............................................................................................. 1 PD Function................................................................................ 13 Applications....................................................................................... 1 Readback Function .................................................................... 13 Functional Block Diagram .............................................................. 1 CLR Function.............................................................................. 13 General Description ......................................................................... 1 Output Voltage............................................................................ 14 Revision History ............................................................................... 2 Bipolar Configuration................................................................ 14 Specifications..................................................................................... 3 Microprocessor Interfacing........................................................... 15 AC Performance Characteristics ................................................ 5 AD5530/AD5531 to ADSP-21xx.............................................. 15 Standalone Timing Characteristics............................................ 5 AD5530/AD5531 to 8051 Interface ......................................... 15 Daisy-Chaining and Readback Timing Characteristics.......... 6 AD5530/AD5531 to MC68HC11 Interface ............................ 15 Absolute Maximum Ratings............................................................ 7 Applications Information .............................................................. 17 ESD Caution.................................................................................. 7 Optocoupler Interface................................................................ 17 Pin Configuration and Function Descriptions............................. 8 Serial Interface to Multiple AD5530s or AD5531s ................ 17 Typical Performance Characteristics ............................................. 9 Terminology .................................................................................... 12 Daisy-Chaining Interface with Multiple AD5530s or AD5531s ...................................................................................... 17 Theory of Operation ...................................................................... 13 Outline Dimensions ....................................................................... 18 DAC Architecture....................................................................... 13 Ordering Guide .......................................................................... 18 Serial Interface ............................................................................ 13 REVISION HISTORY 1/07--Rev. A to Rev. B Updated Format..................................................................Universal Changes to Figure 28...................................................................... 17 3/06--Rev. 0 to Rev. A Change to Table 3 ............................................................................. 5 Change to Figure 4 ........................................................................... 8 Change to Output Voltage Section............................................... 14 Change to Ordering Guide............................................................ 18 5/02--Revision 0: Initial Version Rev. B | Page 2 of 20 AD5530/AD5531 SPECIFICATIONS VDD = 15 V 10%; VSS = -15 V 10%; GND = 0 V; RL = 5 k and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter 1 ACCURACY Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Error Gain Error Gain Temperature Coefficient 2 REFERENCE INPUTS2 Reference Input Range DC Input Resistance Input Current DUTGND INPUT2 DC Input Impedance Max Input Current Input Range O/P CHARACTERISTICS2 Output Voltage Swing Short-Circuit Current Resistive Load Capacitive Load DC Output Impedance DIGITAL I/O VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance2 SDO VOL, Output Low Voltage POWER REQUIREMENTS VDD/VSS Power Supply Sensitivity Full Scale/VDD Full Scale/VSS IDD ISS IDD in Power-Down 1 2 AD5530 AD5531 Unit 12 1 1 2 2 1 0.5 10 14 2 1 8 8 4 0.5 10 Bits LSB max LSB max LSB max LSB max LSB typ ppm FSR/C typ ppm FSR/C max 0 to 5 100 1 0 to 5 100 1 V min to V max M typ A max Per input, typically 20 nA 60 0.3 -4 to +4 60 0.3 -4 to +4 k typ mA typ V min to V max Max output range 10 V 10 15 5 1200 0.5 10 15 5 1200 0.5 V max mA max k min pF max max 2.4 0.8 10 10 0.4 2.4 0.8 10 10 0.4 V min V max A max pF max V max Total for all pins 3 pF typical ISINK = 1 mA +15/-15 +15/-15 V nom 10% for specified performance 110 100 2 2 150 110 100 2 2 150 dB typ dB typ mA max mA max A max Outputs unloaded Outputs unloaded Typically 50 A Temperature range for B Version: -40C to +85C. Guaranteed by design, not subject to production test. Rev. B | Page 3 of 20 Test Conditions/Comments Guaranteed monotonic over temperature Typically within 1 LSB Typically within 1 LSB Max output range 10 V To 0 V To 0 V AD5530/AD5531 VDD = 12 V 10%; VSS = -12 V 10%; GND = 0 V; RL = 5 k and CL = 220 pF to GND; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 ACCURACY Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Error Gain Error Gain Temperature Coefficient 2 REFERENCE INPUTS2 Reference Input Range DC Input Resistance Input Current DUTGND INPUT2 DC Input Impedance Max Input Current Input Range O/P CHARACTERISTICS2 Output Voltage Swing Short-Circuit Current Resistive Load Capacitive Load DC Output Impedance DIGITAL I/O VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance2 SDO VOL, Output Low Voltage POWER REQUIREMENTS VDD/VSS Power Supply Sensitivity Full Scale/VDD Full Scale/VSS IDD ISS IDD in Power-Down 1 2 AD5530 AD5531 Unit 12 1 1 2 2 1 0.5 10 14 2 1 8 8 4 0.5 10 Bits LSB max LSB max LSB max LSB max LSB typ ppm FSR/C typ ppm FSR/C max 0 to 4.096 100 1 0 to 4.096 100 1 V min to V max M typ A max Per input, typically 20 nA 60 0.3 -3 to +3 60 0.3 -3 to +3 k typ mA typ V min to V max Max output range 8.192 V 8.192 15 5 1200 0.5 8.192 15 5 1200 0.5 V max mA max k min pF max max 2.4 0.8 10 10 0.4 2.4 0.8 10 10 0.4 V min V max A max pF max V max Total for all pins 3 pF typical ISINK = 1 mA +12/-12 +12/-12 V nom 10% for specified performance 110 100 2 2 150 110 100 2 2 150 dB typ dB typ mA max mA max A max Outputs unloaded Outputs unloaded Typically 50 A Temperature range for B Version: -40C to +85C. Guaranteed by design, not subject to production test. Rev. B | Page 4 of 20 Test Conditions/Comments Guaranteed monotonic over temperature Typically within 1 LSB Typically within 1 LSB Max output range 8.192 V To 0 V To 0 V AD5530/AD5531 AC PERFORMANCE CHARACTERISTICS VDD = 10.8 V to 16.5 V, VSS = -10.8 V to -16.5 V; GND = 0 V; RL = 5 k and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time B Version Unit Test Conditions/Comments 20 s typ Full-scale change to 1/2 LSB. DAC latch contents alternately loaded with all 0s and all 1s. Slew Rate Digital-to-Analog Glitch Impulse 1.3 120 V/s typ nV-s typ Digital Feedthrough Output Noise Spectral Density @ 1 kHz 0.5 100 nV-s typ nV/Hz typ DAC latch alternately loaded with 0x0FFF and 0x1000. Not dependent on load conditions. Effect of input bus activity on DAC output under test. All 1s loaded to DAC. STANDALONE TIMING CHARACTERISTICS VDD = 10.8 V to 16.5 V, VSS = -10.8 V to -16.5 V; GND = 0 V; RL = 5 k and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter 1, 2 fMAX t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 2 Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Description SCLK frequency SCLK cycle time SCLK low time SCLK high time SYNC to SCLK falling edge setup time SCLK falling edge to SYNC rising edge Min SYNC high time Data setup time Data hold time SYNC high to LDAC low LDAC pulse width LDAC high to SYNC low CLR pulse width Guaranteed by design, not subject to production test. Sample tested during initial release and after any redesign or process change that can affect this parameter. All input signals are measured with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. t1 t3 SCLK t4 SYNC t2 t5 t6 t7 MSB SDIN DB15 DB14 t8 LSB DB11 DB0 t9 LDAC1 t11 t10 t12 CLR 1LDAC 00938-002 1 Limit at TMIN, TMAX 7 140 60 60 50 40 50 40 15 5 50 5 50 CAN BE TIED PERMANENTLY LOW, IF REQUIRED. Figure 2. Timing Diagram for Standalone Mode Rev. B | Page 5 of 20 AD5530/AD5531 DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS VDD = 10.8 V to 16.5 V, VSS = -10.8 V to -16.5 V; GND = 0 V; RL = 5 k and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter 1, 2, 3 fMAX t1 t2 t3 t4 t5 t6 t7 t8 t12 t13 t14 t15 t16 t17 Limit at TMIN, TMAX 2 500 200 200 50 40 50 40 15 50 130 50 50 50 100 Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min ns min ns min Description SCLK frequency SCLK cycle time SCLK low time SCLK high time SYNC to SCLK falling edge setup time SCLK falling edge to SYNC rising edge Min SYNC high time Data setup time Data hold time CLR pulse width SCLK falling edge to SDO valid SCLK falling edge to SDO invalid RBEN to SCLK falling edge setup time RBEN hold time RBEN falling edge to SDO valid 1 Guaranteed by design, not subject to production test. Sample tested during initial release and after any redesign or process change that can affect this parameter. All input signals are measured with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 SDO; RPULLUP = 5 k, CL = 15 pF 2 t1 t3 SCLK t4 t6 t7 MSB SDIN DB15 DB14 t8 DB11 LSB DB0 t13 SDO (DAISYCHAINING) t14 MSB DB15 LSB DB11 DB0 t15 t16 RBEN t13 t17 SDO (READBACK) 0 MSB Figure 3. Timing Diagram for Daisy-Chaining and Readback Mode Rev. B | Page 6 of 20 t14 0 RB13 RB0 LSB 00938-003 SYNC t2 t5 AD5530/AD5531 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 6. Parameter VDD to GND VSS to GND Digital Inputs to GND SDO to GND REFIN to REFAGND REFIN to GND REFAGND to GND DUTGND to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature (TJ MAX) Package Power Dissipation Thermal Impedance JA TSSOP (RU-16) Lead Temperature (Soldering 10 sec) IR Reflow, Peak Temperature (<20 sec) Rating -0.3 V to +17 V +0.3 V to -17 V -0.3 V to VDD + 0.3 V -0.3 V to +6.5 V -0.3 V to +17 V VSS - 0.3 V to VDD + 0.3 V VSS - 0.3 V to VDD + 0.3 V VSS - 0.3 V to VDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION -40C to +85C -65C to +150C 150C (TJ MAX - TA)/JA 150.4C/W 300C 235C Rev. B | Page 7 of 20 AD5530/AD5531 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 16 VDD REFIN 2 15 VOUT LDAC 3 14 DUTGND SDIN 4 13 VSS AD5530/ AD5531 TOP VIEW (Not to Scale) SYNC 5 12 NC RBEN 6 11 GND SCLK 7 10 PD SDO 8 9 CLR NC = NO CONNECT 00938-004 REFAGND Figure 4. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 2 3 Mnemonic REFAGND REFIN LDAC 4 5 6 SDIN SYNC RBEN 7 8 SCLK SDO 9 CLR 10 11 12 13 14 15 16 PD GND NC VSS DUTGND VOUT VDD Description For bipolar 10 V output range, this pin should be tied to 0 V. This is the voltage reference input for the DAC. Connect to external 5 V reference for specified bipolar 10 V output. Load DAC Logic Input (Active Low). When taken low, the contents of the shift register are transferred to the DAC register. LDAC can be tied permanently low, enabling the outputs to be updated on the rising edge of SYNC. Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the falling edge of SCLK. Active Low Control Input. Data is clocked into the shift register on the falling edges of SCLK. Active Low Readback Enable Function. This function allows the contents of the DAC register to be read. Data from the DAC register is shifted out on the SDO pin on each rising edge of SCLK. Clock Input. Data is clocked into the input register on the falling edge of SCLK. Serial Data Out. This pin is used to clock out the serial data previously written to the input shift register or can be used in conjunction with RBEN to read back the data from the DAC register. This is an open drain output; it should be pulled high with an external pull-up resistor. In standalone mode, SDO should be tied to GND or left high impedance. Level Sensitive, Active Low Input. A falling edge of CLR resets VOUT to DUTGND. The contents of the registers are untouched. This allows the DAC to be put into a power-down state. Ground Reference. Do not connect anything to this pin. Negative Analog Supply Voltage. -12 V 10% or -15 V 10%, for specified performance. VOUT is referenced to the voltage applied to this pin. DAC Output. Positive Analog Supply Voltage. 12 V 10% or 15 V 10%, for specified performance. Rev. B | Page 8 of 20 AD5530/AD5531 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.00 VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V TA = 25C 0.8 0.6 VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V TA = 25C 0.75 0.50 0.4 0.25 LSB LSB 0.2 0 -0.2 0 -0.25 -0.4 -0.50 -0.6 0 500 1000 1500 2000 2500 3000 3500 -1.00 4000 00938-008 -1.0 -0.75 00938-005 -0.8 0 2000 4000 6000 CODE Figure 8. AD5531 Typical DNL Plot 2.0 VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V TA = 25C 0.4 0.3 10000 12000 14000 16000 CODE Figure 5. AD5530 Typical INL Plot 0.5 8000 1.5 VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V 1.0 ERROR (LSB) 0.2 LSB 0.1 0 -0.1 0.5 0 -0.5 -0.2 -1.0 -0.3 0 500 1000 1500 2000 2500 3000 3500 -2.0 -40 4000 00938-009 -0.5 -1.5 00938-006 -0.4 -20 0 CODE Figure 6. AD5530 Typical DNL Plot VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V TA = 25C 1.5 0.8 0.6 0 -0.5 80 VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V 0.2 0 -0.2 -0.4 -1.0 -1.5 0 2000 4000 6000 8000 00938-010 -0.6 -0.8 00938-007 LSB 0.5 -2.0 60 0.4 ERROR (LSB) 1.0 40 Figure 9. AD5531 Typical INL Error vs. Temperature 1.0 2.0 20 TEMPERATURE (C) -1.0 -40 10000 12000 14000 16000 -20 0 20 40 60 TEMPERATURE (C) CODE Figure 10. AD5531 Typical DNL Error vs. Temperature Figure 7. AD5531 Typical INL Plot Rev. B | Page 9 of 20 80 AD5530/AD5531 3 0.03 VDD = +15V VSS = -15V REFIN = 0V TA = 25C 2 POSITIVE INL -40C 0.02 IDD (mA) ERROR (LSB) 1 0 NEGATIVE INL +25C +85C 0.01 -1 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 10 6.0 00938-014 -3 2.0 00938-011 -2 11 12 REFIN VOLTAGE (V) 13 14 15 16 17 SUPPLY VOLTAGE (V) Figure 11. AD5531 Typical INL Error vs. Reference Voltage Figure 14. IDD in Power-Down vs. Supply 0 12 VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V -0.5 8 VOUT (V) ERROR (LSB) 4 -1.0 -1.5 0 -4 00938-012 -2.5 -40 -20 0 20 40 60 -12 80 TEMPERATURE (C) 0 5 10 15 20 25 TIME (s) Figure 12. Typical Full-Scale and Offset Error vs. Temperature Figure 15. Settling Time 1.50 0 -0.02 1.45 +85C -0.04 1.40 -0.06 VOUT (V) +25C 1.35 -40C -0.08 -0.10 -0.12 VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V TA = 25C 1.25 1.20 10 11 12 13 14 15 16 17 VDD/VSS (V) -0.14 -0.16 TIME (750ns/DIV) Figure 13. IDD vs. VDD/VSS Figure 16. Typical Digital-to-Analog Glitch Impulse Rev. B | Page 10 of 20 00938-016 1.30 00938-013 CURRENT (mA) VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V TA = 25C -8 00938-015 -2.0 AD5530/AD5531 VOUT VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V TA = 25C PD 2V/DIV 00938-017 2V/DIV Figure 17. Typical Power-Down Time Rev. B | Page 11 of 20 AD5530/AD5531 TERMINOLOGY Relative Accuracy Relative accuracy or endpoint linearity is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Gain Error Gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. It is the deviation in slope of the DAC transfer characteristic from ideal. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. Output Voltage Settling Time This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. Zero-Scale Error Zero-scale error is a measure of the output error when all 0s are loaded to the DAC latch. Full-Scale Error This is the error in DAC output voltage when all 1s are loaded into the DAC latch. Ideally the output voltage, with all 1s loaded into the DAC latch, should be 2 VREF - 1 LSB. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Rev. B | Page 12 of 20 AD5530/AD5531 THEORY OF OPERATION DAC ARCHITECTURE REFIN The AD5530/AD5531 are pin-compatible 12- and 14-bit DACs. The AD5530 consists of a straight 12-bit R-2R voltage mode DAC, and the AD5531 consists of a 14-bit R-2R section. Using a 5 V reference connected to the REFIN pin and REFAGND tied to 0 V, a bipolar 10 V voltage output results. The DAC coding is straight binary. LDAC DAC REGISTER 14 SYNC REGISTER SYNC DB0 (LSB) D6 D5 D4 D3 D2 D1 D0 X X DATA BITS 00938-018 DB15 (MSB) 00938-019 DATA BITS SDO Figure 20. Simplified Serial Interface Data written to the part via SDIN is available on the SDO pin 16 clocks later if the readback function is not used. SDO data is clocked out on the falling edge of the serial clock with some delay. The PD pin allows the user to place the device into power-down mode. While in this mode, power consumption is at a minimum; the device draws only 50 A of current. The PD function does not affect the contents of the DAC register. DB0 (LSB) X X D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-BIT SHIFT REGISTER SDIN PD FUNCTION Figure 18. AD5530 Input Shift Register Contents DB15 (MSB) 14 00938-020 Serial data on the SDIN input is loaded to the input register under the control of SCLK, SYNC, and LDAC. A write operation transfers a 16-bit word to the AD5530/AD5531. Figure 2 and Figure 3 show the timing diagrams. Figure 18 and Figure 19 show the contents of the input shift register. Twelve or 14 bits of the serial word are data bits; the rest are don't cares. OUTPUT 14 SERIAL INTERFACE X X D11 D10 D9 D8 D7 12-/14-BIT DAC Figure 19. AD5531 Input Shift Register Contents The serial word is framed by the signal, SYNC. After a high-tolow transition on SYNC, data is latched into the input shift register on the falling edges of SCLK. There are two ways the DAC register and output can be updated. The LDAC signal is examined on the falling edge of SYNC; depending on its status, either a synchronous or asynchronous update is selected. If LDAC is low, then the DAC register and output are updated on the low-to-high transition of SYNC. Alternatively, if LDAC is high upon sampling, the DAC register is not loaded with the new data on a rising edge of SYNC. The contents of the DAC register and the output voltage are updated by bringing LDAC low any time after the 16-bit data transfer is complete. LDAC can be tied permanently low if required. A simplified diagram of the input loading circuitry is illustrated in Figure 20. READBACK FUNCTION The AD5530/AD5531 allows the data contained in the DAC register to be read back if required. The pins involved are the RBEN and SDO (serial data out). When RBEN is taken low, on the next falling edge of SCLK, the contents of the DAC register are transferred to the shift register. RBEN can be used to frame the readback data by leaving it low for 16 clock cycles, or it can be asserted high after the required hold time. The shift register contains the DAC register data and this is shifted out on the SDO line on each falling edge of SCLK with some delay. This ensures the data on the serial data output pin is valid for the falling edge of the receiving part. The two MSBs of the 16-bit word are 0s. CLR FUNCTION The falling edge of CLR causes VOUT to be reset to the same potential as DUTGND. The contents of the registers remain unchanged, so the user can reload the previous data with LDAC after CLR is asserted high. Alternatively, if LDAC is tied low, the output is loaded with the contents of the DAC register automatically after CLR is brought high. Rev. B | Page 13 of 20 AD5530/AD5531 +15V OUTPUT VOLTAGE The DAC transfer function is as follows: 2 D VOUT = 2 x [2 x ((REFIN - REFAGND) x N ) + 2 x 2 REFAGND - REFIN] - DUTGND 6 REFIN 9 AD586 C1 1F where: 5 R1 10k 4 VOUT AD5530/ AD55311 DUTGND REFAGND D is the decimal data-word loaded to the DAC register. N is the resolution of the DAC. GND VSS SIGNAL GND BIPOLAR CONFIGURATION VOUT (-10V TO +10V) VOUT SIGNAL GND 1ADDITIONAL 00938-021 -15V PINS OMITTED FOR CLARITY. Figure 21. Bipolar 10 V Operation 2 REFIN DAC OUTPUT VOLTAGE Figure 21 shows the AD5530/AD5531 in a bipolar circuit configuration. REFIN is driven by the AD586, 5 V reference, and the REFAGND and DUTGND pins are tied to GND. This results in a bipolar output voltage ranging from -10 V to +10 V. Resistor R1 is provided (if required) for gain adjust. Figure 22 shows the transfer function of the DAC when REFAGND is tied to 0 V. 0V DAC INPUT CODE 000 001 (3)FFF Figure 22. Output Voltage vs. DAC Input Codes (Hex) Rev. B | Page 14 of 20 00938-022 -2 REFIN AD5530/AD5531 MICROPROCESSOR INTERFACING The 8051 provides the LSB of its SBUF register as the first bit in the data stream. The user has to ensure that the data in the SBUF register is arranged correctly because the DAC expects MSB first. For all the interfaces, the DAC output update can be done automatically when all the data is clocked in or asynchronously under the control of LDAC. The contents of the DAC register can be read using the readback function. RBEN is used to frame the readback data, which is clocked out on SDO. Figure 23, Figure 24, and Figure 25 show these DACs interfacing with a simple 4-wire interface. The serial interface of the AD5530/AD5531 can be operated from a minimum of three wires. AD5530/AD5531 TO ADSP-21xx An interface between the AD5530/AD5531 and the ADSP-21xx is shown in Figure 23. In the interface example shown, SPORT0 is used to transfer data to the DAC. The SPORT control register should be configured as follows: internal clock operation, alternate framing mode; active low framing signal. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. As the data is clocked out of the DSP on the rising edge of SCLK, no glue logic is required to interface the DSP to the DAC. In the interface shown, the DAC output is updated using the LDAC pin via the DSP. Alternatively, the LDAC input could be tied permanently low and then the update takes place automatically when TFS is taken high. FO TFS DT SCLK LDAC P3.3 SYNC RxD SDIN TxD SCLK Figure 24. AD5530/AD5531 to 8051 Interface When data is to be transmitted to the DAC, P3.3 is taken low. Data on RxD is clocked out of the microcontroller on the rising edge of TxD and is valid on the falling edge. As a result no glue logic is required between this DAC and microcontroller interface. The 8051 transmits data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. As the DAC expects a 16-bit word, P3.3 must be left low after the first 8 bits are transferred. After the second byte has been transferred, the P3.3 line is taken high. The DAC can be updated using LDAC via P3.4 of the 8051. AD5530/AD5531 TO MC68HC11 INTERFACE Figure 25 shows an example of a serial interface between the AD5530/AD5531 and the MC68HC11 microcontroller. SCK of the MC68HC11 drives the SCLK of the DAC, and the MOSI output drives the serial data lines, SDIN. SYNC is driven from one of the port lines, in this case PC7. MC68HC111 AD5530/ AD55311 LDAC SYNC SDIN SCLK 1ADDITIONAL PINS OMITTED FOR CLARITY. P3.4 1ADDITIONAL PINS OMITTED FOR CLARITY. AD5530/ AD55311 PC6 LDAC PC7 SYNC MOSI SDIN SCK SCLK 1ADDITIONAL PINS OMITTED FOR CLARITY. 00938-023 ADSP-2101/ ADSP-21031 AD5530/ AD55311 00938-024 80C51/80L511 00938-025 Microprocessor interfacing to the AD5530/AD5531 is via a serial bus that uses standard protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5530/AD5531 requires a 16-bit data-word with data valid on the falling edge of SCLK. Figure 25. AD5530/AD5531 to MC68HC11 Interface Figure 23. AD5530/AD5531 to ADSP-21xx Interface AD5530/AD5531 TO 8051 INTERFACE A serial interface between the AD5530/AD5531 and the 8051 is shown in Figure 24. TxD of the 8051 drives SCLK of the AD5530/AD5531, while RxD drives the serial data line, SDIN. P3.3 and P3.4 are bit-programmable pins on the serial port and are used to drive SYNC and LDAC, respectively. The MC68HC11 is configured for master mode, MSTR = 1, CPOL = 0, and CPHA = 1. When data is transferred to the part, PC7 is taken low and data is transmitted MSB first. Data appearing on the MOSI output is valid on the falling edge of SCK. Eight falling clock edges occur in the transmit cycle, so to load the required 16-bit word, PC7 is not brought high until the second 8-bit word has been transferred to the DAC input shift register. Rev. B | Page 15 of 20 AD5530/AD5531 LDAC is controlled by the PC6 port output. The DAC can be updated after each 2-byte transfer by bringing LDAC low. This example does not show other serial lines for the DAC. If CLR were used, it could be controlled by port output PC5. To read data back from the DAC register, the SDO line can be connected to MISO of the MC68HC11, with RBEN tied to another port output controlling and framing the readback data transfer. Rev. B | Page 16 of 20 AD5530/AD5531 APPLICATIONS INFORMATION OPTOCOUPLER INTERFACE In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled. Opto-isolators can provide voltage isolation in excess of 3 kV. The serial loading structure of the AD5530/ AD5531 makes it ideal for opto-isolated interfaces because the number of interface lines is kept to a minimum. Figure 26 shows a 4-channel isolated interface to the AD5530/AD5531. To reduce the number of opto-isolators, if simultaneous updating is not required, then the LDAC pin can be tied permanently low. SERIAL INTERFACE TO MULTIPLE AD5530s OR AD5531s Figure 27 shows how the SYNC pin is used to address multiple AD5530/AD5531s. All devices receive the same serial clock and serial data, but only one device receives the SYNC signal at any one time. The DAC addressed is determined by the decoder. There is some feedthrough from the digital input lines, the effects of which can be minimized by using a burst clock. AD5530/AD55311 SCLK SYNC VCC SDIN SDIN VCC CONTROLLER CONTROL OUT TO LDAC ENABLE SYNC OUT SERIAL CLOCK OUT AD5530/AD55311 EN SYNC DECODER1 TO SYNC CODED ADDRESS VOUT SCLK SDIN DGND VOUT SCLK TO SCLK AD5530/AD55311 1 ADDITIONAL PINS OMITTED FOR CLARITY. SERIAL DATA OUT SYNC TO SDIN SDIN VOUT 00938-026 SCLK OPTOCOUPLER AD5530/AD55311 Figure 26. Opto-Isolated Interface SDIN VOUT SCLK Figure 27. Addressing Multiple AD5530/AD5531s DAISY-CHAINING INTERFACE WITH MULTIPLE AD5530s OR AD5531s A number of these DAC parts can be daisy-chained together using the SDO pin. Figure 28 illustrates such a configuration. VDD R R R AD5530/AD55311 AD5530/AD55311 AD5530/AD55311 SCLK SCLK SCLK SCLK SDIN SDIN SYNC SYNC SDIN SDO SYNC SDIN SYNC SDO TO OTHER SERIAL DEVICES 00938-028 1 ADDITIONAL SDO PINS OMITTED FOR CLARITY. Figure 28. Daisy-Chaining Multiple AD5530/AD5531s Rev. B | Page 17 of 20 00938-027 SYNC AD5530/AD5531 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.65 BSC 0.30 0.19 0.20 0.09 SEATING PLANE COPLANARITY 0.10 0.75 0.60 0.45 8 0 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 29. 16-Lead Thin Shrink Small Outline Package (TSSOP) (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model AD5530BRU AD5530BRU-REEL AD5530BRU-REEL7 AD5530BRUZ 1 AD5530BRUZ-REEL1 AD5530BRUZ-REEL71 AD5531BRU AD5531BRU-REEL AD5531BRU-REEL7 AD5531BRUZ1 AD5531BRUZ-REEL1 AD5531BRUZ-REEL71 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Resolution 12 12 12 12 12 12 14 14 14 14 14 14 INL (LSBs) 1 1 1 1 1 1 2 2 2 2 2 2 Z = Pb-free part. Rev. B | Page 18 of 20 DNL (LSBs) 1 1 1 1 1 1 1 1 1 1 1 1 Package Description 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP Package Option RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 AD5530/AD5531 NOTES Rev. B | Page 19 of 20 AD5530/AD5531 NOTES (c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00938-0-1/07(B) Rev. B | Page 20 of 20