This document is a general product descriptio n and is subject to change wit hout noti ce. Hyni x does no t assume an y respon sibilit y for
use of circuits described. No patent licenses are implied.
Rev 0.5 / Jul. 2007 1
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
512Mb NAND FLASH
HY27US(08/16)12(1/2)B
HY27US0812(1/2)B
HY27US1612(1/2)B
Rev 0.5 / Jul. 2007 2
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Document Title
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory
Revision History
Revision
No. History Draft Date Remark
0.0 Initial Draft. Oct. 19. 2006 Preliminary
0.1 1) Correct Figure 14 & 15 Mar. 07. 2007
0.2
1) Add AC Characteristics
- tRB : Last RE High to busy (at sequential read)
- tCRY : CE High to Ready (in case of interception by CE at read)
- tCEH : CE High Hold Time (at the last serial read)
Mar. 26. 2007
0.3 1) Add sequential row read feature and figure
2) Modify Block Replacement Apr. 27. 2007
0.4
1) Add x16 Characteristics
2) Modify read2 operation (sequential row read)
3) Add AC Characteristics
- tOH : RE or CE High to Output Hold
May. 29. 2007
0.5 1) Correct Read ID Table 16
2) Correct System Interface Using CE don’t care operation
3) Correct Command Set Table 5
Jul. 20. 2007
Rev 0.5 / Jul. 2007 3
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
SUPPLY VOLTAGE
- VCC = 2.7 to 3.6V : HY27US(08/16)12(1/2)B
Memory Cell Array
x8 : (512+16) Bytes x 32 Pages x 4,096 Blocks
x16 : (256+8) Words x 32 Pages x 4,096 Blocks
PAGE SIZE
- x8 device : (512+16) Bytes
: HY27US0812(1/2)B
- x16 device : (256+8) Words
: HY27US1612(1/2)B
BLOCK SIZE
- x8 device: (16K + 512 spare) Bytes
- x16 device: (8K + 256 spare) Words
PAGE READ / PROGRAM
- Random access: 12us (max.)
- Sequential access: 30ns (min.)
- Page program time: 200us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
STATUS REGISTER
ELECTRONIC SIGNATURE
- 1st cycle: Manufacturer Code
- 2nd cycle: Device Code
CHIP ENABLE DON’T CARE
- Simple interface with microcontroller
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions
CE DON’t CARD OPTION ONLY
DATA RETENTION
- 100,000 Program/Erase cycles (with 1bit/512byte ECC)
- 10 years Data Retention
PACKAGE
- HY27US(08/16)12(1/2)B-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27US(08/16)12(1/2)B-T (Lead)
- HY27US(08/16)12(1/2)B-TP (Lead Free)
- HY27US0812(1/2)B-S(P)
: 48-Pin USOP1 (12 x 17 x 0.65 mm)
- HY27US0812(1/2)B-S (Lead)
- HY27US0812(1/2)B-SP (Lead Free)
- HY27US0812(1/2)B-F(P)
: 63-Ball FBGA (9 x 11 x 1.0 mm)
- HY27US0812(1/2)B-F (Lead)
- HY27US0812(1/2)B-FP (Lead Free)
Rev 0.5 / Jul. 2007 4
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
1. SUMMARY DESCRIPTION
The Hynix HY27US(08/16)12(1/2)B series is a 64Mx8bit with spare 2Mx8 bit capacity. The device is offered in 3.3V Vcc
Po wer Supply.
Their NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve v alid data while old data is
erased.
The memory contains 4096 blocks, composed by 32 pages consisting in two NAND structures of 16 series connected Flash
cells.
A progr am oper ation allows to write the 512 -byte (x8 device) or 256- word (x16 device) page in typical 200u s and an erase
operation can be performed in typical 2ms on a 16K-byte (X8 device) block.
Data in the page can be r ead out at 30ns cycle time (3.3V device) per byte. The I/O pins serve as the ports fo r address and
data input/output as well as command input. This int er face allows a reduced pin count and easy migration towards differ-
ent densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where
required, and internal verification and margining of data.
The modify operations can be locked using the WP input pin .
The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple
memories the R/B pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27US(08/16)12(1/2)B extended reliability of 100K pro-
gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
The chip is offered with the CE don’t care function. This option allows the direct download of the code from the NAND Flash
memory device by a microcontroller, since the CE transitions do not stop the read operation.
The copy back function allows the optimization of defective bl ocks man agement: when a page progr am operation fails the
data can be directly programmed in another page inside the same array section without the time consuming serial data
insertion phase.
This device includes also extra features like OTP/Unique ID area, Read ID2 extension.
The HY27US(08/16)12(1/2)B is available in 48 - TSOP1 12 x 20 mm package, 48 - USOP1 12 x 17 mm, FBGA 9 x 11 mm.
1.1 Product List
PART NUMBER ORIZATION VCC RANGE PACKAGE
HY27US0812(1/2)B x8 2.7V - 3.6 Volt 48TSOP1/ 48USOP1/ 63FBGA
HY27US1612(1/2)B x16 48TSOP1
Rev 0.5 / Jul. 2007 5
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
9&&
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Figure1: Logic Diagram
IO15 - IO8 Data Input / Outputs (x16 only)
IO7 - IO0 Data Inputs / Outputs
CLE Command latch enable
ALE Address latch enable
CE Chip Enable
RE Read Enable
WE Write Enable
WP Write Protect
R/B Read y / Bu sy
Vcc Power Supply
Vss Ground
NC No Connection
Table 1: Signal Names
Rev 0.5 / Jul. 2007 6
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 2. 48TSOP1 Contactions, x8 and x16 Device
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Figure 3. 48USOP1 Contactions, x8
Rev 0.5 / Jul. 2007 7
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
1&
1&
1& 1&1&
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Figure 4. 63FBGA Contactions, x8 Device (Top view through package)
Rev 0.5 / Jul. 2007 8
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
1.2 PIN DESCRIPTION
Pin Name Description
IO0-IO7
IO8-IO15(1)
DATA INPUTS/OUTPUTS
The IO pins allow to input command, address and data and to output data during read / program
operations. The inputs are latched on the rising edge of Write Enable (WE).
The I/O buffer float to High-Z when the device is deselected or the outputs are disabled.
CLE COMMAND LATCH ENABLE
This input activates the latching of the IO inputs inside the Command Register on the Rising edge of
Wri te Enable (WE).
ALE ADDRESS LATCH ENABLE
This input activates the latching of the IO inputs inside the Address Register on the Rising edge of
Wri te Enable (WE).
CE CHIP ENABLE
This input cont r ols the sele c tion of the device. When the d evice is busy CE low does not deselect the
memory.
WE WRITE ENABLE
This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise
edge of WE.
RE
READ ENABLE
The RE input is the serial data-out control, and when activ e drives the data onto the I/O bus. Data is
valid tREA after the falling edge of RE which also increments the internal column address counter by
one.
WP WRITE PROTECT
The WP pin, when Low, provides an Har dware pr otection against undesir ed modify (pr ogra m / erase )
operations.
R/B READY BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
VCC SUPPLY VOLTAGE
The VCC supplies the power for all the oper a tions (Read, W rite, Erase).
VSS GROUND
NC NO CONNECTION
Table 2: Pin Description
NOTE:
1. For x16 Version Only
2. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple
the current surges from the power s upply. The PCB track widths must be suf ficient to carry the curr ents required
during program and erase operations.
Rev 0.5 / Jul. 2007 9
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7
1st Cycle A0 A1 A2 A3 A4 A5 A6 A7
2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16
3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24
4th Cycle A25 L(1) L(1) L(1) L(1) L(1) L(1) L(1)
Table 3: Address Cycle Map(x8)
NOTE:
1. L must be set to Low.
2. A8 is set to LOW or High by the 00h or 01h Command.
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8-IO15
1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 L(1)
2nd Cycle A9 A10 A11 A12A13A14A15A16 L
(1)
3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24 L(1)
4th Cycle A25 L(1) L(1) L(1) L(1) L(1) L(1) L(1) L(1)
Table 4: Address Cycle Map(x16)
NOTE:
1. L must be set to Low.
FUNCTION 1st CYCLE 2nd CYCLE 3rd CYCLE 4th CYCLE Acceptabl e command
during busy
READ 1 00h/01h - - -
READ 2 50h---
READ ID 90h---
RESET FFh - - - Yes
PAGE PROGRAM
(start) 80h 10h - -
COPY BACK PGM
(start) 00h 8Ah - -
BLOCK ERASE 60h D0h - -
READ STATUS REGISTER 70h--- Yes
Table 5: Command Set
Rev 0.5 / Jul. 2007 10
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
CLE ALE CE WE RE WP MODE
H L L Rising H X Read Mode Command Input
L H L Rising H X Address Input(4 cycles)
H L L Rising H H Wri te Mo de Command Input
L H L Rising H H Address Input(4 cycles)
LLLRisingHHData Input
LL
L(1) H Falling X Sequential Read and Data Output
L L L H H X During Read (Busy)
XXXXXHDuring Program (Busy)
XXXXXHDuring Erase (Busy)
XXXXXLWrite Protect
XXHXX0V/VccStand By
Table 6: Mode Selection
NOTE:
1. With the CE high during latency time does not stop the read operation
Rev 0.5 / Jul. 2007 11
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
2. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby.
Typically glitches less t han 5 ns on Chip E nable, W rit e Enable and R ead Enable are igno red by the memory an d do not
affect bus o perations.
2.1 Command Input.
Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip
Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising
edge of Write Enable. Mor eover fo r comm ands that starts a modif y ope r ation (wr ite/er ase) the Write Protect pin must
be high. See figure 6 and table 13 for details of the timings requirements. Command codes are always applied on
IO7:0, disregarding the bus configuration (X8/X16).
2.2 Address Input.
Address Input bus op er ation allows the ins ertion of the memory addr ess. To insert the 25 addresses needed to access
the 512Mbit 4 clock cycles (x8 version) are needed. Addresses are accepted with Chip Enable low, Address Latch
Enable High, Command Latch Enable low an d Read Enable High and latched on the rising edge of W r ite Enable. Mor e-
over for commands that starts a modify operation (write/erase) the Write Protect pin must be high. See figure 7 and
table 13 for details of the timings requirements. Addresses are always applied on IO7:0, disregarding the bus configu-
ration (X8/X16).
2.3 Data Input.
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and
timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command
Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See figur e
8 and table 13 for details of the timings requirements.
2.4 Data Output.
Data Output bus operation allows to read data from the memory array and to check the status register content, the
lock status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write
Enable High, Addres s Latch Enable low , and Command Latch En able low . See figures 9 to 15 and table 13 fo r details of
the timings requirements.
2.5 Write Protect.
Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not
start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the pro-
tection even during the power up.
2.6 Standby.
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.
Rev 0.5 / Jul. 2007 12
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
3. DEVICE OPERATION
3.1 Page Read.
Three types of operations are available: random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes (x8 device) or 264 words (x16
device) of data within the selected page are transferred to the data registers in less than access random read time tR
(12us). The system controller can detect the completion of th is data tr ansf er tR (12us) by analyzing the output of R/B
pin. Once the data in a page is loaded into the registers, they may be r ead out in 30ns cycle time by sequentially puls-
ing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last
column address.
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting tR again allows reading the selected page. The sequential row read operation is terminated by bringing CE
high.
The way the Read1 and R e ad2 comma nds work is like a pointer set to either the main area or the spare area. Writing
the Read2 command user may selectively access the spare area of bytes 512 to 527 (x8 device) or words 256 to 263
(x16 device). Addresses A0 to A3 set the starting address of the spare area while addresses A4 to A7 are ignored.
Unless the operation is aborted, the page address is automatically incremented for sequential row
Read as in R ead1 oper ation and spare sixteen b ytes of each page (x8 device) or eight words of ea ch page (x16 device)
may be sequentially read. The Read1 command (00h/01h) is needed to move the pointer back to the main area.
The Read2 command (50h) is needed to move the pointer back to the spare area.
Figure_11 to 14 show typical sequence and timings for each read operation.
3.2 Page Program.
The device is programmed basically on a page basis, but it does allow multiple partia l pa ge pr ogramming of a byte or
consecutive bytes up to 528 (x8 device), in a single page program cycle. The number of consecutive partial page pro-
gramming operations within the same page without an intervening erase operation must not exceed 1 for main array
and 2 for spar e arr ay. The addressing may be done in an y r andom order in a block. A pa ge progr am cycle consists of a
serial data loading period in which up to 528 bytes (x8 device) or 264 word (x16 device) of data may be loaded into
the page register, followed by a non-volatile programming period where the loaded data is programmed into the
appropriate cell. Serial data loading can be started from 2nd half arr ay by mo ving pointer. About the pointer operation,
please refer to Figure 24 The data-loading sequence begins by inputting the Serial Data Input command (80h), fol-
lowed by the f our addr ess input cy cle s and then s erial da ta loading. The P age Progr am confirm command (1 0h) starts
the programming process. Writing 10h alone without previously entering the serial data will not initiate the program-
ming process. The internal Program Erase Controller automatically executes the algorithms and timings necessary for
program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read
Status Register command may be entered, with RE and CE low, to read the status register. The system controller can
detect the completion of a progr am cycle by monitoring the R/B output, or the Status bit (I/O 6) of the Status Register.
Only the Read Status command and Reset command are valid while programming is in progress. When the Page Pro-
gram is complete, the Write Status Bit (I/O 0) may be checked in Figure 15 The internal write verify detects only errors
for "1"s that are not successf ully progr ammed to "0"s. The command r egister rem ains in R ead Status comma nd mode
until another valid command is written to the command register.
Rev 0.5 / Jul. 2007 13
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
3.3 Block Erase.
The Erase operation is done on a block (16K Byte) basis. It consists of an Erase Setup command (60h), a Block
address loading and an Erase Confirm Command (D0h). The Erase Confirm command (D0h) following the block
address loading initiates the internal erasing process. This two-step sequence of setup followed by execution com-
mand ens ures that me mory contents are not accidentally erased due to external noise conditions.
The block address loading is a ccomplished three cycles. Only block addresses (A14 to A25 , highest address depending
on the device density) are needed while A9 to A13 is ignored.
At the rising edge of WE after the er ase confirm command input, the internal Pr ogram Eras e Controller hand les erase
and erase-verify. When the erase operation is completed, the Write Status Bit (I/O 0) may be checked. Figure 17
details the sequence.
3.4 Copy-Back Program.
The copy-back program is provided to quickly and efficiently rewrite data stored in one page within the plane to
another page within the same plane without using an external memory. Since the time-consuming sequential reading
and its reloading cycles are removed, the system performance is improved. The benefit is especially
obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned
free block. The operation for performing a copy-back program is a sequential execution of page-read without burst-
reading cycle and copying-program with the address of destination page. A normal read operation with "00h" com-
mand and the address of the source page moves the whole 528byte data into the internal buffer.
As soon as the device returns to Ready state, Page-Copy Data-input command (8Ah) with the address cycles of desti-
nation page followed may be written. The Program Confirm command (10h) is not needed to actually begin the pro-
gramming oper ation. F or b ackward-compa tibility, issuing Program Confirm command during copy-back does not aff ect
correct device operation.
Copy-Back Pr ogram oper ation is allowed only within the same memory plane. Once the Copy -Back Program is finished,
any additional partial page programming into the copied pages is prohibited before erase. Plane address must be the
same between source and target page.
"When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if Copy-Back oper-
ations are accumulated over time, bit error due to charge loss is not checked by external error detection/correction
scheme. For this reason, two bit error correction is recommended for the use of Copy-Back operation."
Figure 16 shows the command sequence for the copy-back operation.
The Copy Back Program operation requires three steps:
1. The source page must be read using the Read A command (one bus write cycle to setup the command and then
4 bus write cy cles to input the source page a ddress). This oper ation copies all 2KBytes fr om the page into the Page
Buffer.
2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is
given with the 4bus cycles to input the target page address. The v alue for A25 from second to the last page address
must be same as the value given to A25 in first address.
3. Then the confirm command is issued to start the P/E/R Controller.
Rev 0.5 / Jul. 2007 14
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
3.5 Read Status Register.
The device contains a Status Register which may be read to find out whether read, program or erase operatio is com-
pleted, and whether the read, program or er ase operation is com pleted successfully. After writing 70h command to the
command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or
RE, whichever occurs last. This two-line control allows the system to poll the progress of each device in multiple mem-
ory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status.
Ref er to Table 14 for specific Status R eg ister definitions. T he command regis ter rema ins in Status Read mode until fur-
ther commands are issued to it. Therefore, if the status register is read during a r a ndom rea d cy cle, a re ad comma nd
(00h or 50h) should be given before sequential page read cycle.
3.6 Read ID.
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an
address input of 00h. Four read cycles sequentially output the 1st cycle (ADh), and 2nd cycle (the device code) and
3rd cycle ID, 4th cycle ID, respectively. The command register remains in Read ID mode until further commands are
issued to it. Figure 18 shows the operation sequence, while Tables 16 explain the byte meaning.
3.7 Reset.
The device offers a reset feature, executed by writing FFh to the command re gis ter. When the device is in Busy state
during random read, pr ogr am or er ase mode, the res et operation will abort these operations. The contents of memory
cells being altered are no longer valid, as the data will be partially programmed or erased.
The command register is cleared to wait fo r the next comm and, and the Status Register is cleared to value C0h when
WP is high. Refer to table 14 for device status after reset operation. If the device is already in reset state a new reset
command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset com-
mand is written. Refer to Figure 21 below.
Rev 0.5 / Jul. 2007 15
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
4. OTHER FEATURES
4.1 Data Protection for Power on/off Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal
voltage detector disables all functions whene v er Vcc is below about 2.0V(3.0V devi ce ). WP pin p rovides hardware pro-
tection and is recommended to be kept at VIL during powe r-up an d power- down. A recove ry time of minimum 10us is
required before internal circuit gets ready for any command sequences as shown in Figure 22. The two-step command
sequence for program/erase provides additional software protection.
4.2 Ready/Busy.
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase,
copy-back and random read completion. The R/B pin is normally high and goes to low when the device is busy (after a
reset, read, program, erase operation). It returns to high when the internal controller has finished the operation. The
pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied.
Because pull-u p re sistor v a lue is re late d to tr (R/B) and current drain during busy (Ibusy), an appropriat e v alue can be
obtained with the following reference chart in Figure 23. Its value can be determined by the following guidance.
Rev 0.5 / Jul. 2007 16
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Parameter Symbol Min Typ Max Unit
Valid Block Number NVB 4016 4096 Blocks
Table 7: Valid Blocks Number
NOTE:
1. The 1st block is guaranteed to be a valid block up to 1K cycles with ECC. (1bit/528bytes)
Symbol Parameter Value Unit
3.3V
TAAmbient Operating Temperature (Temperature Range Option 1) 0 to 70 ℃
Ambient Operating Temperature (Industrial Temperature Range) -40 to 85 ℃
TBIAS Temperature Und er Bias -50 to 125 ℃
TSTG Storage Temperature -65 to 150 V
VIO(2) Input or Output Voltage -0.6 to 4.6 V
Vcc Supply Voltage -0.6 to 4.6 V
Table 8: Absolute maximum ratings
NOTE:
1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute
Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of
the device at the se or an y other conditions abov e those indicat ed in t he Ope rat ing se ctions o f this specifi cation is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.
Rev 0.5 / Jul. 2007 17
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 5: Block Diagram
$''5(66
5(*,67(5
&2817(5
352*5$0
(5$6(
&21752//(5
+9*(1(5$7,21
&200$1'
,17(5)$&(
/2*,&
&200$1'
5(*,67(5
'$7$
5(*,67(5
,2
5(
%8))(56
<'(&2'(5
3$*(%8))(5
;
'
(
&
2
'
(
5
0ELW 0ELW
1$1')ODVK
0(025<$55$<
:3
&(
:(
&/(
$/(
$a$
Rev 0.5 / Jul. 2007 18
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Parameter Symbol Test Conditions 3.3Volt Unit
Min Typ Max
Operating
Current
Sequential
Read ICC1 tRC=30ns
CE=VIL,
IOUT=0mA -1530mA
Program ICC2 - - 15 30 mA
Erase ICC3 - - 15 30 mA
Stand-by Current (TTL) ICC4 CE=VIH,
WP=0V/Vcc -- 1mA
Stand-by Current (CMOS) ICC5 CE=Vcc-0.2,
WP=0V/Vcc -1050uA
Input Leakage Current ILI VIN=0 to Vcc (max) - - ±10 uA
Output Leakage Current ILO VOUT =0 to Vcc (max) - - ±10 uA
Input High Voltage VIH - Vccx0.8 - Vcc+0.3 V
Input Low Voltage VIL --0.3-Vccx0.2V
Output High Voltage Level VOH IOH=-400uA 2.4 - - V
Output Low Voltage Leve VOL IOL=2.1mA - 0.4 V
Output Low Current (R/B)IOL
(R/B)VOL=0.4V 8 10 - mA
Table 9: DC and Operating Characteristics
Parameter Value
3.3Volt
Input Pulse Levels 0V to Vcc
Input Rise and Fall Times 5ns
Input and Output Timing Levels Vcc / 2
Output Load (2.7V - 3.6V) 1 TTL GATE and CL=50pF
Table 10: AC Conditions
Rev 0.5 / Jul. 2007 19
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Item Symbol Test Condition Min Max Unit
Input / Output Capacitance CI/O VIL=0V - 10 pF
Input Capacitance CIN VIN=0V - 10 pF
Table 11: Pin Capacitance (TA=25C, F=1.0MHz)
Parameter Symbol Min Typ Max Unit
Program Time tPROG - 200 700 us
Number of partial Program Cycles in the same page Main Array NOP - - 1 Cycles
Spare Array NOP - - 2 Cycles
Block Erase Time tBERS -23ms
Table 12: Program / Erase Characteristics
Rev 0.5 / Jul. 2007 20
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Parameter Symbol 3.3Volt Unit
Min Max
CLE Setup time tCLS 15 ns
CLE Hold time tCLH 5ns
CE setup time tCS 20 ns
CE hold time tCH 5ns
WE puls e width tWP 15 ns
ALE setup time tALS 15 ns
ALE hold time tALH 5ns
Data setup time tDS 15 ns
Data hold time tDH 5ns
Write C y cle time tWC 30 ns
WE High hold time tWH 10 ns
Data Transfer from Cell to register tR12 us
ALE to RE Delay tAR 10 ns
CLE to RE Delay tCLR 10 ns
Ready to RE Low tRR 20 ns
RE Pulse Width tRP 15 ns
WE High to Busy tWB 100 ns
Read Cycle Time tRC 30 ns
RE Access Time tREA 18 ns
RE High to Output High Z tRHZ 50 ns
CE High to Output High Z tCHZ 50 ns
RE or CE high to Output hold tOH 10 ns
RE High Hold Time tREH 10 ns
Output High Z to RE low tIR 0ns
CE Access Time tCEA 25 ns
WE High to RE low tWHR 60 ns
Last RE High to busy (at sequential read) tRB 100 ns
CE High to Ready (in case of interception by CE at read) tCRY 60+tr(R/B#)(4) ns
CE High Hold Time (at the last serial read)(3) tCEH 100 ns
Device Resetting Time (Read / Program / Erase) tRST 5/10/500(1,2) us
Write Protecti on time tWW(5) 100 ns
Table 13: AC Timing Characteristics
NOTE:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
2. The time to Ready depends on the value of the pull-up resistor tied R/B pin.ting time.
3. To break the sequential read cycle, CE must be held for longer time than tCEH.
4. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
5. Program / Erase Enable Operation : WP high to WE High.
Program / Erase Disable Operation : WP Low to WE High.
Rev 0.5 / Jul. 2007 21
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
IO Pagae
Program Block
Erase Read Cache
Read CODING
0 Pass / Fail Pass / Fail NA Pass: ‘0’ Fail: ‘1’
1NA NA NA Pass: ‘0’ Fail: ‘1’ (Only for
Cache Program, else Don’t
care)
2NA NA NA -
3NA NA NA -
4NA NA NA -
5 Ready/Busy Ready/Busy Ready/Busy P/E/R
Controller Bit Active: ‘0’ Idle: ‘1’
6 Ready/Busy Ready/Busy Ready/Busy Ready/Busy Busy: ‘0’ Ready’: ‘1’
7 Write Protect Write Protect Write Protect Protected: ‘0’
Not Protected: ‘1’
Table 14: Status Register Coding
DEVIIDENTIFIER CYCLE DESCRIPTION
1st Manufacturer Code
2nd Device Identifier
Table 15: Device Identifier Coding
Part Number Voltage Bus Width 1st cycle
(Manufacture Code) 2nd cycle
(Device Code)
HY27US0812(1/2)B 3.3V x8 ADh 76h
HY27US1612(1/2)B 3.3V x16 ADh 56h
Table 16: Read ID Data Table
Rev 0.5 / Jul. 2007 22
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 6: Command Latch Cycle
W&/
6
W&6
W:3
&RPPDQG
&/(
&(
:(
$/(
,2[
W'+W'6
W$/6 W$/+
W&/+
W&+
W&/6
W&6
W:3
W:& W:&
W:3 W:3 W:3
W$/6
W:+W:+W:+
W$/+ W$/6W$/6W$/6
&RO$GG
W$/+ W$/+ W$/+
W'+
&RO$GG 5RZ$GG 5RZ$GG
W:&
W'+ W'+ W'+
W'6 W'6 W'6W'6
&/(
&(
:(
$/(
,2[
Figure 7: Address Latch Cycle
Rev 0.5 / Jul. 2007 23
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
W:&
W$/6
W&/+
W&+
W:3
W:+
',1 ',1 ',1ILQDO
W'+ W'+ W'+
W'6 W'6 W'6
W:3 W:3
&/(
$/(
&(
,2[
:(
t
CEA
t
REA
t
RP
t
REA
t
RHZ
t
RHZ*
Dout Dout Dout
t
CHZ*
t
OH
t
OH
t
REA
t
REH
t
RC
t
RR
Notes : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
CE
RE
R/B
I/Ox
Figure 9: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L)
Figure 8. Input Data Latch Cycle
Rev 0.5 / Jul. 2007 24
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 10: Status Read Cycle
tCLS
tCLR
tCLH
tCS
tCH
tWP
tWHR
tCEA
tDS tREA
tCHZ
tRH=
t2H
t2H
70h Status Output
tDH tIR
CE
WE
I/O
x
CLE
RE
&/(
&(
:(
$/(
5(
,2[
5%
W:&
W&(+
W&+=
W&5<
W5+=
W5&
W5
W$5
W:%
W53
KRUK &RO$GG 5RZ$GG 5RZ$GG 5RZ$GG 'RXW1 'RXW1 'RXW1 'RXW
W5%
&ROXPQ
$GGUHVV 3DJH5RZ$GGUHVV
%XV\
Figure 11: Read1 Operation (Read One Page)
Rev 0.5 / Jul. 2007 25
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
&/(
&(
:(
$/(
5(
,2[
5%
KRUK &RO$GG 5RZ$GG 5RZ$GG 5RZ$GG 'RXW1 'RXW1 'RXW1
%XV\
W55
W5 W5&
W$5
W:% W&+=
&RO$GG 5RZ$GG
Figure 12: Read1 Operation intercepted by CE
&/(
&(
:(
$/(
5(
,2[
5%
K
&RO$GG 5RZ$GG 5RZ$GG
'RXW
1 'RXW
1
'RXW
'RXW
0
2XWSXW
1
2XWSXW
0
%XV\ %XV\
5HDG\
5RZ$GG
Figure 13: Read2 Operation (Sequential Row Read)
Rev 0.5 / Jul. 2007 26
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
&/(
$/(
&(
5(
5%
,2[
:(
W:&
K &RO$GG
6HULDO'DWD
,QSXW&RPPDQG &ROXPQ
$GGUHVV
5RZ$GGUHVV 5HDG6WDWXV
&RPPDQG
3URJUDP
&RPPDQG
,2R 6XFFHVVIXO3URJUDP
,2R (UURULQ3URJUDP
[XSWR%\WH
[XSWS:RUG
6HULDO,QSXW
5RZ$GG 5RZ$GG 'LQ
1
'LQ
0K K ,2R
W:& W:&
W:% W352*
5RZ$GG
&/(
&(
:(
$/(
5(
,2[
5%
K
&RO$GG 5RZ$GG 5RZ$GG
'RXW
1'RXW
1 'RXW
'RXW
'RXW
'RXW
0
12XWSXW
0
2XWSXW
%XV\ %XV\
5HDG\
5RZ$GG
Figure 15: Page Program Operation
Figure 14: Sequential Row Read Operation Within a Block
Rev 0.5 / Jul. 2007 27
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
W:&
W:%
W5
W352*
,2
K
$K
K
&ROPQ
$GGUHVV 5RZ$GGUHVV &ROPQ
$GGUHVV 5RZ$GGUHVV 5HDG6WDWXV
&RPPDQG
%XV\
%XV\
,2 6XFFHVVIXO3URJUDP
,2 (UURULQ3URJUDP
&RS\%DFN'DWD
,QSXW&RPPDQG KZULWHF\FOHQRPRUH
&/(
&(
:(
$/(
5(
,2
[
5%
&RO$GG 5RZ$GG 5RZ$GG 5RZ$GG &RO$GG 5RZ$GG 5RZ$GG 5RZ$GG
Figure 16 : Copy Back Program
Rev 0.5 / Jul. 2007 28
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
W:&
&/(
&(
:(
$/(
5(
,2[
5%
W:% W%(56
%86<
K ,2
5RZ$GG 5RZ$GG 5RZ$GG
K
$XWR%ORFN(UDVH6HWXS&RPPDQG
(UDVH&RPPDQG
5HDG6WDWXV
&RPPDQG
,2 6XFFHVVIXO(UDVH
,2 (UURULQ(UDVH
5RZ$GGUHVV
'K
Figure 17: Block Erase Operation (Erase One Block)
tAR
90h
CLE
CE
WE
ALE
RE
I/O x 00h
tREA
Read ID Command Address 1 cycle Maker Code Device Code
ADh K
Figure 18: Read ID Operation
Rev 0.5 / Jul. 2007 29
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
System Interface Using CE don’t care
To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below.
So, it is possible to connect NAND Flash to a microporcessor. The only function that was removed from standard NAND
Flash to make CE don’t care read operation was disabling of the au tomatic sequential read function. (HY27US(08/16)122B)
&(GRQ¶WFDUH
K 6WDUW$GG&\FOH 'DWD,QSXW K'DWD,QSXW
&/(
&(
:(
$/(
,2[
Figure 19: Program Operation with CE don’t-care.
,IVHTXHQWLDOURZUHDGHQDEOHG
&(PXVWEHKHOGORZGXULQJW5 &(GRQ¶WFDUH
K K
&/(
&(
5(
$/(
5%
:(
,2[ 6WDUW$GG&\FOH 'DWD2XWSXWVHTXHQWLDO
W5
Figure 20: Read Operation with CE don’t-care.
Rev 0.5 / Jul. 2007 30
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 21: Reset Operation
))K
W567
:(
$/(
&/(
5(
,2
5%
:3
:(
9FF
XV
W
97+
Figure 22: Power On and Data Protection Timing
VTH = 2.5 Volt for 3.3 Volt Supply devices
Rev 0.5 / Jul. 2007 31
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
5SYDOXHJXLGHQFH
5SPLQ
ZKHUH,/LVWKHVXPRIWKHLQSXWFXUUQWVRIDOOGHYLFHVWLHGWRWKH5%SLQ
5SPD[LVGHWHUPLQHGE\PD[LPXPSHUPLVVLEOHOLPLWRIWU
#9FF 97D &&
/
S)
)LJ5SYVWUWI5SYVLEXV\
9FF0D[9
2/0D[ 9
P$,/,2/,/
5S LEXV\
5SRKP
LEXV\
LEXV\>$@
WUWI>V@
WI
%XV\
5HDG\ 9FF
92+
92/
9 99 9
2/ 2+
WUWI
9FF
Q P
N N N N
Q P
Q P
*1'
'HYLFH
RSHQGUDLQRXWSXW
5%
Figure 23: Ready/Busy Pin electrical specifications
Rev 0.5 / Jul. 2007 32
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
['HYLFHV
$UHD$
K
$UHD%
K
$UHD&
K
%\WHV %\WHV %\WHV
$%&
3RLQWHU
KKK
3DJH%XIIHU
['HYLFHV
$UHD$
K
$UHD&
K
%\WHV %\WHV
$&
3RLQWHU
KK
3DJH%XIIHU
K K $GGUHVV
,QSXWV 'DWD,QSXW K K K $GGUHVV
,QSXWV 'DWD,QSXW K
K K $GGUHVV
,QSXWV 'DWD,QSXW K K K $GGUHVV
,QSXWV 'DWD,QSXW K
K K $GGUHVV
,QSXWV 'DWD,QSXW K K K $GGUHVV
,QSXWV 'DWD,QSXW K
$5($$
$5($%
$5($&
,2
,2
,2
$UHDV$%&FDQEHSURJUDPPHGGHSHQGLQJRQKRZPXFKGDWDLVLQSXW6XEVHTXHQWKFRPPDQGVFDQEHRPLWWHG
$UHDV%&FDQEHSURJUDPPHGGHSHQGLQJRQKRZPXFKGDWDLVLQSXW7KHKFRPPDQGPXVWEHUHLVVXHGEHIRUHHDFKSURJUDP
2QO\$UHDV&FDQEHSURJUDPPHG6XEVHTXHQWKFRPPDQGFDQEHRPLWWHG
Figure 24: Pointer operations
Figure 25: Pointer Operations for porgramming
Rev 0.5 / Jul. 2007 33
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the
blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and
common source line by a select transistor. The devices are supplied with all the locations inside valid blocks
erased(FFh).
The Bad Block Information is written prior to shipping. Any block where the 6th Byte/ 3rd Word in the spare area of
the 1st or 2nd page (if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Blo c k Information must be
read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recog-
nize the Bad Blocks based on the original information it is recommended to create a Bad Block table f ollowing the flow-
chart shown in Figure 26. The 1st block, which is placed on 00h block address is guaranteed to be a valid block.
Block Replacement
Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying
the data to a valid block. These ad ditional Bad Blocks can be identified as attempts to program or era se them will give
errors in the Status Register.
As the failure of a page program operation doe s not affect the data in other pages in the same block, the block can b e
replaced by re-programming the current data and copying the rest of the replaced block to an available valid block.
The Copy Back Program command can be used to copy the data to a valid block.
See the “Copy Back Program” section for more details.
Refer to Table 18 for the recommended procedure to follow if an error occurs during an operation.
Operation Recommended Procedure
Erase Block Replacement
Program Block Replacement
Read ECC (with 1bit/528byte)
Figure 26: Bad Block Management Flowchart
<HV
<HV
1R
1R
67$57
%ORFN$GGUHVV
%ORFN
'DWD
))K"
/DVW
EORFN"
(1'
,QFUHPHQW
%ORFN$GGUHVV
8SGDWH
%DG%ORFNWDEOH
Table 18: Block Failure
Rev 0.5 / Jul. 2007 34
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Write Protect Operation
The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations
are enabled and disabled as follows (Figure 27~30)
::
W
K K
:(
,2[
:3
5%
K K
W::
:(
,2[
:3
5%
Figure 27: Enable Programming
Figure 28: Disable Programming
Rev 0.5 / Jul. 2007 35
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
K
W
'K
::
:(
,2[
:3
5%
K
W::
'K
:(
,2[
:3
5%
Figure 29: Enable Erasing
Figure 30: Disable Erasing
Rev 0.5 / Jul. 2007 36
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Table 19: 48pin-TSOP1, 12 x 20mm, Package Mechanical Data
Symbol millimeters
Min Typ Max
A1.200
A1 0.050 0.150
A2 0.980 1.030
B 0.170 0.250
C 0.100 0.200
CP 0.100
D 11.910 12.000 12.120
E 19.900 20.000 20.100
E1 18.300 18.400 18.500
e 0.500
L 0.500 0.680
alpha 0 5
'
$
',(
$
H
%
/
Į
(
(
&
&3
$
Figure 31: 48pin-TSOP1, 12 x 20mm, Package Outline
Rev 0.5 / Jul. 2007 37
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Symbol millimeters
Min Typ Max
A0.650
A1 0 0.050 0.080
A2 0.470 0.520 0.570
B 0.130 0.160 0.230
C 0.065 0.100 0.175
C10.450 0.650 0.750
CP 0.100
D 16.900 17.000 17.100
D1 11.910 12.000 12.120
E 15.300 15.400 15.500
e 0.500
alpha 0 8
Figure 32. 48pin-USOP1, 12 x 17mm, Package Outline
Table 20: 48pin-USOP1, 12 x 17mm, Package Mechanical Data
$
$
$
&
'
(
&
H%
$QJOH DOSKD
'
Į
&3
Rev 0.5 / Jul. 2007 38
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Symbol Millimeters
Min Typ Max
A 0.80 0.90 1.00
A1 0.25 0.30 0.35
A2 0.55 0.60 0.65
b 0.40 0.45 0.50
D 8.90 9.00 9.10
D1 4.00
D2 7.20
E 10.90 11.00 11.10
E1 5.60
E2 8.80
e0.80
FD 2.50
FD1 0.90
FE 2.70
FE1 1.10
SD 0.40
SE 0.40
$
$
$
6(
)(
)(
H
((
%$//³FS´
(
H
HE
'
'
6'
)'
)'
'
Figure 33. 63-ball FBGA - 9 x 11 ball array 0.8mm pitch, Pakage Outline
NOTE: Drawing is not to scale.
Rev 0.5 / Jul. 2007 39
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
MARKING INFORMATION - TSOP1/USOP
Packag M arking Exam ple
TSOP1
/
USOP
K O R
H Y 2 7 U S x x 1 2 x B
x x x x Y W W x x
- hynix
- K O R
- HY27USxx12xB xxxx
HY : Hynix
2 7 : NAND Flash
U: Pow er Supply
S: Classification
x x : B it O r ga n iza tion
12: Density
x: Mode
B: Version
x: Package Type
x : Package M aterial
x : O perating Temperature
x : Bad Block
- Y : Year (ex: 5= year 2005, 06= year 2006)
- w w: Work W eek (ex: 12= w ork w eek 12)
- xx : Process C ode
Note
- C ap ital Lette r
- Sma ll Letter
: H yn ix S ymb ol
: Or ig in C o u n tr y
: U(2.7V ~3.6V)
: S in g le L e v e l C e ll+S in g le D ie +S ma ll B lo ck
: 08(x8), 16(x16)
: 512M bit
: 1 n C E & 1 R /n B ; Se q u e ntia l R o w Re ad E n a b le
: 1 n C E & 1 R /n B ; Se q u e ntia l R o w Re ad Disa b le
: 3 rd Ge ne ration
: T(48-TSO P1), S(48-U SOP)
: Blank(Norm al), P(Lead Free)
: C (0 ℃~70℃), I(-40 ℃~85℃)
: B(Included Bad Block), S(1~5 Bad Block),
P (A ll G o o d B loc k )
: Fixe d Item
: N o n-fix ed Item
: Pa rt N umb er
Rev 0.5 / Jul. 2007 40
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
MARKING INFORMATION - FBGA
Packag M arking Exam ple
FBGA
K O R
H Y 2 7 U S 0 8 1 2 x B
x x x x Y W W x x
- hynix
- K O R
- H Y27U0812xB xxxx
HY : Hynix
2 7 : NAND Flash
U: Pow er Supply
S: Classification
08: Bit O rganization
12: Density
x: Mode
B: Version
x: Package Type
x : Package M aterial
x : O perating Temperature
x : Bad Block
- Y : Year (ex: 5= year 2005, 06= year 2006)
- w w: Work W eek (ex: 12= w ork w eek 12)
- xx : Process C ode
Note
- C ap ital Lette r
- Sma ll Letter
: H yn ix S ymb ol
: Or ig in C o u n tr y
: U(2.7V ~3.6V)
: S in g le L e v e l C e ll+S in g le D ie +S ma ll B lo ck
: 0 8(x 8)
: 512M bit
: 1 n C E & 1 R /n B ; Se q u e ntia l R o w Re ad E n a b le
: 1 n C E & 1 R /n B ; Se q u e ntia l R o w Re ad Disa b le
: 3 rd Ge ne ration
: F (63 F BGA )
: Blank(Norm al), P(Lead Free)
: C (0 ℃~70℃), I(-40 ℃~85℃)
: B(Included Bad Block), S(1~5 Bad Block),
P (A ll G o o d B loc k )
: Fixe d Item
: N o n-fix ed Item
: Pa rt N umb er
