Figure Number LIST OF FIGURES Page Number 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 MC68336/376 Block Diagram ......................................................................... 3-4 MC68336 Pin Assignments for 160-Pin Package ........................................... 3-5 MC68376 Pin Assignments for 160-Pin Package ........................................... 3-6 MC68336/376 Address Map ......................................................................... 3-13 Overall Memory Map .................................................................................... 3-14 Separate Supervisor and User Space Map .................................................. 3-15 Supervisor Space (Separate Program/Data Space) Map ............................. 3-16 User Space (Separate Program/Data Space) Map ...................................... 3-17 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 CPU32 Block Diagram .................................................................................... 4-2 User Programming Model ............................................................................... 4-3 Supervisor Programming Model Supplement ................................................. 4-4 Data Organization in Data Registers .............................................................. 4-5 Address Organization in Address Registers ................................................... 4-6 Memory Operand Addressing ......................................................................... 4-8 Loop Mode Instruction Sequence ................................................................. 4-15 Common In-Circuit Emulator Diagram .......................................................... 4-20 Bus State Analyzer Configuration ................................................................. 4-20 Debug Serial I/O Block Diagram ................................................................... 4-25 BDM Serial Data Word ................................................................................. 4-26 BDM Connector Pinout ................................................................................. 4-26 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 System Integration Module Block Diagram .................................................... 5-2 System Clock Block Diagram ......................................................................... 5-4 System Clock Oscillator Circuit ...................................................................... 5-5 System Clock Filter Networks ......................................................................... 5-6 LPSTOP Flowchart ....................................................................................... 5-12 System Protection Block ............................................................................... 5-12 Periodic Interrupt Timer and Software Watchdog Timer .............................. 5-16 MCU Basic System ....................................................................................... 5-19 Operand Byte Order ..................................................................................... 5-24 Word Read Cycle Flowchart ......................................................................... 5-27 Write Cycle Flowchart ................................................................................... 5-28 CPU Space Address Encoding ..................................................................... 5-30 Breakpoint Operation Flowchart ................................................................... 5-32 LPSTOP Interrupt Mask Level ...................................................................... 5-33 Bus Arbitration Flowchart for Single Request ............................................... 5-38 Preferred Circuit for Data Bus Mode Select Conditioning ............................ 5-42 Alternate Circuit for Data Bus Mode Select Conditioning ............................. 5-43 Power-On Reset ........................................................................................... 5-48 Basic MCU System ....................................................................................... 5-54 Chip-Select Circuit Block Diagram ............................................................... 5-55 CPU Space Encoding for Interrupt Acknowledge ......................................... 5-60 MC68336/376 LIST OF FIGURES USER'S MANUAL Rev. 15 Oct 2000 MOTOROLA xvii Figure Number Page Number 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 QADC Block Diagram ..................................................................................... 8-1 QADC Input and Output Signals ..................................................................... 8-3 Example of External Multiplexing ................................................................. 8-11 QADC Module Block Diagram ...................................................................... 8-13 Conversion Timing ........................................................................................ 8-14 Bypass Mode Conversion Timing ................................................................. 8-15 QADC Queue Operation with Pause ............................................................ 8-18 QADC Clock Subsystem Functions .............................................................. 8-24 QADC Clock Programmability Examples ..................................................... 8-26 QADC Conversion Queue Operation ........................................................... 8-29 QADC Interrupt Vector Format ..................................................................... 8-33 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 QSM Block Diagram ....................................................................................... 9-1 QSPI Block Diagram ....................................................................................... 9-6 QSPI RAM ...................................................................................................... 9-8 Flowchart of QSPI Initialization Operation .................................................... 9-11 Flowchart of QSPI Master Operation (Part 1) ............................................... 9-12 Flowchart of QSPI Master Operation (Part 2) ............................................... 9-13 Flowchart of QSPI Master Operation (Part 3) ............................................... 9-14 Flowchart of QSPI Slave Operation (Part 1) ................................................. 9-15 Flowchart of QSPI Slave Operation (Part 2) ................................................. 9-16 SCI Transmitter Block Diagram .................................................................... 9-24 SCI Receiver Block Diagram ........................................................................ 9-25 10-1 10-2 10-3 10-4 10-5 10-6 CTM4 Block Diagram ................................................................................... 10-1 CPSM Block Diagram ................................................................................... 10-5 FCSM Block Diagram ................................................................................... 10-6 MCSM Block Diagram .................................................................................. 10-8 DASM Block Diagram ................................................................................. 10-12 Pulse-Width Modulation Submodule Block Diagram .................................. 10-14 11-1 11-2 11-3 TPU Block Diagram ...................................................................................... 11-1 TCR1 Prescaler Control ............................................................................. 11-14 TCR2 Prescaler Control ............................................................................. 11-14 13-1 13-2 13-3 13-4 13-5 TouCAN Block Diagram ............................................................................... 13-1 Typical CAN Network ................................................................................... 13-2 Extended ID Message Buffer Structure ........................................................ 13-3 Standard ID Message Buffer Structure ......................................................... 13-4 TouCAN Interrupt Vector Generation ......................................................... 13-19 A-1 A-2 A-3 A-4 A-5 CLKOUT Output Timing Diagram ................................................................... A-8 External Clock Input Timing Diagram ............................................................. A-8 ECLK Output Timing Diagram ........................................................................ A-9 Read Cycle Timing Diagram ........................................................................ A-10 Write Cycle Timing Diagram ......................................................................... A-11 MC68336/376 LIST OF FIGURES USER'S MANUAL Rev. 15 Oct 2000 MOTOROLA xviii Figure Number Page Number A-6 A-7 A-8 A-9 A-10 A-11 A-12 A-13 A-14 A-15 A-16 A-17 A-18 A-19 A-20 Fast Termination Read Cycle Timing Diagram ............................................ A-12 Fast Termination Write Cycle Timing Diagram ............................................. A-13 Bus Arbitration Timing Diagram -- Active Bus Case ................................... A-14 Bus Arbitration Timing Diagram -- Idle Bus Case .......................................A-15 Show Cycle Timing Diagram ........................................................................ A-16 Chip-Select Timing Diagram ........................................................................ A-17 Reset and Mode Select Timing Diagram ...................................................... A-17 Background Debugging Mode Timing -- Serial Communication ................. A-18 Background Debugging Mode Timing -- Freeze Assertion ......................... A-18 ECLK Timing Diagram .................................................................................. A-20 QSPI Timing -- Master, CPHA = 0 .............................................................. A-22 QSPI Timing -- Master, CPHA = 1 .............................................................. A-22 QSPI Timing -- Slave, CPHA = 0 ................................................................ A-23 QSPI Timing -- Slave, CPHA = 1 ................................................................ A-23 TPU Timing Diagram .................................................................................... A-24 B-1 B-2 B-3 MC68336 Pin Assignments for 160-Pin Package .......................................... B-1 MC68376 Pin Assignments for 160-Pin Package .......................................... B-2 160-Pin Package Dimensions ........................................................................ B-3 D-1 D-2 D-3 User Programming Model ..............................................................................D-2 Supervisor Programming Model Supplement .................................................D-3 TouCAN Message Buffer Address Map .......................................................D-82 MC68336/376 LIST OF FIGURES USER'S MANUAL Rev. 15 Oct 2000 MOTOROLA xix Figure Number Page Number MC68336/376 LIST OF FIGURES USER'S MANUAL Rev. 15 Oct 2000 MOTOROLA xx