6288903-L - Delphi - Datasheet.Live

Freescale Semiconductor, Inc. reserves the right to change the detail specifications,

as may be required, to permit improvements in the design of its products.

Document Number: MC33886

Rev 8.0, 2/200 7

Freescale Semiconductor

Technical Data

5.0 A H-Bridge

The 33886 is a monolithic H-Bridge ideal for fractional horsepower

DC-motor and bi-directional thrust solenoid control. The IC

incorporates internal control logic, charge pump, gate drive, and low

RDS(ON) MOSFET output circuitry. The 33886 is able to control

continuous inductive DC load currents up to 5.0 A. Output l oad s ca n

be pulse width modulated (PWM-ed) at frequencies up to 10 kHz.

A Fault Status output reports undervoltage, short circuit, and

overtemperature conditions. Two independent inputs control the two

half-bridge totem-pole outputs. Two disable inputs force the H-Bridge

outputs to tri-state (exhibit high imped ance).

The 33886 is parametrically specified over a temperature range of

-40°C ≤ TA ≤ 125°C, 5.0 V ≤ V+ ≤ 28 V. The IC can also be operated

up to 40 V with derating of the specifications. The IC is available in a

surface mount power package with exposed pad for heatsinking.

Features

•5.0 V to 40 V Continuous Operation

•120 mΩ RDS(ON) H-Bridge MOSFETs

•TTL / CMOS Compatible Inputs

• PWM Frequencies up to 10 kHz

• Active Current Limiting via Internal Constant OFF-Time PWM (with

Temperature-Dependent Threshold Reduction)

• Output Short Circuit Protection

• Undervoltage Shutdown

• Fault Status Reporting

• Pb-Free Packaging Designated by Suffix Code VW

Figure 1. 33886 Simplified Application Diagram

H-BRIDGE

VW SUFFIX (PB-FREE)

DH SUFFIX

98ASH70702A

20-PIN HSOP

33886

ORDERING INFORMATION

Device Temperature

Range (TA)Package

MC33886DH/R2 - 40°C to 125°C 20 HSOP

MC33886VW/R2

5.0 V

MOTOR

MCU OUT2

OUT1

V+

CCP

AGND

IN1

IN2

33886

OUT

PGND

V+

Analog Integrated Circuit Device Data

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33886

INTERNAL BLOCK DIAGRAM

Figure 2. 33886 Simplified Internal Block Diagram

Charge

Pump

Over-

temperature

5.0 V

Regulator

Gate Drive

Current Limit,

Overcurrent

Sense

Circuit

Undervoltage

OUT1

OUT2

IN1

IN2

CCP VPWR

PGNDAGND

Control

Logic

80uA

(each)

25 uA

80 µA

25 µA

Current Limit,

Short Circuit

Sense Circuit

Charge

Pump

5.0 V

Regulator

Gate Drive

Over-

temperature

Undervoltage

V+

CCP

Analog Integrated Circuit Device Data

Freescale Semiconductor 3

33886

PIN CONNECTIONS

Figure 3. 33886 Pin Connections

Table 1. 33886 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.

Pin Number Pin Name Formal Name Definition

1AGND Analog Ground Low-current analog signal ground.

2FS Fault Status for H-

Bridge Open drain active Low Fault Status output requiring a pull-up resistor to 5.0 V.

3 IN1 Logic Input Control 1 True logic input control of OUT1 (i.e., IN1 logic High = OUT1 logic High).

4, 5, 16 V+Positive Power Supply Positive supply connections.

6, 7 OUT1 H-Bridge Output 1 Output 1 of H-Bridge.

8, 20 DNC Do Not Connect Either do not connect (leave floating) or connect these pins to ground in the application.

They are test mode pins used in manufacturing only.

9 –12 PGND Power Ground Device high-current power ground.

13 D2 Disable 2 Active Low input used to simultaneously tri-state disable both H-Bridge outputs. When

D2 is logic Low, both outputs are tri-stated.

14, 15 OUT2 H-Bridge Output 2 Output 2 of H-Bridge.

17 CCP Charge Pump Capacitor External reservoir capacitor connection for internal charge pump capacitor.

18 D1 Disable 1 Active High input used to simultaneously tri-state disable both H-Bridge outputs. When

D1 is logic High, both outputs are tri-stated.

19 IN2 Logic Input Control 2 True logic input control of OUT2 (i.e., IN2 logic High = OUT2 logic High).

DNCAGND IN2

CCP

V+

OUT2

PGND

V+

OUT1

DNC

PGND

IN1

V+

Analog Integrated Circuit Device Data

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33886

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Rating Symbol Value Unit

Supply Voltage V+ 40 V

Input Voltage (1) VIN -0.1 to 7.0 V

FS Status Output (2) V FS 7.0 V

Continuous Current (3) IOUT 5.0 A

ESD Voltage for DH Package

Human Body Model (4)

Machine Model (5)

VESD1

VESD2

±2000 (6)

±200

ESD Voltage for VW Package

Human Body Model (4)

Machine Model (5)

VESD1

VESD2

±2000

±200

Storage Temperature TSTG -65 to 150 °C

Ambient Operating Temperature (7) TA-40 to 125 °C

Operating Junction Temperature TJ-40 to 150 °C

Peak Package Reflow Temperature During Reflow (8), (9) TPPRT Note 8. °C

Approximate Junction-to-Board Thermal Resistance (and Package

Dissipation = 6.0 W) (10) RθJB ~5.0 °C/W

Notes

1. Exceeding the input voltage on IN1, IN2, D1, or D2 may cause a malfunction or permanent damage to the device.

2. Exceeding the pull-up resistor voltage on the open drain FS pin may cause permanent damage to the device.

3. Continuous current capability so long as junction temperature is ≤ 150°C.

4. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF , RZAP = 1500 Ω).

5. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).

6. All pins are capable of Human Body Model ESD voltages of ±2000 V with two exceptions pertaining only to the DH suffix package: (1) D2

to PGND is capable of ±1500 V and (2) OUT1 to AGND is capable of ±1000 V.

7. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heatsinking.

8. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

9. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL),

Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.

MC33xxxD enter 33xxx), and review parametrics.

10. Exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. The actual RθJB (junction-to-PC board)

values will vary depending on solder thickness and composition and copper trace.

Analog Integrated Circuit Device Data

Freescale Semiconductor 5

33886

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted

reflect the approximate parameter mean at TA = 25 °C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

POWER SUPPLY

Operating Voltage Range (11) V+ 5.0 –40 V

Standby Supply Current

VEN = 5.0 V, IOUT = 0 A IQ (standby) – – 20 mA

Threshold Supply Voltag e

Switch-OFF

Switch-ON

Hysteresis

V+(thres-OFF)

V+(thres-ON)

V+(hys)

4.15

4.5

150

4.4

4.75

–

4.65

5.0

–

CHARGE PUMP

Charge Pump Voltage

V+ = 5.0 V

8.0 V ≤ V+ ≤ 40 V

VCP - V+ 3.35

––

CONTROL INPUTS

Input Voltage (IN1, IN2, D1, D2)

Threshold High

Threshold Low

Hysteresis

VIH

VIL

VHYS

3.5

–

0.7

–

1.0

–

1.4

–

Input Current (IN1, IN2, D1) (12)

VIN = 0 V IIN -200 -80 –

µA

D2 Input Current (13)

V D2 = 5.0 V I D2 –25 100

µA

Notes

11. Specifications are characterized over the range of 5.0 V ≤ V+ ≤ 28 V. Operation > 28 V will cause some parameters to exceed listed

min/max values. Refer to typical operating curves to extrapolate values for operation > 28 V but ≤ 40 V.

12. Inputs IN1, IN2, and D1 have independent internal pull-up current sources.

13. The D2 input incorporates an active internal pull-down current sink.

Analog Integrated Circuit Device Data

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33886

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

POWER OUTPUTS (OUT1, OUT2)

Output-ON Resistance (14)

5.0 V ≤ V+ ≤ 28 V, TJ = 25°C

8.0 V ≤ V+ ≤ 28 V, TJ = 150°C

5.0 V ≤ V+ ≤ 8.0 V, TJ = 150°C

RDS(ON) –

–

120

–

225

300

mΩ

Active Current Limiting Threshold (via Internal Constant OFF-Time

PWM) (15) ILIM 5.2 6.5 7.8 A

High-Side Short Circuit Detection Threshold ISCH 11 – – A

Low-Side Short Circuit Detection Threshold ISCL 8.0 – – A

Leakage Current (16)

VOUT = V+

VOUT = GND

IOUT(leak) –

–100

30 200

µA

Output FET Body Diode Forward Voltage Drop (17)

IOUT = 3.0 A VF– – 2.0 V

Switch-OFF

Thermal Shutdown

Hysteresis TLIM

THYS

175

––

15 –

–

°C

FAULT STATUS (18)

Fault Status Leakage Current (19)

V FS = 5.0 V I FS(leak) – – 10

µA

Fault Status Set Voltage (20)

I FS = 300 µA

V FS(LOW) – – 1.0 V

Notes

14. Output-ON resistance as measured from output to V+ and ground.

15. Product with date codes of December 2002, week 51, will exhibit the values indicated in this table. Product with earlier date codes may

exhibit a minimum of 6.0 A and a maximum of 8.5 A.

16. Outputs switched OFF with D1 or D2.

17. Parameter is guaranteed by design but not production tested.

18. Fault Status output is an open drain output requiring a pull-up resistor to 5.0 V.

19. Fault Status Leakage Current is measured with Fault Status High and not set.

20. Fault Status Set Voltage is measured with Fault Status Low and set with I FS = 300 µA.

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted

reflect the approximate parameter mean at TA = 25 °C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

Freescale Semiconductor 7

33886

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted

reflect the approximate parameter mean at TA = 25 °C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

TIMING CHARACTERISTICS

PWM Frequency (21) f PWM – – 10 kHz

Maximum Switching Frequency During Active Current Limiting (22) f MAX – – 20 kHz

Output ON Delay (23)

V+ = 14 V t d (ON) – – 18

µs

Output OFF Delay (23)

V+ = 14 V t d (OFF) – – 18

µs

Output Rise and Fall Time (24)

V+ = 14 V, IOUT = 3.0 A tf , t r2.0 5.0 8.0

µs

Output Latch-OFF Time t a15 20.5 26 µs

Output Blanking Time t b12 16.5 21 µs

Output FET Body Diode Reverse Recove ry Time (25) t r r 100 – – ns

Disable Delay Time (26) t d (disable) – – 8.0 µs

Short Circuit / Overtemperature Turn-OFF Time (27) t FAULT –4.0 –µs

Power-OFF Delay Time t pod –1.0 5.0 ms

Notes

21. The outputs can be PWM controlled from an external source. This is typically done by holding one input high while applying a PWM

pulse train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching

frequency. Refer to Typical Switching Waveforms, Figures 10 through 17, pp. 10–11.

22. The Maximum Switching Frequency during active current limiting is internally implemented. The internal control produces a constant

OFF-time PWM of the output. The output load current effects the Maximum Switching Frequency.

23. Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition

direction) of the OUT1 or OUT2 signal. If the output is transitioning High-to-Low, the delay is from the midpoint of the input signal to the

90% point of the output response signal. If the output is transitioning Low-to-Hig h, the delay is from the midpoint of the input signal to

the 10% point of the output response signal. See Figure 4, page 8.

24. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 6, page 8.

25. Parameter is guaranteed by design but not production tested.

26. Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See

Figure 5, page 8.

27. Increasing currents will become limited at ILIM. Hard shorts will breach the ISCH or ISCL limit, forcing the output into an immediate tri-

state latch-OFF. See Figures 8 and 9, page 9. Active current limiting will cause junction temperatures to rise. A junction temperature

above 160°C will cause the active current limiting to progressively “fold-back” (or decrease) to 2.5 A typical at 175°C where thermal

latch-OFF will occur. See Figure 7, page 8.

Analog Integrated Circuit Device Data

8Freescale Semiconductor

33886

TIMING DIAGRAMS

Figure 4. Output Delay Time

Figure 5. Disable Delay Time

Figure 6. Output Switching Time

Figure 7. Active Current Limiting Versus Temperature (Typical)

TIME

5.0

VPWR td(ON)

50%

90%

50%

10%

IN1

IN2

(V)

td(OFF)

OUT1

(V)

∞Ω

0 V

5.0 V

0Ω

VPWR 90%

10%

OUT1

(V)

10%

90%

MAX

,OUTPUTCURRENT(A)

6.6

2.5

160 175

Thermal Shutdown

TJ, JUNCTION TEMPERATURE (oC)

ILIM,

6.5

LIM

CURRENT (A)

Analog Integrated Circuit Device Data

Freescale Semiconductor 9

33886

TIMING DIAGRAMS

Figure 8. Active Current Limiting Versus Time

Figure 9. Active Current Limiting Detail

D1,LOGICIN

[0]

[1]

Hard Short Detect and Latch-OFF

Typ. Short Ckt. Detect Threshold

PWM

Current

Limiting

(See Figure 6)

8.0

6.5

LOAD

,OUTPUTCURRENT(A)

FS,LOGICOUT

Outputs

Tristated

D2,LOGICIN

[0]

[1]

INn,LOGICIN

[0]

[1]

IN1 IN2

IN2IN1

Outputs Operational

(per Input Control Condition)

Typ. Current Limit Threshold

Outputs

Tristated

IN2 IN1OR

OR IN1OR IN2

IN2ORIN1

Diode Reverse

Recovery Spikes

(See Figure 7)

ISCL Short Circuit Detect Threshold

for Low-Side FETs

Typical Current Limiting Threshold

Load Capacitance and/or

Diode Reverse Recovery Spikes

Hard Short Detect and Latch-O ff

IN1 or IN2 IN2 or IN1

IN1 or IN2

IN2 or IN1

IN1 IN2

Outputs

Tri-stated Outputs

Tri-stated

Outputs Operational

(per Input Control Condition)

SF IOUT,

Active

Current

Limiting

(See Figure 7)

IOUT, CURRENT (A)

Overcurrent Minimum Threshold

tatb

8.0

TIME

LOAD

,OUTPUTCURRENT(A)

Typical PWMLoad

Current Limiting

Waveform

Hard Output

Short Latch-OFF

ta= Tristate Output OFF Time

tb= Current Limit Blank Time

6.5

Hard Short Detect

Latch-Off Prevented During tb

Short Circuit Detect Threshold

ta = Output Latch-OFF Time

tb = Output Blanking Time

ISCL Short Circuit Detect Threshold

IOUT, CURRENT (A)

Typical Current

Limiting Waveform

Analog Integrated Circuit Device Data

10 Freescale Semiconductor

33886

TYPICAL SWITCHING WAVEFORMS

Important For al l plots, the following applies:

•Ch2 = 2.0 A per divisi on

•L

LOAD = 533 µH @ 1.0 kHz

•L

LOAD = 530 µH @ 10.0 kHz

•R

LOAD = 4.0 Ω

Figure 10. Output Voltage and Current vs. Input Voltage

at V+ = 24 V, PMW Frequency of 1.0 kHz,

and Duty Cycle of 10%

Figure 11. Output Voltage and Current vs. Input Voltage

at V+ = 24 V, PMW Frequency of 1.0 kHz,

and Duty Cycle of 50%

Figure 12. Output Voltage and Current vs. Input Voltage

at V+ = 34 V, PMW Frequency of 1.0 kHz,

and Duty Cycle of 90%, Showing Device in

Current Limiting Mode

Figure 13. Output Voltage and Current vs. Input Voltage

at V+ = 22 V, PMW Frequency of 1.0 kHz,

and Duty Cycle of 90%

V+=24 V fPWM=1.0 kHz Duty Cycle=10%

IOUT

Output Voltage

(OUT1)

Input Voltage

(IN1)

V+=24V fPWM=1.0 kHz Duty Cycle=50%

IOUT

Output Voltage

(OUT1)

Input Voltage

(IN1)

V+=34 V fPWM=1.0 kHz Duty Cycle=90%

Output Voltage

(OUT1)

IOUT

Input Voltage

(IN1)

V+=22V f

PWM

=1.0 kHz Duty Cycle=90%

OUT

Output Voltage

(OUT1)

Input Voltage

(IN1)

Analog Integrated Circuit Device Data

Freescale Semiconductor 11

33886

TYPICAL SWITCHING WAVEFORMS

Figure 14. Output Voltage and Current vs. Input Voltage

at V+ = 24 V, PMW Frequency of 10 kHz,

and Duty Cycle of 50%

Figure 15. Output Voltage and Current vs. Input Voltage

at V+ = 24 V, PMW Frequency of 10 kHz,

and Duty Cycle of 90%

Figure 16. Output Voltage and Current vs. Input Voltage

at V+ = 12 V, PMW Frequency of 20 kHz,

and Duty Cycle of 50% for a Pur ely Resistive Load

Figure 17. Output Voltage and Current vs. Input Voltage

at V+ = 12 V, PMW Frequency of 20 kHz,

and Duty Cycle of 90% for a Pur ely Resistive Load

V+=24V fPWM=10 kHz Duty Cycle=50

Output Voltage

(OUT1)

IOUT

Input Voltage

(IN1)

V+=24V fPWM=10 kHz Duty Cycle=90

Output Voltage

(OUT1)

IOUT

Input Voltage

(IN1)

V+=12V fPWM=20 kHz Duty Cycle=50

Output Voltage

(OUT1)

IOUT

Input Volt age

(IN1)

V+=12 V fPWM=20 kHz Duty Cycle=90

Output Voltage

(OUT1)

IOUT

Input Voltage

(IN1)

Analog Integrated Circuit Device Data

12 Freescale Semiconductor

33886

TYPICAL SWITCHING WAVEFORMS

Table 5. Truth Table

The tri-state conditions and the fault status are reset using D1 or D2. The truth table uses the following notations: L = Low,

H = High, X = High or Low, and Z = High impedance (all output power transistors are switched off).

Device State Input Conditions Fault Status

Flag Output States

D1 D2 IN1 IN2 FS OUT1 OUT2

Forward L H H L H H L

Reverse L H L H H L H

Freewheeling Low L H L L H L L

Freewheeling High L H H H H H H

Disable 1 (D1) H X X X L Z Z

Disable 2 (D2)X L X X L Z Z

IN1 Disconnected L H Z X H H X

IN2 Disconnected L H X Z H X H

D1 Disconnected Z X X X L Z Z

D2 Disconnected X Z X X L Z Z

Undervoltage (28) X X X X L Z Z

Overtemperature (29) X X X X L Z Z

Short Circuit (29) X X X X L Z Z

Notes

28. In the case of an undervoltage condition, the outputs tri-state and the fau lt status is set logic Low. Upon undervoltage recovery, fault

status is reset automatically or automatically cleared and the outputs are restored to their original operating condition.

29. When a short circuit or overtemperature condition is detected, the power outputs are tri-state latched-OFF independent of the input

signals and the fault status flag is set logic Low.

Analog Integrated Circuit Device Data

Freescale Semiconductor 13

33886

ELECTRICAL PERFORMANCE CURVES

Figure 18. Typical High-Side RDS(ON) Versus V+

Figure 19. Typical Low-Side RDS(ON) Versus V+

59117131519 3733 35 3927 412917 21 23 25 31

0.0

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

Volts

Ohms

59117131519 3733 35 3927 412917 21 23 25 31

0.13

0.128

0.126

0.124

0.122

0.12

OHMS

PWR

Ohms

Volts

Analog Integrated Circuit Device Data

14 Freescale Semiconductor

33886

ELECTRICAL PERFORMANCE CURVES

Figure 20. Typical Quiescent Supply Current Versus V+

59117131519 3733 35 3927 412917 21 23 25 31

5.0

4.0

3.0

2.0

1.0

0.0

OHMS

PWR

6.0

7.0

8.0

9.0

milli amperes

Volts

Analog Integrated Circuit Device Data

Freescale Semiconductor 15

33886

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

Numerous protection and operational features (speed,

torque, direction, dynamic braking, and PWM control), in

addition to the 5.0 A current capability, make the 33886 a

very attractive, cost-effective solution for controlling a broad

range of fractional horsepower DC moto rs. A pair of 33886

devices can be used to control bipolar stepper motors in both

directions. In addition, the 3388 6 can be used to control

permanent magnet solenoids in a push-pul l variable force

fashion using PWM control. The 33886 can also be used to

excite transformer primary windings with a switched square

wave to produce secondary winding AC currents.

As shown in Figure 2, Simplified Internal Block Diagram,

page 2, the 33886 is a fully protected monolithic H-Bridge

with Fault Status reporting. For a DC motor to run the input

conditions need be as follow s: D1 inp ut logic Low , D2 input

logic High, FS flag cleared (logic High), with one IN logic Low

and the other IN logic High to define output polarity. The

33886 can execute dynamic braking by simultaneously

turning on either both high-side MOSFETs or both low-side

MOSFETs in the output H-Bridge; e.g., IN1 and IN2 logic

High or IN1 and IN2 logic Low.

The 33886 outputs are capable of providing a continuous

DC load current of 5.0 A from a 40 V V+ source. An internal

charge pump supports PWM frequencies up to 10 kHz. An

external pull-up resistor is required for the open drain FS pin

for fault status reporting.

Two independent inputs (IN1 and IN2) provide co ntrol of

the two totem-pole half-bridge outputs. Two disabl e inputs

(D1 and D2) are for forcing the H-Bridge outputs to a high

impedance state (all H-Bridge switches OFF).

The 33886 has undervoltage shutdown with automatic

recovery, active current limiting, output short-circuit latch-

OFF, and overtemperature latch-OFF. An undervoltage

shutdown, output short circuit latch-OFF, or overtemperat ure

latch-OFF fault condition will cause the outputs to turn OFF

(i.e., become high impedance or tri-stated) and the fault

output flag to be set Low. Either of the Disable inputs or V+

must be “toggled” to clear the fault flag.

The short circuit / overtemperature shutdown scheme is

unique and best described as using a junction temperature-

dependent active current “fold back” protection scheme.

When a short circuit condition is experienced, the current

limited output is “ramped down” as the junction temperature

increases above 160°C, until at 175°C the current has

decreased to about 2.5 A. Above 175°C, overtemperature

shutdown (latch-OFF) occurs. This feature allows the device

to remain in operation for a longer time with unexpected

loads, while still retaining adequate protection for both the

device and the load.

FUNCTIONAL PIN DESCRIPTION

POWER/ANALOG GROUNDS (PGND AND AGND)

Power and analog ground pins. The power and analog

ground pins should be connected togeth er with a very low

impedance connection.

POSITIVE POWER SUPPLY (V+)

V+ pins are the power supply inputs to the device. All V+

pins must be connected together on the printed circuit board

with as short as possible traces offering as low impedance as

possible between pins.

V+ pins have an undervoltage threshold. If the supply

voltage drops below a V+ undervoltage threshold, the output

power stage switches to a tri-state condition and the fault

status flag is set and the Fault St atus pin voltage switched to

a logic Low . When the supply voltage returns to a level that is

above the threshold, the power stage automatically resumes

normal operation according to the established condition of

the input pins and the fault stat us flag is automatically reset

logic High.

FAULT STATUS (FS)

This pin is the device fault status output. This output is an

active Low open drain structure requiring a pull-up resistor to

5.0 V. Refer to Table 5, Truth Table, page 12.

LOGIC INPUT 1, 2 AND DISABLE1, 2 (IN1, IN2, D1,

AND D2)

These pins are input control pins used to control the

outputs. These pins are 5.0 V CMOS-compatible inputs with

hysteresis. The IN1 and IN2 independently control OUT1 and

OUT2, respectively. D1 and D2 are complimentary inputs

used to tri-state disable the H-Bridge outputs.

When either D1 or D2 is set (D1 = logic High or D2 = logic

Low) in the disable state, outputs OUT1 and OUT2 are both

tri-state disabled; however, the rest of the device circuitry is

fully operational and the supply IQ (standby) current is reduced

to a few milliamperes. Refer to Table 5, Truth Table, and

Static Electrical Characteristics table, page 5.

Analog Integrated Circuit Device Data

16 Freescale Semiconductor

33886

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

H-BRIDGE OUTPUT 1, 2 (OUT1 AND OUT2)

These pins are the outputs of the H-Bridge with integrated

output FET body diodes. The bridge output is controlled using

the IN1, IN2, D1, and D2 inputs. The outputs have active

current limiting above 6.5 A. The outputs also have therma l

shutdown (tri-state latch-OFF) with hysteresis as well as

short circuit latch-OFF protection.

A disable timer (time t b) incorporated to detect currents

that are hig her than active current limit is activated at each

output activation to facilitate detecting hard output short

conditions (see Figure 9, page 9).

CHARGE PUMP CAPACITOR (CCP)

Charge pump output pin. A filter capacitor (up to 33 nF)

can be connected from the CCP pin and PGND. The device

can operate without the external capacitor , although the CCP

capacitor helps to reduce noise and allows the device to

perform at maximum speed, timing, and PWM frequency.

Analog Integrated Circuit Device Data

Freescale Semiconductor 17

33886

FUNCTIONAL DEVICE OPERATION

FUNCTIONAL PIN DESCRIPTION

FUNCTIONAL DEVICE OPERATION

SHORT CIRCUIT PROTECTION

If an output short circuit condition is detected, the power

outputs tri-state (latch-OFF) independent of the input (IN1

and IN2) states, and the fault status output flag is set logic

Low. If the D1 input changes from logic High to logic Low, or

if the D2 input changes from logic Low to logic High, the

output bridge will become operati onal again and the fault

status flag will be reset (cleared) to a logic High state.

The output stage will always switch into the mode defined

by the input pins (IN1, IN2, D1, and D2), provided the device

junction temperature is wit hin the specified operating

temperature.

ACTIVE CURRENT LIMITING

The maximum current flow under normal operating

conditions is internally limited to ILIM (5.2 A to 7.8 A). When

the maximum current value is reached, the output stages are

tri-stated for a fixed time (t a) of 20 µs typical. Depending on

the time constant associated with the load characteristics, the

current decreases during the tri-state duration until the next

output ON cycle occurs (see Figures 9 and 12, page 9 and

page 10, respectively).

The current limiting threshold value is dependent upon the

device junction temperature. When -40°C < TJ < 160°C, ILIM

is between 5.2 A and 7.8 A. When TJ exceeds 160°C, the ILIM

current decreases linearly down to 2.5 A typical at 175°C.

Above 175°C the device overtemperature circuit detects TLIM

and overtemperature shutdown occurs (see Figure 7,

page 8). This feature allows the device to remain operational

for a longer time but at a regressing output performance level

at junction temperatures above 160°C.

OVERTEMPERATURE SHUTDOWN AND

HYSTERESIS

If an overtemperature condition occurs, the power outputs

are tri-state (latched-OFF) independent of the input signals

and the fault statu s fl ag is se t lo gi c Lo w .

To reset from this condition, D1 must change from logic

High to logic Low , or D2 must change from logic Low to logic

High. When reset, the output stage switches ON again,

provided that the junction temperature is now below the

overtemperature threshold limit minus the hysteresis.

Note Resetting from the fault condition will clear the fault

status flag.

MAIN DIFFERENCES COMPARED TO

MC33186DH1

• COD pin has been removed. Pin 8 is now a Do Not

Connect (DNC) pin.

• Pin 20 is no longer connected in the 20 HSOP package. It

is now a DNC pin.

•R

DS(ON) max at TJ = 150°C is now 225 mΩ per each output

transistor.

• Maximum temperature operation is now 160°C, as

minimum thermal shutdown temperature has increased .

• Current regulation limiting foldback is implemented above

160°C TJ.

• Thermal resistance junction to case has been increased

from ~2.0°C/W to ~5.0°C/W.

Analog Integrated Circuit Device Data

18 Freescale Semiconductor

33886

FUNCTIONAL DEVICE OPERATION

PERFORMANCE

The 33886 is designed for enhanced thermal

performance. The significa nt f eature of this device is the

exposed copper pad on which the power die is soldered. This

pad is soldered on a PCB to provide heat flow to ambient and

also to provide thermal capacitan ce. The more copp er ar ea

on the PCB, the better the power dissipation and transient

behavior will be.

Example Characterization on a double-sided PCB:

bottom side area of copper is 7.8 cm2; top surface is 2.7 cm2

(see Figure 21); grid array of 24 vias 0.3 mm in diameter.

Figure 21. PCB Test Layout

Figure 22 shows the thermal response with the device

soldered on to the test PCB described in Figure 21.

Figure 22. 33886 Thermal Response

Top Side Bottom Side

0,1

100

0,001 0,01 0,1 1 10 100 1000 10000

t, Time (s)

Rth (°C/W)

Analog Integrated Circuit Device Data

Freescale Semiconductor 19

33886

TYPICAL APPLICATIONS

A typical application schematic is shown in Figure 23. For

precision high-current applications in harsh, noisy environments, the V+ by-pass capacitor may need to be

substantially larger.

Figure 23. 33886 Typical Application Schematic

MOTOR

AGND

OUT1

PGND

V+

CCP

OUT2

IN1

IN2

33 nF 47 µF

V+

33886

IN2

IN1

Analog Integrated Circuit Device Data

20 Freescale Semiconductor

33886

PACKAGING

PACKAGE DIMENSIONS

PACKAGING

PACKAGE DIMENSIONS

Important For the most cur rent revision of the package, visit www.freescale.com and perform a keyword search on 98ASH70702A listed

below.

SEATING

PLANE

DATUM

PLANE

BOTTOM VIEW

X 45

18X

bbb C

NOTES:

1. CONTROLLING DIMENSION: MILLIMETER.

2. DIMENSIONS AND TOLERANCES PER ASME

Y14.5M, 1994.

3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE.

4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.150 PER SIDE. DIMENSIONS D AND E1 DO

INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE –H–.

5. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS

OF THE b DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. DATUMS –A– AND –B– TO BE DETERMINED AT

DATUM PLANE –H–.

7. DIMENSION D DOES NOT INCLUDE TIEBAR

PROTRUSIONS. ALLOWABLE TIEBAR

PROTRUSIONS ARE 0.150 PER SIDE.

ÇÇÇ

ÉÉÉ

SECTION W–W

aaa C

EXPOSED

HEATSINK AREA

PIN ONE ID

10X

GAUGE

PLANE

DETAIL Y

(1.600)

bbb C

DIM MIN MAX

MILLIMETERS

A3.000 3.400

A1 0.100 0.300

A2 2.900 3.100

A3 0.00 0.100

D15.800 16.000

D1 11.700 12.600

D2 0.900 1.100

E13.950 14.450

E1 10.900 11.100

E2 2.500 2.700

E3 6.400 7.200

E4 2.700 2.900

L0.840 1.100

L1 0.350 BSC

b0.400 0.520

b1 0.400 0.482

c0.230 0.320

c1 0.230 0.280

e1.270 BSC

h––– 1.100

0 8

aaa 0.200

bbb 0.100

e/2

DH SUFFIX

VW (Pb-FREE) SUFFIX

20-PIN HSOP

PLASTIC PACKAGE

98ASH70702A

ISSUE A

Analog Integrated Circuit Device Data

Freescale Semiconductor 21

33886

5.0 A H-BRIDGE

THERMAL ADDENDUM - REVISION 2.0

5.0 A H-BRIDGE

THERMAL ADDENDUM - REVISION 2.0

Introduction

This thermal addendum is provided as a supplement to the MC33186

technical data sheet. The addendum provides thermal performance information

that may be critical in the design and development of system applications. All

electrical, applica tio n, and packaging info rmation is provided in the data sheet.

Packaging and Therma l Considerations

The MC33186 is offered in a 20 pin HSOP exposed pad, single die package.

There is a single heat source (P), a single junction temperature (TJ), and thermal

resistance (RθJA).

The stated values are solely for a thermal performance comparison of one

package to another in a standardized environment. This methodology is not

meant to and will not predict the performance of a package in an application-

specific environment. Stated values were obtained by measurement and

simulation according to the standards listed below.

Standards

NOTES:

1.Per JEDEC JESD51-2 at natural convection, still air condition.

2.2s2p thermal test board per JEDEC JESD51-5 and JESD51-7.

3.Per JEDEC JESD51-8, with the board temperature on the center

trace near the center lead.

4.Single layer thermal test board per JEDEC JESD51-3 and

JESD51-5.

5.Thermal resistance between the die junction and the exposed

pad surface; cold plate attached to the package bottom side,

remaining surfaces insulated. Figure 24. Thermal Land Pattern for Direct Thermal

Attachment According to JESD51-5

20-PIN

HSOP-EP

33886

Note For package dimensions, refer to

the 33886 device data sheet.

DH SUFFIX

VW (Pb-FREE) SUFFIX

98ASH70702A

20-PIN HSOP-EP

TJ=RθJA .P

Table 6. Thermal Performance Comparison

Thermal Resistance [°C/W]

RθJA(1)(2) 20

RθJB(2)(3) 6.0

RθJA(1)(4) 52

RθJC(5) 1.0

1.0

0.2

Soldermast

openings

Thermal vias

connected to top

buried plane

* All measurements

are in millimeters

20 Terminal HSOP-EP

1.27 mm Pitch

16.0 mm x 11.0 mm Body

12.2 mm x 6.9 mm Exposed Pad

Analog Integrated Circuit Device Data

22 Freescale Semiconductor

33886

5.0 A H-BRIDGE

THERMAL ADDENDUM - REVISION 2.0

Figure 25. Thermal Test Board

Device on Thermal Test Board

RθJA is the thermal resistance between die junction and

ambient air.

RθJS is the thermal resistance between die junction and the

reference location on the board surface n ear a center lead of the

package (see Figure 25).

20-Pin HSOP

1.27 mm Pitch

16.0 mm x 11.0 mm Body

12.2 mm x 6.9 mm Exposed Pad

DNCAGND IN2

CCP

V+

OUT2

PGND

V+

OUT1

DNC

PGND

IN1

V+

33886 Pin Connections

Material: Single layer printed circuit board

FR4, 1.6 mm thickness

Cu traces, 0.07 mm thickness

Outline: 80 mm x 100 mm board area,

including edge connector for thermal

testing

Area A:Cu heat-spreading areas on board

surface

Ambient Conditions : Natural convection, still air

Table 7. Thermal Resistance Performance

Thermal

Resistance Area A (mm2)°C/W

RθJA 0.0 52

300 36

600 32

RθJS 0.0 10

300 7.0

600 6.0

Analog Integrated Circuit Device Data

Freescale Semiconductor 23

33886

5.0 A H-BRIDGE

THERMAL ADDENDUM - REVISION 2.0

Figure 26. Device on Thermal Test Board RθJA

Figure 27. Transient Thermal Resistance RθJA

Device on Thermal Te st Board Area A = 600 (mm2)

H eat spr eading ar ea A [mm²]

Therm al Resistance [ºC/W

]

0 300 600

0.1

100

1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04

time[s]

T her m al Res istanc e [º C/W]

Time(s)

Analog Integrated Circuit Device Data

24 Freescale Semiconductor

33886

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES

7.0 7/2005 • Implemented Revision History page

• Added Thermal Addendum

• Converted to Freescale format

8.0 2/2007 • Updated data sheet format

• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from

Maximum Ratings on page 4. Added note with instructions to obtain this information from

www.freescale.com.

MC33886

Rev 8.0

2/2007

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