R5S72030W200FP - Renesas Electronics

To our customers,

Old Company Name in Catalogs and Other Documents

On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both

companies. Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1st, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is

subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please

confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to

additional and different information to be disclose d by Renesa s Electronics such as that disclosed through our website.

2. Renesas Electronics does not assum e any liability for inf ringement of patents, co pyrights, or other int ellectual property rights

of third parties by or arising from the use of Renesas Elec tronics products or technical information described in this document.

No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights

of Renesas Electronics or others.

3. You should not alter, m odify, copy, or otherw ise misappropriate an y Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of

semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,

and information in the design of your equipment. Renesas Electronics assumes no responsi bility for any losse s incurred by

you or third parties arising from the use of these circuits, software, or information.

5. When exporting the products or technol ogy described in this document, you should comply with the applicable export control

laws and regulations and follow the procedures required by such law s and regulations. You should not use Renesas

Electronics products or the technology described in this docum ent for any purpose rela ting to military applications or use by

the military, including but not limited to the developm ent of weapons of ma ss destruction. Renesas Electronics products and

technology may not be used for or incor porated into any products or system s whose manufac ture, use, or sale is prohibited

under any applicable domestic or foreign laws or regulations.

6. Renesas Electronics has used reasonable care in prepa ring the information included in this document, but Renesas Electronics

does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages

incurred by you resulting from errors in or omissions from the information included herein.

7. Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and

“Specific”. The recom mended applicatio ns for each Renesas Electronics prod uct depends on the produc t’s quality grade, as

indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular

application. You may not use any Renesas Elec tronics product for any application cate gorized as “Spec ific” without the prior

written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any applic ation for

which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way

liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an

application categorized as “Specific” or for which the product is not intende d where you have failed to obtain the prior written

consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise

expressly specified in a Renesas Electronics data sheets or data books, etc.

“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual

equipment; home electronic appli ances; mac hine tools; personal electronic equipm ent; and industrial robots.

“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-

crime systems; safety equipment; and medical equipment not specifically designed for life support.

“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or

systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare

intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,

especially with respect to the m aximum rating , opera ting supply voltag e range, movement power voltage ra nge, heat radiation

characteristics, installation and other product characteristic s. Re nesas Electronics shall have no liabil ity for malfunctions or

damages arising out of the use of Re nesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliabili ty of its products, semiconductor products have

specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,

Renesas Electronics products are not subject to radiation res istance design. Pleas e be sure to implement saf ety measures to

guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a

Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire

control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because

the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system

manufactured by you.

10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental

compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable

laws and regulations that regulate the inclusion or use of controlled substa nces, including without lim itation, the EU R oHS

Directive. Renesas Electronics assum es no liability for damage s or losses occurring as a result of your noncom pliance with

applicable laws and regulatio ns.

11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas

Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions re garding the information conta ined in this

document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-

owned subsidiaries.

(Note 2) “Re nesas Electronics produc t(s)” means any product develope d or manufactured by or for Re nesas Electronics.

SH-2A, SH2A-FPU

Software Manual

User’s Manual

Rev.3.00 2005.07

Renesas 32-Bit RISC

Microcomputer

SuperHTM RISC engine Family

Rev. 3.00 Jul 08, 2005 page ii of xiv

1. These materials are intended as a reference to assist our customers in the selection of the Renesas

Technology Corp. product best suited to the customer's application; they do not convey any license

under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or

a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-

party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or

circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and

algorithms represents information on products at the time of publication of these materials, and are

subject to change by Renesas Technology Corp. without notice due to product improvements or

other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or

an authorized Renesas Technology Corp. product distributor for the latest product information

before purchasing a product listed herein.

The information described here may contain technical inaccuracies or typographical errors.

Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising

from these inaccuracies or errors.

Please also pay attention to information published by Renesas Technology Corp. by various means,

including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data,

diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total

system before making a final decision on the applicability of the information and products. Renesas

Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the

information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or

system that is used under circumstances in which human life is potentially at stake. Please contact

Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when

considering the use of a product contained herein for any specific purposes, such as apparatus or

systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in

whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must

be exported under a license from the Japanese government and cannot be imported into a country

other than the approved destination.

Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the

country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products

contained therein.

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and

more reliable, but there is always the possibility that trouble may occur with them. Trouble with

semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate

measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or

(iii) prevention against any malfunction or mishap.

Keep safety first in your circuit designs!

Notes regarding these materials

Rev. 3.00 Jul 08, 2005 page iii of xiv

Main Revisions for this Edition

Item Page Revision (See Manual for Details)

1.1 Features 1 Description amended

The SH-2A/SH2A-FPU is a 32-bit RISC (reduced instruction set

computer) microprocessor that is upward-compatible with the SH-

1, SH-2, and SH-2E at the object code level.

2.2.2 Control

Registers

(1) Status Register,

5 Description amended

(32-bit, initial value =0000 0000 0000 0000 00X0 00XX 1111

00XX)

3.1.1 Exception

Handling Types and

Priority

Table 3.1 Exception

Types and Priority

16 Note amended

Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR,

RTS, RTE, BF/S, BT/S, BSRF, BRAF .

3.1.2 Exception

Handling Operation

(2) Address Error,

RAM Error, Register

Bank Error, Interrupt,

or Instruction

Exception Handling

18 Description amended

⋅⋅⋅ and the vector table address offset of the interrupt exception

handling to be executed,⋅⋅⋅

3.3.1 Address Error

Sources

Table 3.5 Bus

Cycles and Address

Errors

22 Table amended

Bus Cycle

Type Bus Master Bus Cycle Operation

Address Error

Occurrence

Data

read/write

CPU or

DMAC

Double longword data accessed from double

longword boundary

No error (normal)

Double longword data accessed from other

than double longword boundary

Address error

3.6.3 Interrupt

Exception Handling

26 Description amended

⋅⋅⋅ and the vector table address offset of the interrupt exception

handling to be executed,⋅⋅⋅

Rev. 3.00 Jul 08, 2005 page iv of xiv

Item Page Revision (See Manual for Details)

4.3 Instruction

Format

Table 4.8

Instruction Formats

45 Table amended

Instruction Formats

nid format

nnnnxxxx xxxx

32 16

xiii

ddddxxxx dddd

15 0

dddd

5.1 Instruction Set

by Classification

Table 5.2

Instruction Code

Format

53 Table amended

Item Format Explanation

Instruction

Rm: Source register

Rn: Destination register

imm: Immediate data

disp: Displacement*

5.1.1 Data Transfer

Instructions

Table 5.3 Data

Transfer Instructions

56 Table amended

MOVML.L @R15+,Rn

MOVMU.L @R15+,Rn

Note: When Rn = R15, read Rn as PR

6.2 Format of

Instruction

Descriptions

76 Description amended

(VTO: Interrupt vector table address offset)

6.3.30 RESBANK

REStore from

registerBANK

System Control

Instruction

145 Note amended

* 19 when a bank overflow has occurred and the register is

restored from the stack

6.4.21 DT

Decrement and Test

Arithmetic Instruction

196 Program listing amended

DT R5

6.4.31 MOV

MOVe immediate

data

Data Transfer

Instruction

219 Description amended

⋅⋅⋅ The PC points to the starting address of the fourth byte after this

MOV instruction. ⋅⋅⋅ The PC points to the starting address of the

fourth byte after this MOV instruction,⋅⋅⋅

Rev. 3.00 Jul 08, 2005 page v of xiv

Item Page Revision (See Manual for Details)

6.4.48 RTE

ReTurn from

Exception

System Control

Instruction

244 Description amended

Return from

Exception Handling Delayed Branch Instruction

6.4.50 SETT

SET T bit

System Control

Instruction

248 Description amended

T Bit Setting

6.4.57 SLEEP

SLEEP

System Control

Instruction

257 Description amended

Transition to Power-Down Mode .

6.5.10 FLOAT

Floating-point

convert from integer

Floating-Point

Instruction

296 Description amended

⋅⋅⋅ When FPSCR.enable.I = 1, and FPSCR.PR = 0, an FPU

exception trap is generated regardless of whether or not an

exception has occurred.⋅⋅⋅

7.1 Overview

Figure 7.1 Overview

of Register Bank

Configuration

325 Figure amended

(Before) IVO → (After) VTO

Figure notes amended

VTO: Interrupt vector table address offset

7.2.1 Banked Data 326 Description amended

⋅⋅⋅ and the interrupt vector table address offsets (VTO) are banked.

7.2.2 Register

Banks

326 Description amended

⋅⋅⋅ Register banks are stacked in first in last out (FILO) sequence.⋅⋅⋅

7.2.3 Bank Control

Registers

(2) Bank Number

bit, Initial value:

H'0000)

327 Description amended

Bits 3 to 0: BN3 to BN0

⋅⋅⋅ after which the data is retrieved from the register bank. These

bits are read-only and cannot be modified.

7.3.1 Save to Bank 328 Description amended

(b) ..., and the interrupt vector table address offset (VTO) are

saved to the bank indicated by the BN, bank i.

Figure 7.2 Bank

Save Operations

Figure 7.3 Bank

Save Timing

328,

329

Figure amended

(Before) IVN → (After) VTO

Rev. 3.00 Jul 08, 2005 page vi of xiv

Item Page Revision (See Manual for Details)

7.4.2 Register Bank

Addressing

330 Description amended

⋅⋅⋅ and the entry within the bank (R0 to R14, GBR, MACH, MACL,

PR, VTO) is specified by address bits 6 to 2 (EN).

Figure 7.4 Register

Bank Addressing

331 Figure amended

(Before) IVO → (After) VTO

8.2 Slots and

Pipeline Flow

Figure 8.3

Impossible Pipeline

Flow (1)

339 Figure amended

Instruction 1 IF ID EX MA WB

8.6 Contention Due

to FPU

Figure 8.36

Example of Use of

Result of Zero-

Latency Instruction

as Source

353 Figure amended

(Before) GX → (After) EX

8.9 Pipeline

Operations for Each

Instruction

Table 8.1 Number

of Instruction Stages

and Execution States

372 Table amended

Type Category Number

of Stages

Execution

States Latency Contention Instructions

4 1 2 STS MACH,RnSystem

control

instructions

MAC →

transfer

instructions

• These instruc-

tions use the

multiplication

result read path.

STS MACL,Rn

Appendix A SH-

2A/SH2A-FPU

Parallel Execution

480,

481

Table amended

Classifi-

cation of

First

Instruction

Classifi-

cation of

Second

Instruction

MW MW STC.L VBR,@-Rn STS.L PR,@-Rn

EX EX SUBC Rm,Rn SUBV Rm,Rn TST #imm,R0

BR MR JSR/N @@(disp8,TBR)

Rev. 3.00 Jul 08, 2005 page vii of xiv

Contents

Section 1 Overview............................................................................................................. 1

1.1 Features............................................................................................................................. 1

Section 2 Programming Model........................................................................................ 3

2.1 Data Formats..................................................................................................................... 3

2.2 Register Configuration...................................................................................................... 3

2.2.1 General Registers................................................................................................. 3

2.2.2 Control Registers ................................................................................................. 5

2.2.3 System Registers.................................................................................................. 6

2.2.4 Floating-Point Registers ...................................................................................... 7

2.2.5 Floating-Point System Registers.......................................................................... 8

2.2.6 Register Banks..................................................................................................... 10

2.2.7 Register Initial Values ......................................................................................... 10

2.3 Data Formats..................................................................................................................... 11

2.3.1 Data Format in Registers ..................................................................................... 11

2.3.2 Data Formats in Memory..................................................................................... 11

2.3.3 Immediate Data Format ....................................................................................... 12

2.4 Processing States .............................................................................................................. 13

Section 3 Exception Handling ......................................................................................... 15

3.1 Overview .......................................................................................................................... 15

3.1.1 Exception Handling Types and Priority............................................................... 15

3.1.2 Exception Handling Operation ............................................................................ 17

3.1.3 Exception Vector Table ....................................................................................... 18

3.2 Resets................................................................................................................................ 20

3.2.1 Types of Reset ..................................................................................................... 20

3.2.2 Power-On Reset................................................................................................... 20

3.2.3 Manual Reset ....................................................................................................... 21

3.3 Address Errors .................................................................................................................. 22

3.3.1 Address Error Sources ......................................................................................... 22

3.3.2 Address Error Exception Handling...................................................................... 23

3.4 RAM Errors ...................................................................................................................... 23

3.4.1 RAM Error Sources ............................................................................................. 23

3.4.2 RAM Error Exception Handling.......................................................................... 23

3.5 Register Bank Errors.........................................................................................................24

3.5.1 Register Bank Error Sources................................................................................ 24

3.5.2 Register Bank Error Exception Handling ............................................................ 24

3.6 Interrupts........................................................................................................................... 25

Rev. 3.00 Jul 08, 2005 page viii of xiv

3.6.1 Interrupt Sources.................................................................................................. 25

3.6.2 Interrupt Priority .................................................................................................. 25

3.6.3 Interrupt Exception Handling .............................................................................. 26

3.7 Instruction Exceptions ...................................................................................................... 27

3.7.1 Types of Instruction Exception............................................................................ 27

3.7.2 Trap Instruction ................................................................................................... 28

3.7.3 Slot Illegal Instructions........................................................................................ 28

3.7.4 General Illegal Instructions.................................................................................. 29

3.7.5 Integer Division Instructions ............................................................................... 29

3.7.6 Floating-Point Operation Instructions.................................................................. 29

3.8 Cases in Which Exceptions Are Not Accepted................................................................. 30

3.9 Stack Status after Exception Handling.............................................................................. 31

3.10 Usage Notes...................................................................................................................... 32

3.10.1 Stack Pointer (SP) Value ..................................................................................... 32

3.10.2 Vector Base Register (VBR) Value ..................................................................... 32

3.10.3 Address Errors Occurring in Address Error Exception Handling Stacking......... 32

Section 4 Instruction Features ......................................................................................... 33

4.1 RISC-Type Instruction Set................................................................................................ 33

4.2 Addressing Modes ............................................................................................................ 37

4.3 Instruction Format............................................................................................................. 41

Section 5 Instruction Set.................................................................................................... 47

5.1 Instruction Set by Classification ....................................................................................... 47

5.1.1 Data Transfer Instructions ................................................................................... 54

5.1.2 Arithmetic Operation Instructions ....................................................................... 58

5.1.3 Logic Operation Instructions ............................................................................... 61

5.1.4 Shift Instructions.................................................................................................. 62

5.1.5 Branch Instructions.............................................................................................. 63

5.1.6 System Control Instructions................................................................................. 64

5.1.7 Floating-Point Instructions .................................................................................. 66

5.1.8 FPU-Related CPU Instructions............................................................................ 68

5.1.9 Bit Manipulation Instructions .............................................................................. 69

Section 6 Instruction Descriptions.................................................................................. 71

6.1 Overview of New Instructions.......................................................................................... 71

6.2 Format of Instruction Descriptions ................................................................................... 75

6.3 New Instructions............................................................................................................... 88

6.3.1 BAND......... Bit AND ...................................... Bit Manipulation Instruction ... 88

6.3.2 BANDNOT Bit ANDNOT .............................. Bit Manipulation Instruction ... 90

6.3.3 BCLR ......... Bit CLeaR .................................... Bit Manipulation Instruction ... 92

Rev. 3.00 Jul 08, 2005 page ix of xiv

6.3.4 BLD ........... Bit LoaD ...................................... Bit Manipulation Instruction ... 94

6.3.5 BLDNOT ... Bit LoaDNOT .............................. Bit Manipulation Instruction ... 96

6.3.6 BOR ........... Bit OR ......................................... Bit Manipulation Instruction ... 98

6.3.7 BORNOT ... Bit ORNOT ................................. Bit Manipulation Instruction ... 100

6.3.8 BSET ......... Bit SET ........................................ Bit Manipulation Instruction ... 102

6.3.9 BST ............ Bit STore ..................................... Bit Manipulation Instruction ... 104

6.3.10 BXOR ........ Bit exclusive OR ......................... Bit Manipulation Instruction ... 106

6.3.11 CLIPS ........ CLIP as Signed ............................ Arithmetic Instruction ............. 108

6.3.12 CLIPU ........ CLIP as Unsigned ........................ Arithmetic Instruction ............. 111

6.3.13 DIVS .......... DIVide as Signed ........................ Arithmetic Instruction ............. 113

6.3.14 DIVU ......... DIVide as Unsigned .................... Arithmetic Instruction ............. 114

6.3.15 FMOV ........ Floating-point MOVe .................. Floating-Point Instruction........ 115

6.3.16 JSR/N ......... Jump to SubRoutine with No delay slot

...................................................... Branch Instruction ................... 118

6.3.17 LDBANK ... LoaD register BANK .................. System Control Instruction...... 121

6.3.18 LDC ........... LoaD to Control register ............. System Control Instruction...... 123

6.3.19 MOV .......... MOVe structure data ................... Data Transfer Instruction......... 124

6.3.20 MOV .......... MOVe reverse stack .................... Data Transfer Instruction......... 127

6.3.21 MOVI20 .... MOVe Immediate 20bits data ..... Data Transfer Instruction......... 130

6.3.22 MOVI20S .. MOVe Immediate 20bits data and 8bits Shift left

...................................................... Data Transfer Instruction......... 131

6.3.23 MOVML.L MOVe Multi-register Lower part Data Transfer Instruction......... 133

6.3.24 MOVMU.L MOVe Multi-register Upper part Data Transfer Instruction......... 136

6.3.25 MOVRT ..... MOVe Reverse Tbit .................... Data Transfer Instruction......... 139

6.3.26 MOVU ....... MOVe structure data as Unsigned

...................................................... Data Transfer Instruction......... 140

6.3.27 MULR ........ MULtiply to Register .................. Arithmetic Instruction ............. 142

6.3.28 NOTT ........ NOT Tbit ..................................... Data Transfer Instruction......... 143

6.3.29 PREF .......... PREFetch data to cache ............... Data Transfer Instruction......... 144

6.3.30 RESBANK REStore from registerBANK ...... System Control Instruction...... 145

6.3.31 RTS/N ........ ReTurn from Subroutine with No delay slot

...................................................... Branch Instruction ................... 147

6.3.32 RTV/N ....... ReTurn to Value and from subroutine with No delay slot

...................................................... Branch Instruction ................... 148

6.3.33 SHAD ........ SHift Arithmetic Dynamically .... Shift Instruction....................... 150

6.3.34 SHLD ......... SHift Logical Dynamically ......... Shift Instruction....................... 152

6.3.35 STBANK ... STore register BANK .................. System Control Instruction...... 154

6.3.36 STC ............ STore Control register ................. System Control Instruction...... 156

6.4 SH-2E CPU Instructions................................................................................................... 157

6.4.1 ADD .......... ADD Binary ................................ Arithmetic Instruction ............. 157

6.4.2 ADDC ........ ADD with Carry .......................... Arithmetic Instruction ............. 158

Rev. 3.00 Jul 08, 2005 page x of xiv

6.4.3 ADDV ........ ADD with (V flag) overflow check

...................................................... Arithmetic Instruction ............. 159

6.4.4 AND .......... AND logical ................................ Logical Instruction................... 161

6.4.5 BF .............. Branch if False ............................ Branch Instruction ................... 163

6.4.6 BF/S ........... Branch if False with delay Slot ... Branch Instruction ................... 165

6.4.7 BRA ........... BRAnch ....................................... Branch Instruction ................... 167

6.4.8 BRAF ......... BRAnch Far ................................ Branch Instruction ................... 169

6.4.9 BSR ............ Branch to SubRoutine ................. Branch Instruction ................... 171

6.4.10 BSRF ......... Branch to SubRoutine Far ........... Branch Instruction ................... 173

6.4.11 BT .............. Branch if True ............................. Branch Instruction ................... 175

6.4.12 BT/S ........... Branch if True with delay Slot .... Branch Instruction ................... 177

6.4.13 CLRMAC .. CleaR MAC register .................... System Control Instruction...... 179

6.4.14 CLRT ......... CleaR T bit .................................. System Control Instruction...... 180

6.4.15 CMP/cond .. CoMPare conditionally ............... Arithmetic Instruction ............. 181

6.4.16 DIV0S ........ DIVide (step 0) as Signed ........... Arithmetic Instruction ............. 185

6.4.17 DIV0U ....... DIVide (step 0) as Unsigned ....... Arithmetic Instruction ............. 186

6.4.18 DIV1 .......... DIVide 1 step .............................. Arithmetic Instruction ............. 187

6.4.19 DMULS.L .. Double-length MULtiply as Signed

...................................................... Arithmetic Instruction ............. 192

6.4.20 DMULU.L Double-length MULtiply as Unsigned

...................................................... Arithmetic Instruction ............. 194

6.4.21 DT .............. Decrement and Test ..................... Arithmetic Instruction ............. 196

6.4.22 EXTS ......... EXTend as Signed ....................... Arithmetic Instruction ............. 197

6.4.23 EXTU ........ EXTend as Unsigned ................... Arithmetic Instruction ............. 198

6.4.24 JMP ............ JuMP ........................................... Branch Instruction ................... 199

6.4.25 JSR ............. Jump to SubRoutine .................... Branch Instruction ................... 201

6.4.26 LDC ........... LoaD to Control register ............. System Control Instruction...... 203

6.4.27 LDS ............ LoaD to System register .............. System Control Instruction...... 205

6.4.28 MAC.L ....... Multiply and ACcumulate Long .. Arithmetic Instruction ............. 207

6.4.29 MAC.W ..... Multiply and ACcumulate Word Arithmetic Instruction ............. 211

6.4.30 MOV .......... MOVe data .................................. Data Transfer Instruction......... 214

6.4.31 MOV .......... MOVe immediate data ................ Data Transfer Instruction......... 219

6.4.32 MOV .......... MOVe peripheral Data ................ Data Transfer Instruction......... 222

6.4.33 MOV .......... MOVe structure data ................... Data Transfer Instruction......... 225

6.4.34 MOVA ....... MOVe effective Address ............. Data Transfer Instruction......... 228

6.4.35 MOVT ....... MOVe T bit ................................. Data Transfer Instruction......... 230

6.4.36 MUL.L ....... MULtiply Long ........................... Arithmetic Instruction ............. 231

6.4.37 MULS.W ... MULtiply as Signed Word .......... Arithmetic Instruction ............. 232

6.4.38 MULU.W ... MULtiply as Unsigned Word ...... Arithmetic Instruction ............. 233

6.4.39 NEG ........... NEGate ........................................ Arithmetic Instruction ............. 234

6.4.40 NEGC ........ NEGate with Carry ...................... Arithmetic Instruction ............. 235

Rev. 3.00 Jul 08, 2005 page xi of xiv

6.4.41 NOP ........... No OPeration ............................... System Control Instruction...... 236

6.4.42 NOT ........... NOT-logical complement ............ Logical Instruction................... 237

6.4.43 OR .............. OR logical .................................. Logical Instruction................... 238

6.4.44 ROTCL ...... ROTate with Carry Left .............. Shift Instruction ....................... 240

6.4.45 ROTCR ...... ROTate with Carry Right ............ Shift Instruction....................... 241

6.4.46 ROTL ......... ROTate Left ................................ Shift Instruction....................... 242

6.4.47 ROTR ........ ROTate Right .............................. Shift Instruction....................... 243

6.4.48 RTE ............ ReTurn from Exception ............... System Control Instruction...... 244

6.4.49 RTS ............ ReTurn from Subroutine ............. Branch Instruction ................... 246

6.4.50 SETT .......... SET T bit ..................................... System Control Instruction...... 248

6.4.51 SHAL ......... SHift Arithmetic Left .................. Shift Instruction ....................... 249

6.4.52 SHAR ........ SHift Arithmetic Right ................ Shift Instruction ....................... 250

6.4.53 SHLL ......... SHift Logical Left ....................... Shift Instruction ....................... 251

6.4.54 SHLLn ....... n bits SHift Logical Left .............. Shift Instruction....................... 252

6.4.55 SHLR ......... SHift Logical Right ..................... Shift Instruction....................... 254

6.4.56 SHLRn ....... n bits SHift Logical Right ........... Shift Instruction....................... 255

6.4.57 SLEEP ....... SLEEP ......................................... System Control Instruction...... 257

6.4.58 STC ............ STore Control register ................. System Control Instruction...... 258

6.4.59 STS ............ STore System register ................. System Control Instruction...... 260

6.4.60 SUB ........... SUBtract binary ........................... Arithmetic Instruction ............. 262

6.4.61 SUBC ......... SUBtract with Carry .................... Arithmetic Instruction ............. 263

6.4.62 SUBV ........ SUBtract with (V flag) underflow check

...................................................... Arithmetic Instruction ............. 264

6.4.63 SWAP ........ SWAP register halves .................. Data Transfer Instruction......... 266

6.4.64 TAS ............ Test And Set ................................ Logical Instruction................... 268

6.4.65 TRAPA ...... TRAP Always ............................. System Control Instruction...... 269

6.4.66 TST ............ TeST logical ................................ Logical Instruction................... 271

6.4.67 XOR ........... eXclusive OR logical .................. Logical Instruction................... 273

6.4.68 XTRCT ...... eXTRaCT .................................... Data Transfer Instruction......... 275

6.5 Floating-Point Instructions and FPU-Related CPU Instructions....................................... 276

6.5.1 FABS ......... Floating-point ABSolute value .... Floating-Point Instruction........ 276

6.5.2 FADD ........ Floating-point ADD .................... Floating-Point Instruction........ 277

6.5.3 FCMP ........ Floating-point CoMPare .............. Floating-Point Instruction........ 280

6.5.4 FCNVDS ... Floating-point CoNVert Double to Single precision

...................................................... Floating-Point Instruction........ 284

6.5.5 FCNVSD ... Floating-point CoNVert Single to Double precision

...................................................... Floating-Point Instruction........ 287

6.5.6 FDIV .......... Floating-point DIVide ................. Floating-Point Instruction........ 289

6.5.7 FLDI0 ........ Floating-point LoaD Immediate 0.0

...................................................... Floating-Point Instruction........ 293

Rev. 3.00 Jul 08, 2005 page xii of xiv

6.5.8 FLDI1 ........ Floating-point LoaD Immediate 1.0

...................................................... Floating-Point Instruction........ 294

6.5.9 FLDS ......... Floating-point LoaD to System register

...................................................... Floating-Point Instruction........ 295

6.5.10 FLOAT ...... Floating-point convert from integer

...................................................... Floating-Point Instruction........ 296

6.5.11 FMAC ........ Floating-point Multiply and ACcumulate

...................................................... Floating-Point Instruction........ 298

6.5.12 FMOV ........ Floating-point MOVe .................. Floating-Point Instruction........ 304

6.5.13 FMUL ........ Floating-point MULtiply ............. Floating-Point Instruction........ 308

6.5.14 FNEG ......... Floating-point NEGate value ....... Floating-Point Instruction........ 310

6.5.15 FSCHG ...... Sz-bit CHanGe ............................ Floating-Point Instruction........ 311

6.5.16 FSQRT ....... Floating-point SQuare RooT ....... Floating-Point Instruction........ 312

6.5.17 FSTS .......... Floating-point STore System register

...................................................... Floating-Point Instruction........ 315

6.5.18 FSUB ......... Floating-point SUBtract .............. Floating-Point Instruction........ 316

6.5.19 FTRC ......... Floating-point TRuncate and Convert to integer

...................................................... Floating-Point Instruction........ 318

6.5.20 LDS ............ LoaD to FPU System register ...... System Control Instruction...... 321

6.5.21 STS ............ STore from FPU System register System Control Instruction...... 323

Section 7 Register Banks .................................................................................................. 325

7.1 Overview .......................................................................................................................... 325

7.2 Register Banks and Bank Control Registers ..................................................................... 326

7.2.1 Banked Data ........................................................................................................ 326

7.2.2 Register Banks..................................................................................................... 326

7.2.3 Bank Control Registers........................................................................................ 326

7.3 Bank Save and Retrieve Operations ................................................................................. 328

7.3.1 Save to Bank........................................................................................................ 328

7.3.2 Retrieve from Bank.............................................................................................. 329

7.3.3 Save and Retrieve Operations after Saving to All Banks .................................... 329

7.4 Register Bank Data Send Instructions .............................................................................. 330

7.4.1 Description of Instructions .................................................................................. 330

7.4.2 Register Bank Addressing ................................................................................... 330

7.5 Register Bank Exceptions................................................................................................. 332

7.5.1 Register Bank Error Sources................................................................................ 332

7.5.2 Register Bank Error Exception Processing.......................................................... 332

7.6 SR Register Bank Overflow Bit (BO Bit)......................................................................... 333

Section 8 Pipeline Operation............................................................................................ 335

8.1 Basic Pipeline Configuration ............................................................................................ 335

Rev. 3.00 Jul 08, 2005 page xiii of xiv

8.2 Slots and Pipeline Flow .................................................................................................... 339

8.3 Instruction Execution and Parallel Execution Capability ................................................. 341

8.3.1 Details of Resource Contention ........................................................................... 342

8.3.2 Details of Contention Due to Wait for Result of Previously Issued Instruction .. 345

8.3.3 Details of Register Contention and Flag Contention ........................................... 345

8.3.4 Details of Contention Due to Multi-Cycle Instruction......................................... 347

8.3.5 Details of Contention Due to 32-Bit Instruction.................................................. 348

8.3.6 Details of Contention Due to Instruction that Uses FPSCR ................................ 349

8.3.7 Details of Contention Due to Branch Instruction................................................. 350

8.4 Number of Instruction Execution States ........................................................................... 351

8.5 Effect of Memory Load Instruction on Pipeline ............................................................... 352

8.6 Contention Due to FPU..................................................................................................... 353

8.7 Contention Due to Multiplier............................................................................................ 360

8.8 Programming Strategy ...................................................................................................... 364

8.9 Pipeline Operations for Each Instruction.......................................................................... 364

8.9.1 Data Transfer Instructions ................................................................................... 378

8.9.2 Arithmetic Operation Instructions ....................................................................... 390

8.9.3 Logical Operation Instructions ............................................................................ 404

8.9.4 Shift Instructions.................................................................................................. 412

8.9.5 Branch Instructions.............................................................................................. 414

8.9.6 System Control Instructions................................................................................. 422

8.9.7 Exception Handling ............................................................................................. 443

8.9.8 Floating-Point Instructions and FPU-Related CPU Instructions.......................... 448

8.10 Simple Method of Calculating Required Number of Clock Cycles.................................. 475

Appendix A SH-2A/SH2A-FPU Parallel Execution................................................. 479

Appendix B Programming Guidelines (Using MOVI20 and MOVI20S) .......... 483

Rev. 3.00 Jul 08, 2005 page xiv of xiv

Section 1 Overview

Rev. 3.00 Jul 08, 2005 page 1 of 484

REJ09B0051-0300

Section 1 Overview

1.1 Features

The SH-2A/SH2A-FPU is a 32-bit RISC (reduced instruction set computer) microprocessor that is

upward-compatible with the SH-1, SH-2, and SH-2E at the object code level. The SH2A-FPU has

an on-chip floating point unit and the SH-2A does not. The use of 16-bit basic instructions enables

code efficiency, performance, and ease of use to be improved.

Features of the SH-2A/SH2A-FPU are summarized in table 1.1.

Table 1.1 SH-2A/SH2A-FPU Features

Item Features

CPU • Original Renesas Technology architecture

• 32-bit internal data bus

• General-register architecture

 Sixteen 32-bit general registers

 Four 32-bit control registers

 Four 32-bit system registers

 Register banks for fast interrupt response

• RISC-type instruction set (upward-compatible with SH Series)

 Instruction length: 16-bit basic instructions for improved efficiency,

and 32-bit instructions for improved performance and ease of use

 Load-store architecture

 Delayed branch instructions

 Instruction set based on C language

• Superscalar architecture allowing simultaneous execution of two

instructions, including FPU

• Instruction execution time: Max. 2 instructions/cycle

• Address space: 4 Gbytes

• On-chip multiplier

• Five-stage pipeline

• Harvard architecture

Section 1 Overview

Rev. 3.00 Jul 08, 2005 page 2 of 484

REJ09B0051-0300

Item Features

Floating-Point Unit

(FPU)

• On-chip floating-point coprocessor

• Supports single-precision (32 bits) and double-precision (64 bits)

• Supports IEEE754-compliant data types and exceptions

• Two rounding modes: Round to Nearest and Round to Zero

• Handling of denormalized numbers: Truncation to zero

• Floating-point registers

 Sixteen 32-bit floating-point registers

(single-precision x 16 words or double-precision x 8 words)

 Two 32-bit floating-point system registers

• Supports FMAC (multiply and accumulate) instruction

• Supports FDIV (divide) and FSQRT (square root) instructions

• Supports FLDI0/FLDI1 (load constant 0/1) instructions

• Instruction execution times

 Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single-precision), 8

cycles (double-precision)

 Pitch (FMAC/FADD/FSUB/FMUL): 1 cycle (single-precision), 6

cycles (double-precision)

Note: FMAC is supported for single-precision only.

• Five-stage pipeline

Section 2 Programming Model

Rev. 3.00 Jul 08, 2005 page 3 of 484

REJ09B0051-0300

Section 2 Programming Model

2.1 Data Formats

Data formats supported by the SH-2A/SH2A-FPU are shown in figure 2.1.

Byte (8 bits)

Word (16 bits)

Longword (32 bits)

Single-precision floating-point (32 bits)

Double-precision floating-point (64 bits)

015

031

031 30 22

fractionexps

063 62 51

exps fraction

Figure 2.1 Data Formats

2.2 Register Configuration

2.2.1 General Registers

Figure 2.2 shows the general registers. There are 16 general registers (Rn) numbered R0 to R15,

which are 32 bits in length. General registers are used for data processing and address calculation.

R0 is also used as an index register. Several instructions use R0 as a fixed source or destination

(SR) and program counter (PC) in exception processing is accomplished by referencing the stack

using R15.

Section 2 Programming Model

Rev. 3.00 Jul 08, 2005 page 4 of 484

REJ09B0051-0300

R10

R11

R12

R13

R14

R15, SP

31 0

R0 functions as an index register in the indirect indexed

addressing mode. In some instructions, R0 functions as

a fixed source register or destination register.

R15 functions as a hardware stack pointer (SP) during

exception processing.

1.Notes:

(hardware stack pointer)*

Figure 2.2 General Registers

Section 2 Programming Model

Rev. 3.00 Jul 08, 2005 page 5 of 484

REJ09B0051-0300

2.2.2 Control Registers

There are four control registers, each 32 bits in length: the status register (SR), global base register

(GBR), vector base register (VBR), and jump table base register (TBR).

The status register indicates the processing status of instructions.

The global base register is used as the base address in the GBR indirect addressing mode and to

transfer register data from on-chip peripheral modules.

The vector base register is used as the base address for the exception processing vector area,

including interrupts.

The table base register is used as the base address for the function table area.

(1) Status Register, SR

(32-bit, initial value = 0000 0000 0000 0000 00X0 00XX 1111 00XX) (X = undefined))

31 15 14 13 12 10 9 8 7 4 3 2 1 0

— BO CS — M Q IMASK — S T

Note: —: Reserved bits. Always read as 0. The write value should always be 0.

BO: Indicates that a register bank has overflowed.

CS: Indicates that, in CLIP instruction execution, the value has exceeded the saturation upper-

limit value or fallen below the saturation lower-limit value.

M, Q: Used by the DIV0S, DIV0U, and DIV1 instructions.

IMASK: Interrupt mask level

S: Specifies a saturation operation for a MAC instruction.

T: True/false condition or carry/borrow bit

(2) Global Base Register, GBR (32-bit, initial value = undefined)

GBR is referenced as the base address in a GBR-referencing MOV instruction.

(3) Vector Base Register, VBR (32-bit, initial value = H'0000 0000)

VBR is referenced as the branch destination base address in the event of an exception or interrupt.

Section 2 Programming Model

Rev. 3.00 Jul 08, 2005 page 6 of 484

REJ09B0051-0300

(4) Jump Table Base Register, TBR (32-bit, initial value = undefined)

TBR is referenced as the start address of a function table located in memory in a JSR/N

@@(disp8,TBR) table referencing subroutine call instruction.

2.2.3 System Registers

System registers consist of four 32-bit registers: high and low multiply and accumulate registers

(MACH and MACL), the procedure register (PR), and the program counter (PC). The multiply

and accumulate registers store the results of multiply and multiply and accumulate operations. The

procedure register stores the return address from the subroutine procedure. The program counter

indicates the address of the program executing and controls the flow of the processing.

MACL

MACH

31 0

Multiply and accumulate

Procedure register (PR):

Stores the return address for

a subroutine procedure.

Program counter (PC):

Indicates the fourth byte after

the current instruction.

(1) Multiply and Accumulate Register High, MACH (32-bit, initial value = undefined)

Multiply and Accumulate Register Low, MACL (32-bit, initial value = undefined)

MACH/MACL is used as the addition value in a MAC instruction, and to store the operation result

of a MAC or MUL instruction.

(2) Procedure Register, PR (32-bit, initial value = undefined)

PR stores the return address of a subroutine call using a BSR, BSRF, or JSR instruction, and is

referenced by a subroutine return instruction (RTS).

(3) Program Counter, PC (32-bit, initial value = value of PC in vector table)

The PC indicates the address of the instruction being executed.

Section 2 Programming Model

Rev. 3.00 Jul 08, 2005 page 7 of 484

REJ09B0051-0300

2.2.4 Floating-Point Registers

Figure 2.3 shows the floating-point registers. There are sixteen 32-bit floating-point registers,

FPR0 to FPR15. These sixteen registers are referenced as FR0 to FR15 and

DR0/2/4/6/8/10/12/14. The correspondence between FPRn and the reference name is determined

by the PR bit and SZ bit in FPSCR. See figure 2.3.

(1) Floating-Point Registers, FPRn (16 Registers)

FPR0, FPR l, FPR2, FPR3, FPR4, FPR5, FPR6, FPR7,

FPR8, FPR9, FPR10, FPR11, FPR12, FPR13, FPR14, FPR15

(2) Single-Precision Floating-Point Registers, FRi (16 Registers)

FR0 to FR15 are assigned to FPR0 to FPR15.

(3) Double-Precision Floating-Point Registers or Single-Precision Floating-Point Register

Pairs, DRi (8 Registers)

A DR register is composed of two FR registers.

DR0 = (FPR0, FPR1), DR2 = (FPR2, FPR3 ),

DR4 = (FPR4, FPR5), DR6 = (FPR6, FPR7),

DR8 = (FPR8, FPR9), DR10 = (FPR10, FPR11),

DR12 = (FPR12, FPR13), DR14 = (FPR14, FPR15)

Section 2 Programming Model

Rev. 3.00 Jul 08, 2005 page 8 of 484

REJ09B0051-0300

FPR0

FPR1

FPR2

FPR3

FPR4

FPR5

FPR6

FPR7

FPR8

FPR9

FPR10

FPR11

FPR12

FPR13

FPR14

FPR15

FR0

FR1

FR2

FR3

FR4

FR5

FR6

FR7

FR8

FR9

FR10

FR11

FR12

FR13

FR14

FR15

DR0

DR2

DR4

DR6

DR8

DR10

DR12

DR14

In case of transfer instruction:

In case of arithmetic/logical instruction:

FPSCR.SZ = 0

FPSCR.PR = 0

FPSCR.SZ = 1

FPSCR.PR = 1

Reference Name Register Name

Figure 2.3 Floating-Point Registers

Programming Note:

The values of FPR0 to FPR15 are undefined after a reset.

2.2.5 Floating-Point System Registers

(1) Floating-Point Communication Register, FPUL (32-bit, initial value = undefined)

Data transfers between an FPU register and CPU register are performed via FPUL.

(2) Floating-Point Status/Control Register, FPSCR (32-bit, initial value = H'0004 0001)

31 23 22 21 20 19 18 17 12 11 7 6 2 1 0

— QIS — SZ PR DN Cause Enable Flag RM

Section 2 Programming Model

Rev. 3.00 Jul 08, 2005 page 9 of 484

REJ09B0051-0300

QIS: sNaN is treated as qNaN or ±∞. Valid only when the V bit in the enable field of FPSCR is

set to 1.

• QIS = 0: Processed as qNaN or ±∞.

• QIS = 1: Exception generated (processed same as sNaN).

SZ: Transfer Size Mode

• SZ = 0: The data size of an FMOV instruction is 32 bits.

• SZ = 1: The data size of an FMOV instruction is a 32-bit pair (64 bits).

PR: Precision Mode

• PR = 0: Floating-point instructions are executed as single-precision operations.

• PR = 1: Floating-point instructions are executed as double-precision operations (the result of

an instruction for which double-precision is not supported is undefined).

DN: Denormalization Mode (always 1)

• DN = 1: A denormalized number is treated as zero.

Cause: FPU exception cause field

Enable: FPU exception enable field

Flag: FPU exception flag field

FPU Error

(E)

Invalid

Operation

(V)

Division

by Zero

(Z)

Overflow

(O)

Underflow

(U)

Inexact

Exception

(I)

Cause FPU exception

cause field

Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12

Enable FPU exception

enable field

None Bit 11 Bit 10 Bit 9 Bit 8 Bit 7

Flag FPU exception

flag field

None Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

When an FPU operation instruction is executed, the FPU exception cause field is initially set to 0.

When an FPU exception next occurs, the corresponding bit in the FPU exception cause field and

FPU exception flag field is set to 1.

The FPU exception flag field retains the status of an exception generated after that field was last

cleared.

Section 2 Programming Model

Rev. 3.00 Jul 08, 2005 page 10 of 484

REJ09B0051-0300

RM: Rounding Mode

RM = 00: Round to Nearest

RM = 01: Round to Zero

RM = 10: Reserved

RM = 11: Reserved

Bits 21, 23 to 31: Reserved

Note: The SH-2A does not generate an FPU error.

2.2.6 Register Banks

For the nineteen 32-bit registers comprising general registers R0 to R14, control register GBR, and

system registers MACH, MACL, and PR, high-speed register saving and restoration can be carried

out using a register bank. Saving to the bank is performed automatically after the CPU accepts an

interrupt that uses a register bank. Restoration from the bank is executed by issuing a RESBANK

instruction in an interrupt service routine.

For details, refer to section 7, Register Banks.

2.2.7 Register Initial Values

Table 2.1 Initial Values of Registers

Classification Register Initial Value

General registers R0–R14

R15(SP)

Undefined

SP value in the program address table

Control registers SR Bits I3–I0 are 1111 (H'F), BO, CS are 0,

reserved bits are 0, and other bits are

undefined

GBR, TBR Undefined

VBR H'00000000

System registers MACH, MACL, PR Undefined

PC Value of the program counter in the vector

address table

Floating-point registers FRR0–FRR15 Undefined

Floating-point system registers FPUL Undefined

FPSCR H'00040001

Section 2 Programming Model

Rev. 3.00 Jul 08, 2005 page 11 of 484

REJ09B0051-0300

2.3 Data Formats

2.3.1 Data Format in Registers

and the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a

longword when stored into a register.

31 0

Longword

2.3.2 Data Formats in Memory

Byte, word, and longword data formats are used. Memory can be accessed in 8-bit bytes, 16-bit

words, or 32-bit longwords. A memory operand of fewer than 32 bits is stored in a register in

sign-extended or zero-extended form.

A word operand should be accessed starting from a word boundary (2-byte even address: address

2n), and a longword operand from a longword boundary (4-byte even address: address 4n). If this

rule is not observed, an address error will occur. A byte operand can be accessed from any

address.

Only big-endian byte order can be selected for the data format.

Data formats in memory are shown in figure 2.4.

31 015

23 7

Byte Byte Byte Byte

WordWord

ddress 2n

ddress 4n Longword

Address m Address m + 2

Address m + 1 Address m + 3

Big-endian

Figure 2.4 Data Format in Memory

Section 2 Programming Model

Rev. 3.00 Jul 08, 2005 page 12 of 484

REJ09B0051-0300

2.3.3 Immediate Data Format

Byte immediate data is located in an instruction code. Immediate data accessed by the MOV,

ADD, and CMP/EQ instructions is sign-extended and is handled in registers as longword data.

Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and is

handled as longword data. Consequently, AND instructions with immediate data always clear the

upper 24 bits of the destination register.

20-bit immediate data is stored in the code of a MOVI20 or MOVI20S 32-bit transfer instruction.

The MOVI20 instruction stores immediate data in the destination register in sign-extended form.

The MOVI20S instruction shifts immediate data by 8 bits in the upper direction, and stores it in

the destination register in sign-extended form.

Word or longword immediate data is not located in the instruction code but rather is stored in a

memory table. The memory table is accessed by a immediate data transfer instruction (MOV)

using the PC relative addressing mode with displacement.

Specific examples are given in 4.1, (10) Immediate Data in section 4, Instruction Features.

Section 2 Programming Model

Rev. 3.00 Jul 08, 2005 page 13 of 484

REJ09B0051-0300

2.4 Processing States

The CPU has five processing states: the reset state, exception handling state, bus-released state,

program execution state, and power-down state. Figure 2.5 shows the state transitions.

Reset release

Power-on reset state Manual reset state

Program execution state

Bus-released state

Exception-handling state

Interrupt or DMA address error NMI or IRQ interrupt

End of exception

handling

Bus

request

Exception

handling

request

Bus

request

Bus

request

cleared

Bus request

cleared SLEEP

instruction with

STBY bit cleared

SLEEP

instruction with

STBY bit set

Power-on reset

from any state

Manual reset

from any state

Reset state

Power-down state

Standby input from any state

Bus request

cleared

Software standby modeSleep mode

Hardware standby mode

Figure 2.5 Processing State Transitions

Section 2 Programming Model

Rev. 3.00 Jul 08, 2005 page 14 of 484

REJ09B0051-0300

(1) Reset State

In this state, the CPU is reset. There are two kinds of reset, power-on and manual. See the

Hardware Manual for details.

(2) Exception Handling State

The exception handling state is a transient state that occurs when the CPU alters the normal

programming flow due to a reset, interrupt, or other exception handling source.

In the case of a reset, the CPU fetches the execution start address as the initial value of the

program counter (PC) from the exception vector table, and the initial value of the stack pointer

(SP), stores these values, branches to the start address, and begins program execution at that

address.

In the case of an interrupt, etc., the CPU references the SP and saves the PC and status register

(SR) in the stack area. It fetches the start address of the exception service routine from the

exception vector table, branches to that address, and begins program execution.

Subsequently, the processing state is the program execution state.

(3) Program Execution State

In the program execution state the CPU executes program instructions in the normal sequence.

(4) Power-Down State

In the power-down state the CPU stops operating to conserve power. Sleep mode or software

standby mode is entered by executing a SLEEP instruction. If hardware standby input is received,

the CPU enters the hardware standby mode.

(5) Bus-Released State

In the bus-released state, the CPU releases the bus to a device that has requested it.

Note: For information on the processing states, please refer to the hardware manual for the

product in question.

Section 3 Exception Handling

Rev. 3.00 Jul 08, 2005 page 15 of 484

REJ09B0051-0300

Section 3 Exception Handling

3.1 Overview

3.1.1 Exception Handling Types and Priority

As table 3.1 indicates, exception handling may be caused by a reset, address error, RAM error,

3.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of

priority.

Section 3 Exception Handling

Rev. 3.00 Jul 08, 2005 page 16 of 484

REJ09B0051-0300

Table 3.1 Exception Types and Priority

Exception Handling Priority

Power-on reset HighReset

Manual reset

CPU address errorAddress errors

DMAC address error

RAM errors RAM error

FPU exception

Integer division exception (division by zero)

Instructions

Integer division exception (overflow)

Bank underflowRegister bank

errors Bank overflow

NMI

User break

H-UDI

External interrupt (IRQ)

Interrupts

On-chip peripheral modules

Trap instruction (TRAPA instruction)

General illegal instruction (undefined code)

Instructions

Slot illegal instruction (undefined code (FPU instruction or FPU-

related CPU instruction in module standby status including FPU or in

product with no FPU, or register bank-related instruction*2 in product

with no register bank) located immediately after delayed branch

instruction*1, instruction that modifies PC*3, 32-bit instruction*4,

RESBANK instruction, DIVS instruction, or DIVU instruction) Low

Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,

BRAF

2. Register bank-related instructions: RESBANK, LDBANK, STBANK

3. Instructions that modify PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S,

BT/S, BSRF, BRAF, JSR/N, RTV/N

4. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B,

BORNOT.B, BSET.B, BST.B, BXOR.B, FMOV.S @disp12, FMOV.D @disp12,

MOV.B @disp12, MOV.W @disp12, MOV.L @disp12, MOVI20, MOVI20S, MOVU.B,

MOVU.W

Section 3 Exception Handling

Rev. 3.00 Jul 08, 2005 page 17 of 484

REJ09B0051-0300

3.1.2 Exception Handling Operation

Table 3.2 shows the timing of detection and the start of exception handling for each exception

source.

Table 3.2 Timing of Exception Source Detection and Start of Exception Handling

Exception Handling Exception Source Detection and Start of Exception Handling

Power-on reset Started by detection of power-on reset condition

Reset

Manual reset Started by detection of manual reset condition

Address error

RAM error

Interrupt

Detected when instruction is decoded; exception handling is

started after completion of currently executing instruction

bank error

Bank underflow Started upon attempted execution of RESBANK instruction when

save has not been performed to register bank

Bank overflow Started when save has already been performed to all register

bank areas when acceptance of register overflow exception has

been set by interrupt controller, and interrupt that uses register

bank is generated and accepted by CPU

Instruction Trap instruction Started by execution of TRAPA instruction

General illegal

instruction

Started when undefined code (FPU instruction or FPU-related

CPU instruction in module standby status including FPU or in

product with no FPU, or register bank-related instruction in

product with no register bank) not immediately following delayed

branch instruction (delay slot) is decoded

Slot illegal

instruction

Started when undefined code (FPU instruction or FPU-related

CPU instruction in module standby status including FPU or in

product with no FPU, or register bank-related instruction in

product with no register bank) not immediately following delayed

branch instruction (delay slot), instruction that modifies PC, 32-bit

instruction, RESBANK instruction, DIVS instruction, or DIVU

instruction is decoded

Integer division

instruction

Started upon detection of division-by-zero exception or overflow

exception caused by dividing negative maximum value

(H’80000000) by –1

Floating-point

operation

instruction

Started by floating-point operation instruction invalid operation

exception (stipulated by IEEE754), or overflow, underflow, or

imprecision interrupt. Also started when qNaN or ±∞ is input to a

floating-point operation instruction source

Section 3 Exception Handling

Rev. 3.00 Jul 08, 2005 page 18 of 484

REJ09B0051-0300

When exception handling is initiated, the CPU operates as follows.

(1) Reset Exception Handling

The initial values of the program counter (PC) and stack pointer (SP) are fetched from the

exception vector table (addresses H'00000000 and H'00000004 in the case of a power-on reset,

and addresses H'00000008 and H'0000000C in the case of a manual reset). See section 3.1.3,

Exception Vector Table, for details of the exception vector table. Next, the vector base register is

cleared to H'00000000, the interrupt mask bits (I3 to I0) in the status register (SR) are set to (H'F)

(1111), and the BO and CS bits are initialized to 0. The BN bit in IBNR of INTC is also

initialized to 0. In addition, in products with an FPU, FPSCR is initialized to H'00040001.

Program execution starts from the PC address fetched from the exception vector table.

(2) Address Error, RAM Error, Register Bank Error, Interrupt, or Instruction Exception

Handling

SR and PC are saved on the stack indicated by R15. In interrupt exception handling other than

NMI and UBC, when register bank use has been set, general registers R0 to R14, control register

GBR, system registers MACH, MACL, and PR, and the vector table address offset of the interrupt

exception handling to be executed, are saved to the register bank. In the case of exception

handling due to an address error, RAM error, register bank error, NMI interrupt or UBC interrupt,

saving to a register bank is not performed. Also, when saving is performed to all register banks,

automatic saving to the stack is performed instead of register bank saving. In this case, an

interrupt controller setting must have been made for register bank overflow exceptions not to be

accepted. If a setting has been made for register bank overflow exceptions to be accepted, a

the interrupt priority level is written to the interrupt mask bits (I3 to I0) in SR. In address error,

RAM error, and instruction exception handling, bits I3 to I0 are not affected. Next, the start

address is fetched from the exception vector table and program execution is started from that

address.

3.1.3 Exception Vector Table

Before exception handling is executed, the exception vector table must have been set up in

memory. The exception vector table holds the start addresses of the exception service routines

(the reset exception handling table holds the initial values of PC and SP).

A different vector number and vector table address offset are assigned to each exception source.

The vector table address is calculated from the corresponding vector number and vector table

address offset. In exception handling, the start address of the exception service routine is fetched

from the exception vector table entry indicated by this vector table address.

Section 3 Exception Handling

Rev. 3.00 Jul 08, 2005 page 19 of 484

REJ09B0051-0300

The vector numbers and vector table address offsets are shown in table 3.3, and the method of

calculating the vector table address in table 3.4.

Table 3.3 Exception Vector Table

Exception Source Vector Number Vector Table Address Offset

Power-on reset PC 0 H'00000000 to H'00000003

SP 1 H'00000004 to H'00000007

Manual reset PC 2 H'00000008 to H'0000000B

SP 3 H'0000000C to H'0000000F

General illegal instruction 4 H'00000010 to H'00000013

RAM error 5 H'00000014 to H'00000017

Slot illegal instruction 6 H'00000018 to H'0000001B

(Reserved for system) 7 H'0000001C to H'0000001F

8 H'00000020 to H'00000023

CPU address error 9 H'00000024 to H'00000027

DMAC address error 10 H'00000028 to H'0000002B

Interrupt NMI 11 H'0000002C to H'0000002F

User break 12 H'00000030 to H'00000033

FPU exception 13 H'00000034 to H'00000037

H-UDI 14 H'00000038to H'0000003B

Bank overflow 15 H'0000003C to H'0000003F

Bank underflow 16 H'00000040 to H'00000043

Integer division exception

(division by zero)

17 H'00000044 to H'00000047

Integer division exception (overflow) 18 H'00000048 to H'0000004B

(Reserved for system) 19

•

H'0000004C to H'0000004F

•

H'0000007C to H'0000007F

Trap instruction (user vector) 32

•

H'00000080 to H'00000083

•

H'000000FC to H'000000FF

External interrupt (IRQ), on-chip

peripheral module*

•

511

H'00000100 to H'00000103

•

H'000007FC to H'000007FF

Note: *For the vector numbers and address offsets of external interrupts and on-chip peripheral

module interrupts, see “Internal Module Interrupt Exception Handling Vectors and Priority

Order” in the Interrupt Controller section of the hardware manual.

Section 3 Exception Handling

Rev. 3.00 Jul 08, 2005 page 20 of 484

REJ09B0051-0300

Table 3.4 Exception Vector Table Address Calculation

Exception Source Vector Table Address Calculation

Reset Vector table address = (vector table address offset)

= (vector number) × 4

Address error, RAM error,

instruction

Vector table address = VBR + (vector table address offset)

= VBR + (vector number) × 4

Note: VBR: Vector base register

Vector table address offset: See table 3.3.

Vector number: See table 3.3.

3.2 Resets

3.2.1 Types of Reset

A reset is the highest-priority exception handling source. There are two types of reset: a power-on

reset and a manual reset. The CPU state is initialized by both a power-on reset and a manual reset.

The FPU state is initialized by a power-on reset, but not by a manual reset. Refer to the hardware

manual of the relevant product for information on the states of on-chip peripheral modules, the

PFC, and I/O ports.

3.2.2 Power-On Reset

When a power-on reset condition is detected, the chip enters the power-on reset state. See

“Power-On Reset” in the Exception Handling section of the hardware manual for the relevant

product for details of power-on reset conditions.

When the power-on reset state is released, power-on reset exception handling is started. CPU

operations are as follows.

1. The initial value of the program counter (PC) (i.e. the execution start address) is fetched from

the exception vector table.

2. The initial value of the stack pointer (SP) is fetched from the exception vector table.

3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask bits (I3 to I0) in

the status register (SR) are set to (H'F) (1111), and the BO and CS bits are initialized to 0. The

BN bit in IBNR of INTC is also initialized to 0. In addition, in products with an FPU, FPSCR

is initialized to H'00040001.