1/35October 2004
M45PE10
1 Mbit, Low Voltage, Page-Erasable Serial Flash Memory
With Byte-Alterability and a 25 MHz SPI Bus Interface
FEATURES SUMMARY
■1Mbit of Page-Erasable Flash Memory
■Page Write (up to 256 Bytes) in 11ms (typical)
■Page Program ( up to 256 Bytes) i n 1.2ms
(typical)
■Page Erase (256 Bytes) in 10ms (typical)
■Sector Erase (512 Kb it)
■2.7 to 3.6V Single Supply Vo ltage
■SPI Bus Compatible Serial Interface
■25MH z Clock Rate (maximum)
■D eep Power-down Mod e 1µA (typical)
■Ele ctronic Signature
– JEDEC Standard Two-Byte Signature
(4011h)
■More than 100, 000 Write Cycles
■More than 20 Yea r Data Retention
Figure 1. Packages
SO8 (MN)
150 mil width
8
1
VDFPN8 (MP)
(MLP8)
M45PE10
2/35
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. SO and VDFPN Connec tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
R eset (Reset). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SPI MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Sharing the Overhead of Modifying Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
An Easy Way to Modify Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
A Fast Way to Modify Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Po lling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
R eset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Active Power, Standby Power and Deep Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
Table 3. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 6. Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Write Enable (WREN) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2
Figure 8. Write Disable (WRDI) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3/35
M45PE10
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Read Identification (RD ID) Data-Out Seque nce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Read Identification (RD ID) Instruction Sequence and Data-O ut Sequen ce . . . . . . . . . . 13
Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
Figure 10.Read S tatus Register (RDSR) Instruction Sequence and Data-O ut Sequen ce . . . . . . . 14
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11.Read Dat a Bytes (READ) Instruction Sequen ce and Data-Out Sequence . . . . . . . . . . . 15
Read Data Bytes at Higher Speed (FAST_READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12.Read Data Bytes at Higher Speed (FAST_READ ) Instruction Sequenc e and Data-Out Se-
quence 16
Page Write (PW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13.P age Write (PW) Instruction Sequenc e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8
Figure 14.P age Pro gram (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pag e Erase (PE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15.P age Era se (PE) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Sec tor Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0
Figure 16.S ector Eras e (SE) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Deep Power-down (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 17.Deep P ower-down (DP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Release from Deep Power-down (RDP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 18.Release from Deep Power-down (RDP) I nstruc tion Sequence. . . . . . . . . . . . . . . . . . . . 22
POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 19.Power-up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3
Table 6. Power-Up Timing and VWI Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6
Table 8. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. A C Measurem ent Condition s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 20.AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8
Figure 21.S erial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9
Figure 22.Write Protect Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 23.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 24.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
M45PE10
4/35
PACKAGE M ECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1
Figure 25.S O8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 31
Table 13. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
31
Figure 26.M LP 8, 8-lead Very thin Dual Flat Package No lead, 6x 5mm, Package Outli ne . . . . . . . 32
Table 14. MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5mm , Package Mechanical Data32
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 16. Document Revisi on Histo ry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5/35
M45PE10
S UM MARY DESCR IPTION
The M45PE10 is a 1Mbit (128K x 8 bit) Serial
Paged Flash Memory accessed by a high speed
SPI - co mp atible bu s .
The memory can be written or programmed 1 to
256 bytes at a time, using t he Page Writ e or Page
Program instruction. The Page Write instruction
consists of an integrated Page Erase cycle fol-
lowe d by a Page Program cycle.
The memory is organi zed as 2 sec tors, each c on-
taining 256 p ages. Each page is 256 bytes wide.
Thus, the whole memory can be viewed as con-
sisting of 512 pages, or 131,072 bytes.
The memory c an be erased a page at a time, using
the Page Erase instruction, or a sector at a time,
using the Sector Erase instruction.
Figure 2. Logic Diagram
Figu re 3. S O and VD FP N C onnec tio ns
Note : 1. There is an exposed di e paddle on the u nders ide of the
MLP8 package. This is pulled, internally, to VSS, and
must not be allowed to be connected to any other voltage
or si gnal line on the PCB.
2. See PACKAGE MECHANICAL section for package di-
mens i ons, and how to identify pin-1.
Table 1. Signal Names
Reset
AI07403
S
VCC
M45PE10
VSS
W
Q
C
D
1
AI07404
2
3
4
8
7
6
5WS VCC
VSS
C
DQ
Reset
M45PE10
C Serial Clock
D Serial Data Input
Q Serial Data Outp ut
SChip Select
W Write Protect
Reset Reset
VCC Supply Voltage
VSS Ground
M45PE10
6/35
SIGNAL DESCRIPTION
Serial Data O utp ut (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data In put (D). This input signal is used to
transfer data seriall y into t he devi ce. It receives in-
structions, addresses, and the data to be pro-
grammed. Values are latched on the rising edge of
Serial Clock (C).
Serial Clock (C). This input signal provides the
timing of the s erial interface. Instructions, addres s-
es, or data present at Serial Data Input (D) are
latched on the ris ing edge of Serial Clock (C) . Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Selec t (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) i s at high impedance. Unless an internal Read,
Program, Erase or Write cycle is in progress, the
device will be in the Standby Power m ode (this is
not the Deep Power-down mode). Driving Chip
Se l e c t (S) Low sel ects the device, placing it in the
Active Power mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Reset (R eset). T he Reset (Reset) input provides
a hardware reset for the memory. In this mode, the
outputs are high impedan ce.
When Reset (Reset) i s driven High, the memory is
in the normal operating mode. When Reset (Re-
set) is driven Low, the memory will enter t he Reset
mode, provided that no internal operation is cur-
rently in progress . Driving Reset (Reset) Low while
an internal operation is in progress has no effect
on that internal operation (a write cycle, program
cycle, or eras e cy cle).
Write Protect (W). This input signal puts th e de-
vice in the Hardware Protected mode, when Write
Protect (W ) is c onnected to VSS, causing the first
256 pages of memory to become read-only by pro-
tecting them fro m write, program and erase oper-
ations. When Write Protect (W) is connected to
VCC, the first 256 pages of memory behave like
the other pages of memory.
7/35
M45PE10
SPI MODES
These dev ices can be drive n by a microcont roller
with its SPI peripheral running in either of the two
following modes:
– CPOL=0, CP HA=0
– CPOL=1, CP HA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference between t he two modes, as shown
in Figure 5., is the clock polarity when the bus
master is in Stand-by mode and not transferring
data:
– C remains at 0 for (CPOL=0, CPHA =0)
– C remains at 1 for (CPOL=1, CPHA =1)
Figure 4. Bus Master and Memo ry Devices on the SPI Bus
Note: The Write Protect (W) signal shou l d be dri ven, High or Low as appropria te.
Figure 5 . S PI Modes Suppor te d
AI04043B
Bus Master
(ST6, ST7, ST9,
ST10, Others) SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3 CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
WRP WRP WRP
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
M45PE10
8/35
OPERAT ING FEA TURES
Sharing the Overhead of Modifying Data
To write or program one (or more) data bytes, two
instructions are required: Write Enable (WREN),
which is one byte, and a Page Write (PW) or Page
Program (PP) sequence, which consists of four
bytes plus data. T his is f ollowed by the internal cy-
cle (of duration tPW or tPP).
To share this overhead, the Page Write (PW) or
Page Program (PP) instruction allows up to 256
bytes to be p rogrammed (changing bits from 1 t o
0) or wri tten (changi ng bits to 0 or 1) at a time, pro-
vided that they lie in consecutive addresses on the
same page of memory.
An Easy Way to Modify Data
The Page Write (PW) instruction provides a con-
venient w ay of modifying data (up to 256 contigu-
ous bytes at a t ime), a nd sim ply requ ires the s tart
address, and the new data in the instruction se-
quence.
The Page Write (PW) instruction is entered by
driving Chip Select (S) Low , and then transmit ting
the instruction byte, three address bytes (A23-A0)
and at least one data byte, and then driving Ch ip
Select (S) High. While Chip Select (S) is being
held Low, the data bytes are written to the data
buffer, starting at the address given in the third ad-
dress byte (A7-A0). When Chip Select (S) is driven
High, the Write cycle starts. The remaining, un-
changed, bytes of the data buffer are automatically
loaded with the values of the correspondin g bytes
of the addressed memory page. The addressed
memory page then automatically put into an Erase
cycle. Finally, the addr essed mem ory page is pro-
grammed wi th the contents of the data buf fer.
All of this buffer management is handled internally,
and is transparent to the user. The user is given
the facility of bei ng able to alter the contents of the
memory on a byte-by-byte basis.
A Fast Way to M odify Data
The Page Program (PP) instruction provides a f as t
way of modifying data (up to 256 contiguous bytes
at a time), provided that it only involves resetting
bits to 0 that had previously been set t o 1.
This might be:
– when the designer is programming the devi ce
fo r the first ti me
– w hen the designer know s that the page has
already been erased by an earlier Page Erase
(PE) or Sector Erase (SE) instruct ion. This is
use ful, for example, when storing a fast
stream of data, having first performed the
erase cycle when ti me was available
– w hen the designer know s that the only
changes involve resetting bits to 0 that are still
set to 1. When this method is possible, it has
the addi tional advantage of minimisin g the
number of unnecessary erase operations, and
the extra stress incurred by each page.
Polling Duri ng a Write, Program or Erase Cycle
A further improvement in the write, program or
erase time can be achieved by not waiting for the
worst case delay (tPW, tPP, tPE, or tSE). The Write
In Progress (WIP) bit is provided in the Status
Register so that the applic ation progr am can mon-
itor its value, polling it to esta blish when the previ-
ous cycl e is complet e .
Reset
An internal Power On Reset circuit helps protect
against inadvertent data writes. Addition protec-
tion is provided by driving Re set (Reset) Low dur-
ing the Power-on process, and only driving it High
when VCC has reached the correct voltage level,
VCC(min).
Active Power, Standby Power and Deep
Power- Down Modes
When Chip Select (S) is Low, the device is select -
ed, and in the A ctive Power mode.
When Chip Sel ec t ( S) is High, the device is dese-
lected, but could remain i n t he Acti ve P ower mode
until all internal cycles have completed (Program,
Erase, Write). The device then goes in to the
Standby Power mode. The device consumption
drops to ICC1.
The Deep Power-down mode is entered when the
specific instruction (the Deep Power -down (DP) in-
struction) is executed. The device consumption
drops further to ICC2. The device remains in this
mode until another specific instruction (the Re-
lease from Deep Power-down and Read Elec tron-
ic Signature (RES) instruct ion) is executed.
All other instructions are igno red while the device
is in the Deep Power-down mode. This can be
used as an ext ra softw are protection mecha nism,
when the device is not in active use, to protect the
device from inadvertent Write, Program or Erase
instructions.
9/35
M45PE10
Status Reg ister
The Status Register contains two status bits that
can be read by the Read Status Register (RDSR)
instruction.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Wr ite, Program
or Erase cycle.
WE L bi t. The W rite Enable Latch (W EL ) bit indi-
cates the status of the int ernal Write Enable Latch.
Table 2. Status Regi ster Format
Note: WEL and WIP are volat ile read-only bits (WEL is set and re-
set by s pecific instructions; WIP is automat ic ally s et and re -
se t by the int ernal l og i c of the device ).
P rotec tion Mo des
The environments where non-vol atile memory de-
vices are used can be very noisy. No SPI device
can operate correct ly in the presence of excessive
noise. To help combat this, the M45PE10 features
the following data protection m echanisms:
■Powe r On Reset and an internal timer (tPUW)
can provide protecti on against inadvertant
changes while the power supply is outside the
operat ing specificatio n.
■Program , Erase and Write instructions are
chec ked that they consist of a number of clock
pulses that is a multiple of eight, before they
are accepted for execut ion.
■All instructions that modify data must be
prece ded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WE L) bit. This bit is returned to its reset state
by the following events:
– Power-up
– Reset (RESET) driven Low
– Write Disable (WRDI) instruction
completion
– Page Write (PW) ins truction complet ion
– Page Progr am (PP) instruction completion
– Page Erase (PE) instruction com pletion
– Sector Erase (SE) instruction comple tion
■The Hardware P rotected mo de is entered
when Write Protect (W) is driven Low, causing
the first 256 pages of memory to become
read-only. When Write Protect (W) is driven
Hi gh, the fir st 256 pages of memory behave
like the other pages of memo ry
■The Reset (Reset) signal can be driven Low to
prot ect the contents of the memory during any
critical time, not just during Power-up and
Power-down.
■In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software protection from inad vertant
W rite, Program and Erase instructions while
the device is not in active use.
b7 b0
0 0 0 0 0 0 WEL WIP
M45PE10
10/35
ME M ORY ORGANIZA TION
The memory is organized as:
■512 pages (256 bytes each).
■131, 072 bytes (8 bits each)
■2 sectors (512 Kbits, 65536 bytes each)
Each page can be individuall y:
– programmed (bits are programmed from 1 to
0)
– erased (bits are erased from 0 to 1)
– w ritten (bits are changed to either 0 or 1 )
The device is Page or Sector Erasable (bits are
erased f rom 0 to 1).
Table 3. Memory Organization
Figu re 6. Blo ck Diagram
Sector Address Range
1 10000h 1FFFFh
0 00000h 0FFFFh
AI07405
S
WControl Logic High Voltage
Generator
I/O Shift Register
Address Register
and Counter 256 Byte
Data Buffer
256 Bytes (Page Size)
X Decoder
Y Decoder
C
D
Q
Status
Register
00000h
1FFFFh
000FFh
Reset
10000h
First 256 Pages can
be made read-only
11/35
M45PE10
INSTRUCTIONS
All instructions, addresses and data are shifted in
and out of the device, most significant bit f irst.
Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) after Chip Select (S) is
driven Low. Then, the one-byte instruction code
must be shifted in t o the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
The instruct i on set is listed in Tab le 4..
Every instruction sequence s tarts with a one-byte
instruction code. Depending on the instruction,
this might be f ollowed by address bytes, or by data
bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read
Data Bytes at Higher Speed (Fast_Read) or Read
Status Register (RDSR) instruction, the shifted-in
instruction sequenc e is follo wed by a data-out se-
quence. Chip Select (S) can be driven High after
any bit of the data-out sequence is being shifted
out.
In the cas e of a Page Write (PW), Page P rogram
(PP), Page Erase (PE), Sector Erase (SE), Write
Enable (WREN), Write Disable (WRDI), Deep
Power-down (DP) or Release from Deep Power-
down (RDP) instruction, Chip Select (S) must be
driven H igh e xactly a t a by te boundary, otherwise
the instruction is rejected, and is not executed.
That is, Chip Select (S) must driven High when the
number of cl ock pulses after Chip Select (S) being
driven Low is an exact multiple of eight.
All attempts to access t he memory arra y during a
Write cycle, Program cycle or Erase cycle are ig-
nored , and the internal Wri te cycle, Pr ogram cycl e
or Erase cycle continues unaffected.
Table 4. Instruction Set
Instruction Description One-byte Instruction Code Address
Bytes Dummy
Bytes Data
Bytes
WREN Write Enable 0000 0110 06h 0 0 0
WRDI Write Disable 0000 0100 04h 0 0 0
RDID Read Identification 1001 1111 9Fh 0 0 1 to 3
RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞
READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞
FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to ∞
PW Page Write 0000 1010 0Ah 3 0 1 to 256
PP Page Program 0000 0010 02h 3 0 1 to 256
PE Page Erase 1101 1011 DBh 3 0 0
SE Sector Erase 1101 1000 D8h 3 0 0
DP Deep Power-down 1011 1001 B9h 0 0 0
RDP Release from Deep Power-down 1010 1011 ABh 0 0 0
M45PE10
12/35
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 7.)
sets the Write Enable Latc h (WEL) bit.
The Write Enabl e Latch (WEL) bi t must be set pri-
or to every Page Write (PW), Page Program (PP),
Page Erase (PE), and Sector Erase (SE) instruc-
tion.
The Write Enable (WREN) instruction is entered
by driving Chip Select (S) Low, sending the in-
struction code, and then driving Chip Select (S)
High.
Figure 7. Write Enable (WREN) Instruction Sequen ce
Write Disabl e (WRDI)
The Write Disable (WRDI) instruction (Figure 8.)
resets the Write Enable Latch (WEL ) bit.
The Write Disable (WRDI) inst ruction is entered by
driving Chip Select (S) Low, sending the instruc-
tion code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under
the following conditions:
–Power-up
– Write Disable (WRDI) instruction completion
– Page Write (PW) instruction compl etion
– Page Program ( PP) instruction compl etion
– Pag e Erase (PE) instruction completion
– Sector Erase (SE) instruction completion
Figure 8. Write Disable (WRDI) Instruction Sequence
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
13/35
M45PE10
Read Identification (RDID)
The Read Identification (RDID) instruction allows
the 8-bit manufacturer identification to be read, fol-
lowed by two bytes of device identification. The
manufacturer identification is assigned by JEDEC,
and has the value 20h for STMicroelectronics. The
device identification is assigned by the device
manufacturer, and indicates the memory type in
the first byte (40h), and the memory capacity of the
device in the second byte (11h).
Any Read Identification (RDID) instruction while
an Erase or Program cycle is in progress, is not
decoded, and has no ef fect on the cycle that is in
progress.
The device is first selected by driving Chip Sele ct
(S) Low. Then, the 8-bit i nst ruction code for the i n-
struction is shi fted in. This is followed by the 24-bit
device identification, stored in the memory, be ing
shifted out on Serial Data Output (Q), each bit be-
ing shifted out during the falling edge of Serial
Clock (C).
The instruct i on sequence is shown in Figure 9..
The Read Identification (RDID) instruction is t ermi-
nated b y driving Chip Select ( S) High at any time
during data output.
When Chip Select (S) i s dr i ven Hig h, the devi ce i s
put in the Standby Power mode. Once in the
Standby Power mode, the device waits to be se-
lected, so that it can receive, decode and execute
instructions.
Table 5. Read Identification (RDID) Data-Out Sequence
Figure 9. Read Identification (RDID) Instruction Sequence and Data-Ou t Seq uen ce
Manufacturer Identification Device Identification
Memory Type Memory Capacity
20h 40h 11h
C
D
S
21 3456789101112131415
Instruction
0
AI06809
Q
Manufacturer Identification
High Impedance
MSB
15 1413 3210
Device Identification
MSB
16 16 18 28 29 30 31
M45PE10
14/35
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Program, Erase or Write cycle is in progress.
When one of these cycles is in progress, it is rec-
ommended to check the Write In Progress (WIP)
bit before sending a new instruction to the device.
It is also possible to read the Status Register con-
tinuously, as shown in Figure 10..
The status bits of the Status Register are as fol-
lows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Wr ite, Program
or Erase cycle. When set to 1, such a cycle is in
progress, when reset to 0 no such cycle is in
progress.
WE L bi t. The W rite Enable Latch (W EL ) bit indi-
cates the status of the int ernal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when s et to 0 the inte rnal W r ite Enabl e Latch
is reset and no Write, Program or Erase instruction
is accepted.
Figure 10. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q76543210
Status Register Out
High Impedance
MSB
76543210
Status Register Out
MSB
7
15/35
M45PE10
Read Data Bytes (READ)
The device is first selected by driving Chip Sele ct
(S) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte
address (A23-A0), each bit being latched- in during
the rising edge of Serial Cl ock (C). Then the mem-
ory contents , at that address, is shifted out on Se-
rial Data Output (Q), eac h b it bein g s hifted out, at
a maximum frequency fR, during the falling edge of
Serial Clock (C).
The instruct i on sequence is shown in Figure 11..
The first byte addressed can be at any location.
The address is automatically incremented to the
next higher address after each byte of data is shift-
ed out. The whole memory can, ther efore, be read
with a singl e Read Data Byt es (READ) i nstruction.
When the highes t address is reached, the address
counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is termi-
nated by driving Chi p Select (S) High. Chip Select
(S) can be driven High at any time during data out-
put. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in
progress, is rej ected without having any ef fects on
th e cycle tha t is in pro gr es s.
Figure 11. Read Data Bytes (READ) Instruction Sequ ence and Data-Out Sequence
Note: Address bi ts A23 to A17 are Don’ t Care.
C
D
AI03748D
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
76543 1 7
0
High Impedance Data Out 1
Instruction 24-Bit Address
0
MSB
MSB
2
39
Data Out 2
M45PE10
16/35
Read Data Bytes at Hig her Speed
(FAST_READ)
The device is first selected by driving Chip Sele ct
(S) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction
is followed by a 3-byte address (A23-A0) and a
dummy byte, each bit being latched-in during the
rising edge of S erial Clock (C). Then the memory
contents, at that address, is shifted out on Serial
Data Output (Q), each bit being shifted out, at a
maximum frequency fC, durin g the falling edg e of
Serial Clock (C).
The instruct i on sequence is shown in Figure 12..
The first byte addressed can be at any location.
The address is automatically incremented to the
next higher address after each byte of data is shift-
ed out. The whole memory can, ther efore, be read
with a single Read Data Bytes at Higher Speed
(FAST_READ) instruction. When the highest ad-
dress is reached, the address counter rolls over to
000000h, allowing the read sequence to be contin-
ued indefinitely.
The Read Data Bytes at Higher Speed
(FAST_READ) instruction is terminated by driving
Chip Select ( S) Hi gh. Chip Select (S) can be driv-
en High at any time during data output. Any Read
Data Bytes at Higher Speed (FAST_READ) in-
struction, while an Erase, Program or Write cycle
is in progress, is rejected without having any ef-
fects on the cycle that is in progress.
Figure 12. Read Data Bytes at Hi gher Speed (F AST_READ) Instruction Sequence and Data-Out
Sequence
Note: Address bi ts A23 to A17 are Don’ t Care.
C
D
AI04006
S
Q
23
21 345678910 28293031
2221 3210
High Impedance
Instruction 24 BIT ADDRESS
0
C
D
S
Q
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy Byte
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
17/35
M45PE10
Page Write (PW)
The Page Write (PW) instruction allows bytes to
be written in the m emory. Before i t can be accept-
ed, a Write Enable (WREN) instruction must previ-
ously have been exec uted. After the Write Enable
(WREN) instruction has been decoded, t he devi ce
sets the Write Enable Latc h (WEL).
The Page Write (PW) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, three address bytes and at least
one data byte on Serial Data Input (D). The rest of
the page remains unchanged if no power failure
occurs during this write cycle.
The Page Write (P W) instruc tion performs a p age
erase cycle even if only one byte is updated.
If the 8 least significant address bits (A7-A0) are
not all zero, all transmitted data ex ceeding the ad-
dressed page boundary wrap round, and are writ-
ten from the start address of the same page (the
one whose 8 l east significant address bits ( A7-A0)
are all zero). Chip Select (S) mus t be d riven Low
for the entire duration of the sequence.
The instruct i on sequence is shown in Figure 13..
If more than 256 bytes are sent to the device, pre-
viously latched data are discarded and the last 256
data bytes are guaranteed to be written correctly
within the same page. If less than 256 Data bytes
are sent to device, they are corr ectly written at the
requested addresses without having any effects
on the other bytes of the same page.
Chip Select (S) must be driven High after the
eighth bi t of the last data byte has been l atched in,
otherwise the Page Write (PW) instruction is not
executed.
As soon as Chip Select (S ) is dr iv en Hi gh , t he s elf -
timed Page Write cycle (whose duration is t PW) is
initiated. While the Page Write cycle is in progress ,
the Status Register may be read to check the val-
ue of the Wr ite In Progress (WIP) bit. The Write In
Progress (WIP) bit is 1 during the self-timed Page
Write cycle, and is 0 when it is completed. At some
unspecified time before the cycle is com plete, the
Write Enable Latch (WEL) bit is reset.
A Page Write (PW) instruction applied to a page
that is Har dware Protect ed is not executed.
An y Pag e Writ e (P W) in str uctio n, wh ile an Era se,
Prog ram or Write cycle is in progress, is rejected
without having any effects on the cycle that is in
progress.
Figu re 13 . P age W rite (PW ) Instruction S e qu e nce
Note: 1. Address bits A23 to A17 are D on’t Ca re
2. 1 ≤ n ≤ 25 6
C
D
AI04045
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
D
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-Bit Address
0
765432 0
1
Data Byte 1
39
51
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3 Data Byte n
765432 0
1
MSB MSB
MSB MSB MSB
M45PE10
18/35
Page Prog ram (PP)
The Page Pr ogram (PP) instruction allows bytes to
be programmed in the memory (changing bits from
1 to 0, only). Before it can be accepted, a Write En-
able (WREN) instruction must previously have
been executed. After the Write Enable (WREN) in-
struction has been decoded, the device sets the
Write Enable Latch (WEL).
The Page Pro gram (PP) instru ction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, three address bytes and at least
one data byte on Serial Data Input (D). If the 8
least significant address bits (A7-A0) are not all
zero, all transmitted data exceeding the ad-
dressed page bound ary wrap round , and are pro-
grammed f rom the start address of the same page
(the one whose 8 least significant address bits
(A7-A0) are all zero). Chip Select (S) mus t be driv-
en Low for the entire duration of the sequence.
The instruct i on sequence is shown in Figure 14..
If more than 256 bytes are sent to the device, pre-
viously latched data are discarded and the last 256
data bytes are guaranteed to be programmed cor-
rectly within the sam e page. If less than 2 56 Dat a
bytes are sent to device, they are correctly pro-
grammed at the request ed addres ses without hav-
ing any effects on the other bytes of the same
page.
Chip Select (S) must be driven High after the
eighth bi t of the last data byte has been l atched in,
otherwise the Page Program (PP) instr uction is not
executed.
As soon as Chip Select (S ) is dr iv en Hi gh , t he s elf -
time d Pa ge Progra m cycle (whose duratio n i s tPP)
is initiated. While the Page Program cycle is in
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit .
The Write In Progress ( WIP) bit is 1 during the self-
timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is complete, the Write Enable Latch (WEL)
bit is rese t.
A Page Program (PP) instruction applied to a page
that is Har dware Protect ed is not executed.
Any Page Program (PP) instruction, while an
Erase, Program or Write cycle is in progress, is re-
jected without having any effec ts o n the cycl e tha t
is in progr ess.
Figu re 14 . P age Program ( P P) Instructio n Seq uence
Note: 1. Address bits A23 to A17 are D on’t Ca re
2. 1 ≤ n ≤ 25 6
C
D
AI04044
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
D
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-Bit Address
0
765432 0
1
Data Byte 1
39
51
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3 Data Byte n
765432 0
1
MSB MSB
MSB MSB MSB
19/35
M45PE10
Page Erase (PE)
The Page Erase (PE) instruction sets to 1 (FFh) al l
bits inside the chosen p age. Before it can be ac-
cepted, a Write Enable (WREN) instruction must
previously have been executed. After the Write
Enable (WREN) instruction has been decoded,
the device sets the Write Enable Latch (WEL).
The Page Erase (PE) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, and three address by tes on Serial
Data Input (D). Any a ddress inside the Page is a
valid address for the P age Eras e (P E) instru ction.
Chip Select (S) must be driven Low for the entire
duration of the seq uence.
The instruct i on sequence is shown in Figure 15..
Chip Select (S) must be driven High after the
eighth bit of the last address byt e has been latched
in, otherwise the Page Erase (PE) instruction is
not executed. As soon as Chip Sel ect (S) is driven
High, the self-timed Pag e E rase cycle (w hose du-
ration is tPE) i s initiated. Whil e the Page Erase cy-
cle is in progress, the Stat us Register may be read
to check the value of the Write In Progress (WIP)
bit. The Wri t e In Progress (WIP) bit is 1 dur ing the
self-timed Page Erase cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is complete, the Write Enable Latch (WEL)
bit is rese t.
A Page Erase (PE) instruction applied to a page
that is Har dware Protect ed is not executed.
Any Page Erase (PE) instruction, while an Erase,
Prog ram or Write cycle is in progress, is rejected
without having any effects on the cycle that is in
progress.
Fig ur e 15. Page Eras e (PE) Instru ction S equ ence
Note: Address bi ts A23 to A17 are Don’ t Care.
24 Bit Address
C
D
AI04046
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
M45PE10
20/35
Sector Erase (SE)
The Sector E rase (SE) instruction sets t o 1 (FFh)
all bits inside the chosen sector. Before it can be
accepted, a Write Enable (WREN) instruction
must previously have been executed. After the
Write Enable (WREN) instruction has been decod-
ed, the device sets the Wr ite Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, and three address by tes on Serial
Data Input (D). Any address inside the Sector (see
Table 3.) is a valid address for the Sector Erase
(SE) instruction. Chip Select (S) must be driven
Low for the entire duration of the sequence.
The instruct i on sequence is shown in Figure 16..
Chip Select (S) must be driven High after the
eighth bit of the last address byt e has been latched
in, otherwise the Sector Erase (SE) instruction is
not executed. As soon as Chip Sel ect (S) is driven
High, the self-ti med Sector Erase cycle (whose du-
ration is tSE) is initiated. While the Sector Erase cy-
cle is in progress, the Stat us Register may be read
to check the value of the Write In Progress (WIP)
bit. The Wri t e In Progress (WIP) bit is 1 dur ing the
self-timed Sector Erase cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is complete, the Write Enable Latch (WEL)
bit is rese t.
A Sector Eras e (SE) instr uction appl ied to a s ector
that contains a page that is Hardware Protected is
not executed.
Any Sector Erase (SE) instruction, while an Eras e,
Prog ram or Write cycle is in progress, is rejected
without having any effects on the cycle that is in
progress.
Figure 16. Sector Erase (SE) Instruction Sequ ence
Note: Address bi ts A23 to A17 are Don’ t Care.
24 Bit Address
C
D
AI03751D
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
21/35
M45PE10
Deep Pow er-down (DP)
Executing the Deep Power-down (DP) instruction
is the only way to put the device in t he lowest con-
sumption mode (the Deep Power-down mode). It
can also be used as an extra software protecti on
mechanism, while the device is not in active use,
since in this mode, the device ignores all Write,
Program and Eras e instructions.
Driving Chip Select (S) High deselects the device,
and puts the device i n the Standby Power mode (if
there is no internal cycle currently in progress). But
this mode is not t he Deep Power-down mode. The
Deep Power-down mode can only be entered by
executing the Deep Power-down (DP) instru ction,
to reduce the standby current (from ICC1 to ICC2,
as specified in Table 11.).
Once the device has entered the Deep Power-
down mode, all instructions are ignored except the
Release from Deep Power-down (RDP) instruc-
tion. This releas es the device from this mode.
The Deep P ower-down m ode automaticall y stops
at Power-down, and the device always Powers-up
in the Sta ndby Powe r mode.
The Deep Power-down (DP) instructi on is entered
by driving Chip Select (S) Low, followed by the in-
struction code on Serial Data Inp ut (D ). Chip Se-
lect (S) m ust be d riven Low for the entire durat ion
of the seq uence.
The instruct i on sequence is shown in Figure 17..
Chip Select (S) must be driven High after the
eighth bi t of the instruction code has been l atched
in, otherwise t he Deep Power-down (DP) instruc -
tion is not executed. As soon as Chip Select (S) is
driven High, it requires a delay of tDP before the
supply current is reduced to ICC2 and the Deep
Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an
Erase, Program or Write cycle is in progress, is re-
jected without having any effec ts o n the cycl e tha t
is in progr ess.
Figure 17. Deep Power-down ( DP) Instruction Sequence
C
D
AI03753D
S
21 345670tDP
Deep Power-down Mode
Stand-by Mode
Instruction
M45PE10
22/35
Release from Deep Power-do wn (RDP)
Once the device has entered the Deep Power-
down mode, all instructions are ignored except the
Release from Deep Power-down (RDP) instruc-
tion. Executing this instruction takes the device out
of the Deep Power-down mode.
The Release from Deep Power-down (RDP) in-
struction is entered by driving Chip Select (S) Low,
followed by the instruction code on Serial Data In-
put (D). Chip Sel ect (S) must be driven Low for the
entire durat ion of the sequence.
The instruct i on sequence is shown in Figure 18..
The Release from Deep Power-down (RDP) in-
struction is terminated by driving Chip Select (S)
High. Sending additional clock cycles on Serial
Clock (C), while Chip Select (S) is driven Low,
cause the instruction to be rejected, and not exe-
cuted.
After Chip Select (S) has been driven High, fol-
lowed by a delay, tRDP, the device is put in the
Standby Power mode. Chip Select (S) must re-
main High at l east until this period i s over. The de-
vice waits to be selected, so that it can receive,
decode and execut e instructions.
Any Release from Deep Power-down (RDP) in-
struction, while an Erase, Program or Write cycle
is in progress, is rejected without having any ef-
fects on the cycle that is in progress.
Figure 18. Rel ease from Deep Power-d ow n (RDP) Instruction Seque nce
C
D
AI06807
S
21 345670tRDP
Stand-by Mode
Deep Power-down Mode
QHigh Impedance
Instruction
23/35
M45PE10
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must
not be selected (that is Chip Select (S ) must follow
the volt age appl ied on VCC) un t i l V CC reac he s the
correct value:
–V
CC(min) at Power-up, and then for a further
delay of tVSL
–V
SS at P o wer-down
Usually a simple pull-up resistor on Chip Select (S)
can be used to en sure safe and proper P ower-up
and Power-down.
To avoid data corruption and inadvertent write op-
erations during power up, a Power On Reset
(POR) circuit i s included. Th e logic i nside the de-
vice is held reset while VCC is less than the Power
On Reset (POR) t hreshold value, VWI – all opera-
tions are disabled, and the device does not re-
spond to any instruction.
Moreover, the device ignores all Write Enable
(WREN), Page Write (PW), Page Program (PP),
Page Erase (PE) and Sector Erase (SE) instruc-
tions until a time delay of tPUW has e lapsed after
the moment that VCC rises above t he VWI thresh-
old. However, the correct operation of the device
is not guaranteed if , by this time, VCC is still below
VCC(min). No Write, Program or Erase instructions
should be sent until the later of:
–t
PUW after VCC passed the VWI threshold
–t
VSL after wrap roundVCC passed the
VCC(min) level
These values are specified in Table 6..
If the delay, tVSL, has elapsed, after VCC has risen
above VCC(min), the device can be selected for
READ instructions even if the tPUW delay is not y et
fully elapsed.
As an extra protection, the Reset (Reset) signal
can be driven Low for the whole duration of the
Power-up and Power-down phases.
At Power-up, the dev ice is in the following state:
– The device is in the Standby Power mode (not
the Deep Power-down m ode).
– The Write Enable Latch (WEL) bit is reset.
Normal precautions must be taken for supply rail
decoupli ng, to stabilize the VCC supply. Each de-
vice in a system should have the VCC rail decou-
pled by a suitable capacitor close to the package
pins. (Generally, this capacitor is of the order of
0.1µF).
At Power-down, when VCC drops from the operat-
ing voltage, to below the Po wer On Reset (POR)
threshold value, VWI, all operations are disabled
and the device does not respond to any instruc-
tion. (The designer needs to be aware that if a
Power-down occurs while a Write, Program or
Erase cycle is in progress, some data corruption
can result.)
Figure 19. Power-up Timing
VCC
AI04009C
VCC(min)
VWI
Reset State
of the
Device
Chip Selection Not Allowed
Program, Erase and Write Commands are Rejected by the Device
tVSL
tPUW
time
Read Access allowed Device fully
accessible
VCC(max)
M45PE10
24/35
Table 6. Power-Up Timing and VWI Thresh ol d
Note: 1. These parameters are character i zed only, over the tem perature range –40°C to +85°C.
INITIAL DEL IVE RY STATE
The device is delivered with the memory array
erased: all bits are set to 1 (each byte contains
FFh). All usable Status Register bi ts are 0.
Symbol Parameter Min. Max. Unit
tVSL1VCC(min) to S low 30 µs
tPUW1Time delay before the first Write, Program or Erase instruction 1 10 ms
VWI1Write Inhibit Voltage 1.5 2.5 V
25/35
M45PE10
MAXI MUM RAT IN G
Stressing the device outside the ratings listed in
Table 7. may cause permanent damage to the de-
vice. These are s tress ratings only, and operation
of the device at these, or any other conditions out-
side those indicated in the Operating sections of
this specification, is not implied. Exposure to Ab-
solute Maximum Rating conditions for extended
periods may af fect device rel iability. Refer also to
the STMicroelectroni cs SURE Program and ot her
relevant quali ty documents.
Table 7. Absolute Maxi mum Ratings
Note : 1. Comp liant wit h JEDEC Std J- STD- 020 B (for sm all bod y, Sn -Pb or Pb as sem bly ), the ST EC OPA CK ® 7191395 spec i f ication, and
the Eu ropean di rectiv e on Restr i ct i ons on Haz ardous S ubstan ces (RoH S ) 2002/95/EU
2. JED EC St d J ESD22 -A 114A (C 1=100 pF, R1 =1500 Ω, R2=500 Ω)
Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 150 °C
TLEAD Lead Temperature during Soldering See note 1°C
VIO Input and Output Voltage (with respect to Ground) –0.6 4.0 V
VCC Supply Voltage –0.6 4.0 V
VESD Electrostatic Discharge Voltage (Human Body model) 2–2000 2000 V
M45PE10
26/35
DC AND A C PARAMETE RS
This section summarizes the operating and mea-
surement condition s, and the DC and AC charac-
teristics o f the device. The para meters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Des igners shoul d c heck that the operating
conditions in t heir circuit matc h the measurem ent
conditions when relying on the quoted parame-
ters.
Table 8. Operating Conditions
Table 9. AC Measu remen t Conditions
Note: O ut put Hi-Z is define d as the point where data ou t is no l onger dri ven.
Figu re 20. AC Measurement I/O W av eform
Table 10. Capacitanc e
Note: Sampled o nl y, not 100% tested , at TA= 25°C and a frequency of 20 M Hz .
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 2.7 3.6 V
TAAmb ient Operati ng Tem peratur e –40 85 °C
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 30 pF
Input Rise and Fall Times 5 ns
Input Pulse Voltages 0.2VCC to 0.8VCC V
Input and Output Timing Reference Voltages 0.3VCC to 0.7VCC V
Symbol Parameter Test Condition Min.Max.Unit
COUT Output Capacitance (Q) VOUT = 0V 8 pF
CIN Input Capacitance (other pins) VIN = 0V 6 pF
AI00825B
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and Output
Timing Reference Levels
Input Levels
27/35
M45PE10
Table 11. DC Characteristics
Symbol Parameter Test Condition
(in addition to those in Table 8.)Min. Max. Unit
ILI Input Leakage Current ± 2 µA
ILO Output Leakage Current ± 2 µA
ICC1 Standby Current
(Stand by and Reset modes) S = VCC, VIN = VSS or VCC 50 µA
ICC2 Deep Power-down Current S = VCC, VIN = VSS or VCC 10 µA
ICC3 Operating Current (FAST_READ) C = 0.1VCC / 0.9.VCC at 25 MHz,
Q = open 6mA
ICC4 Operating Current (PW) S = VCC 15 mA
ICC5 Operating Current (SE) S = VCC 15 mA
VIL Input Low Voltage – 0.5 0.3VCC V
VIH Input High Volta ge 0.7VCC VCC+0.4 V
VOL Output Low Voltage IOL = 1.6 mA 0.4 V
VOH Output High Voltage IOH = –10 0 µAV
CC–0.2 V
M45PE10
28/35
Table 12. AC Characteristics
Note: 1. tCH + tCL must be gr eater th an or equal to 1/ f C(max)
2. Value guaranteed by characterization, not 100% tested i n product i on.
Test conditions specified in Table 8. and Table 9.
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfC
Clock Fre quen cy for the following
instructions: FAST_READ, PW, PP,
PE, SE, DP, RDP, WREN, WRDI,
RDSR
D.C. 25 MHz
fRClock Fre quen cy for READ
instructions D.C. 20 MHz
tCH 1tCLH Clock High Time 18 ns
tCL 1tCLL Cl ock Low Tim e 18 ns
Clock Slew Rate 2 (peak to peak) 0.03 V/ns
tSLCH tCSS S Active Setup Time (relative to C) 10 ns
tCHSL S Not Active Hold Time (relative to C) 10 ns
tDVCH tDSU Data In Setup Time 5 ns
tCHDX tDH Data In Hold Time 5 ns
tCHSH S Active Hold Time (relative to C) 10 ns
tSHCH S Not Activ e Setup Time (relative to C) 10 ns
tSHSL tCSH S Deselect Time 200 ns
tSHQZ 2tDIS Output Disable Time 15 ns
tCLQV tVClock Low to Output Valid 15 ns
tCLQX tHO O utput Hold Time 0 ns
tRLRH 2tRST Reset Pulse Width 10 µs
tRHSL tREC Reset Recovery Time 3 µs
tSHRH Chip should have been deselected
before Reset is de-asserted 10 ns
tWHSL Write Protect Setup Time 50 ns
tSHWL Write Protect Hold Time 100 ns
tDP 2S to Deep Power-down 3 µs
tRDP 2S High to Standby Power mode 30 µs
tPW Page Write Cycle Time 11 25 ms
tPP Page Program Cycle Time 1.2 5 ms
tPE Page Erase Cycle Time 10 20 ms
tSE Sector Erase Cycle Time 1 5 s
29/35
M45PE10
Figu re 21 . Seri a l Input Timing
Figu re 22 . Wri t e Pr ote ct Se tu p and Hol d Ti m in g
C
D
AI01447C
S
MSB IN
Q
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
C
D
S
Q
High Impedance
W
tWHSL tSHWL
AI07439
M45PE10
30/35
Figu re 23. Ou t pu t Tim i ng
Figure 24. Reset AC Wavefo rms
C
Q
AI01449D
S
LSB OUT
D
ADDR.LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
AI06808
Reset tRLRH
S
tRHSLtSHRH
31/35
M45PE10
P ACKAGE ME CHANICAL
Figure 25. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width , Packag e Outline
No te : Drawing is not to scal e.
Table 13. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
Symb. mm inches
Typ. Min. Max. Typ. Min. Max.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e1.27––0.050––
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α0° 8° 0° 8°
N8 8
CP 0.10 0.004
SO-a
E
N
CP
Be
A
D
C
LA1 α
1H
h x 45˚
M45PE10
32/35
Figure 26. MLP8, 8-lead Very thin Dual Flat Pack age No lead, 6x5mm , Package Ou tline
No te : Drawing is not to scal e.
Table 14. MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5m m , Packag e Mechanical Data
Symb. mm inches
Typ. Min. Max. Typ. Min. Max.
A 0.85 1.00 0.0335 0.0394
A1 0.00 0.05 0.0000 0.0020
A2 0.65 0.0256
A3 0.20 0.0079
b 0.40 0.35 0.48 0.0157 0.0138 0.0189
D 6.00 0.2362
D1 5.75 0.2264
D2 3.40 3.20 3.60 0.1339 0.1260 0.1417
E 5.00 0.1969
E1 4.75 0.1870
E2 4.00 3.80 4.20 0.1575 0.1496 0.1654
e 1.27 0.0500
L 0.60 0.50 0.75 0.0236 0.0197 0.0295
θ12° 12°
D
E
VDFPN-01
A2
A
A3
A1
E1
D1
eE2
D2
L
b
θ
33/35
M45PE10
PART NUMBERING
Table 15. Ordering Information Scheme
Note: 1. Avai l able f or S O 8 package only
2. Available for MLP pa ck age only
For a list of available options (speed, package,
etc.) or for further i nf ormation on any aspect of this device, please c ontact your neares t ST Sales O f-
fice.
Example: M45PE10 – V MP 6 T P
Device Type
M45PE = Serial Flash Memory for Data Storage
Device Function
10 = 1Mbit (128K x 8)
Operating Voltage
V = VCC = 2.7 to 3.6V
Package
MN = SO8 (150 mil width)
MP = VDFPN8 6x5mm (MLP8)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
P1 = Lead-Free and RoHS compliant
G2 = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free
M45PE10
34/35
REVISION HISTORY
Table 16. Document Revi sion History
Date Version Description of Revision
29-Apr-2003 1.0 Document written
04-Jun-2003 1.1 Description corrected of entering Hardware Protected mode (W must be driven, and
cannot be left unconnected).
04-Dec-2003 1.2 VIO(min) e xtended to –0.6V, tPW(typ) and tPP(typ) improv ed. Table of contents, w arning
about exposed paddle on MLP8, and Pb-free options added. Change of naming for
VDFPN8 package
25-Jun-2004 1.3 Soldering temperature information clarified for RoHS compliant devices. Device Gr ade
clarified
22-Sep-2004 2.0 Document promoted to Preliminary Data. Minor wording changes
08-Oct-2004 3.0 Document promoted to Mature Datasheet. No other changes
35/35
M45PE10
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication ar e s ub j ect
to change without notice. This publication supersedes and replaces all information previously supplied. STMi croelectronics product s are not
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