SN54HC646, SN74HC646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS150C – DECEMBER 1982 – REVISED MARCH 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Wide Operating Voltage Range of 2 V to 6 V
D
High-Current 3-State Outputs Can Drive Up
To 15 LSTTL Loads
D
Low Power Consumption, 80-µA Max ICC
D
Typical tpd = 11 ns
D
±6-mA Output Drive at 5 V
D
Low Input Current of 1 µA Max
D
Independent Registers for A and B Buses
D
Multiplexed Real-Time and Stored Data
D
True Data Paths
14 15 16 17
SN54HC646 ...JT OR W PACKAGE
SN74HC646 . . . DW OR NT PACKAGE
(TOP VIEW)
SN54HC646 . . . FK PACKAGE
(TOP VIEW)
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
4321 28
12 13
OE
B1
B2
NC
B3
B4
B5
A1
A2
A3
NC
A4
A5
A6
DIR
SAB
CLKAB
B8
B7
A8
GND
NC NC
CLKBA
SBA
V
A7
B6
18
27 26
CC
NC – No internal connection
description/ordering information
The ’HC646 devices consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control
circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers.
Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB
or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed
with the ’HC646 devices.
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver
mode, data present at the high-impedance port may be stored in either or both registers.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR
determines which bus receives data when OE is active (low). In the isolation mode (OE high), A data may be
stored in one register and/or B data may be stored in the other register.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP – NT Tube SN74HC646NT SN74HC646NT
–40°C to 85°C
SOIC DW
Tube SN74HC646DW
HC646
SOIC
–
DW
Tape and reel SN74HC646DWR
HC646
CDIP – JT Tube SNJ54HC646JT SNJ54HC646JT
–55°C to 125°CCFP – W Tube SNJ54HC646W SNJ54HC646W
LCCC – FK Tube SNJ54HC646FK SNJ54HC646FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54HC646, SN74HC646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS150C – DECEMBER 1982 – REVISED MARCH 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
When an output function is disabled, the input function is still enabled and can be used to store data. Only one
of the two buses, A or B, may be driven at a time.
FUNCTION TABLE
INPUTS DATA I/O
OPERATION OR FUNCTION
OE DIR CLKAB CLKBA SAB SBA A1–A8 B1–B8
OPERATION
OR
FUNCTION
X X ↑X X X Input Unspecified†Store A, B unspecified†
XXX ↑X X Unspecified†Input Store B, A unspecified†
H X ↑ ↑ X X Input Input Store A and B data
HX H or L H or L X X Input disabled Input disabled Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
LL X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B bus
L H H or L X H X Input Output Stored A data to B bus
†The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
SN54HC646, SN74HC646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS150C – DECEMBER 1982 – REVISED MARCH 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
L
3
DIR
L
1
CLKAB
X
23
CLKBA
X
2
SAB
X
22
SBA
L
REAL-TIME TRANSFER
BUS B TO BUS A
21
L
3
DIR
H
1
CLKAB
X
23
CLKBA
X
2
SAB
L
22
SBA
X
REAL-TIME TRANSFER
BUS A T O BUS B
21
X
3
DIR
X
1
CLKAB 23
CLKBA
X
2
SAB
X
22
SBA
X
STORAGE FROM
A, B, OR A AND B
21
L
3
DIR
L
1
CLKAB
X
23
CLKBA
H or L
2
SAB
X
22
SBA
H
TRANSFER STORED DATA
TO A AND/OR B
X
HX
XXX
XX
XL H H or L X H X
↑↑
↑↑
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OE OE
OEOE
Pin numbers shown are for the DW, JT, NT, and W packages.
Figure 1. Bus-Management Functions
SN54HC646, SN74HC646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS150C – DECEMBER 1982 – REVISED MARCH 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
A1 B1
One of Eight Channels
SAB
CLKAB
SBA
CLKBA
DIR
OE
To Seven Other Channels
21
3
23
22
1
2
420
1D
C1
1D
C1
Pin numbers shown are for the DW, JT, NT, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DW package 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): NT package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-3.
SN54HC646, SN74HC646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS150C – DECEMBER 1982 – REVISED MARCH 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
SN54HC646 SN74HC646
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0.5 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VCC = 6 V 1.8 1.8
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
VCC = 2 V 1000 1000
ttInput transition (rise and fall) time VCC = 4.5 V 500 500 ns
VCC = 6 V 400 400
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C SN54HC646 SN74HC646
UNIT
PARAMETER
TEST
CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA4.5 V 4.4 4.499 4.4 4.4
VOH VI = VIH or VIL 6 V 5.9 5.999 5.9 5.9 V
IOH = –6 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –7.8 mA 6 V 5.48 5.8 5.2 5.34
2 V 0.002 0.1 0.1 0.1
IOL = 20 µA4.5 V 0.001 0.1 0.1 0.1
VOL VI = VIH or VIL 6 V 0.001 0.1 0.1 0.1 V
IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 7.8 mA 6 V 0.15 0.26 0.4 0.33
IIControl
inputs VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
IOZ A or B VO = VCC or 0 6 V ±0.01 ±0.5 ±10 ±5µA
ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA
CiControl
inputs 2 V to 6 V 3 10 10 10 pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54HC646, SN74HC646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS150C – DECEMBER 1982 – REVISED MARCH 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25°C SN54HC646 SN74HC646
UNIT
V
CC MIN MAX MIN MAX MIN MAX
UNIT
2 V 6 4.3 5.5
fclock Clock frequency 4.5 V 31 22 27 MHz
6 V 36 25 31
2 V 80 115 95
twPulse duration, CLKBA or CLKAB high or low 4.5 V 16 23 19 ns
6 V 14 20 16
2 V 100 150 125
tsu Setup time, A before CLKAB
or B before CLKBA
4.5 V 20 30 25 ns
6 V 17 26 21
2 V 5 5 5
thHold time, A after CLKAB
or B after CLKBA
4.5 V 5 5 5 ns
6 V 5 5 5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54HC646, SN74HC646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS150C – DECEMBER 1982 – REVISED MARCH 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 2)
PARAMETER
FROM TO
VCC
TA = 25°C SN54HC646 SN74HC646
UNIT
PARAMETER
(INPUT) (OUTPUT)
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 611 4.4 5.5
fmax 4.5 V 31 54 22 27 MHz
6 V 36 64 25 31
2 V 65 180 270 225
CLKBA or CLKAB A or B 4.5 V 18 36 54 45
6 V 14 31 46 38
2 V 50 135 205 170
tpd A or B B or A 4.5 V 14 27 41 34 ns
6 V 11 23 35 29
†
2 V 70 190 285 240
SBA or SAB
†
A or B 4.5 V 20 38 57 48
6 V 16 32 48 41
2 V 85 245 370 305
ten OE A or B 4.5 V 25 49 74 61 ns
6 V 20 42 63 52
2 V 85 245 370 305
tdis OE A or B 4.5 V 25 49 74 61 ns
6 V 20 42 63 52
2 V 80 245 370 305
ten DIR A or B 4.5 V 25 49 74 61 ns
6 V 20 42 63 52
2 V 80 245 370 305
tdis DIR A or B 4.5 V 25 49 74 61 ns
6 V 20 42 63 52
2 V 28 60 90 75
ttAny 4.5 V 8 12 18 15 ns
6 V 6 10 15 13
†These parameters are measured with the internal output state of the storage register opposite that of the bus input.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54HC646, SN74HC646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS150C – DECEMBER 1982 – REVISED MARCH 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 2)
PARAMETER
FROM TO
VCC
TA = 25°C SN54HC646 SN74HC646
UNIT
PARAMETER
(INPUT) (OUTPUT)
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 90 265 400 330
CLKBA or CLKAB A or B 4.5 V 24 53 80 66
6 V 20 46 68 57
2 V 70 220 335 280
tpd A or B B or A 4.5 V 20 44 67 56 ns
6 V 15 38 57 49
†
2 V 80 275 415 345
SBA or SAB
†
A or B 4.5 V 24 55 83 69
6 V 20 47 70 60
2 V 113 330 500 410
OE A or B 4.5 V 33 66 100 82
t
6 V 27 57 85 71
ns
t
en 2 V 113 330 500 410
ns
DIR A or B 4.5 V 33 66 100 82
6 V 27 57 85 71
2 V 45 210 315 265
ttAny 4.5 V 17 42 63 53 ns
6 V 13 36 53 43
†These parameters are measured with the internal output state of the storage register opposite that of the bus input.
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load 50 pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54HC646, SN74HC646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS150C – DECEMBER 1982 – REVISED MARCH 2003
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
50%
50%50% 10%10% 90% 90%
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
50%
High-Level
Pulse 50% VCC
0 V
50% 50%
VCC
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50% 10%10% 90% 90%
VCC
VOH
VOL
0 V
trtf
Input
In-Phase
Output
50%
tPLH tPHL
50% 50%
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-
Phase
Output
50%
10%
90%
VCC
≈VCC
VOL
0 V
Output
Control
(Low-Level
Enabling)
Output
W aveform 1
(See Note B)
50%
tPZL tPLZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOH
≈0 V
50%
50%
tPZH tPHZ
Output
W aveform 2
(See Note B)
≈VCC
Test
Point
From Output
Under Test
RL
VCC
S1
S2
LOAD CIRCUIT
PARAMETER CL
tPZH
tpd or tt
tdis
ten tPZL
tPHZ
tPLZ
1 kΩ
1 kΩ
50 pF
or
150 pF
50 pF
Open Closed
RLS1
Closed Open
S2
Open Closed
Closed Open
50 pF
or
150 pF Open Open––
NOTES: A. CL includes probe and test-fixture capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily . All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmax is measured when the input duty cycle is 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
CL
(see Note A)
Figure 2. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74HC646DW ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC646DWE4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC646DWG4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC646DWR ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC646DWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC646DWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC646NT ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74HC646NT3 OBSOLETE PDIP NT 24 TBD Call TI Call TI
SN74HC646NTE4 ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HC646DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC646DWR SOIC DW 24 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
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