Si8285/86 Data Sheet ISODrivers with System Safety Features KEY FEATURES The Si828x (Si8285 and Si8286) are isolated, high current gate drivers with integrated system safety and feedback function. The devices are ideal for driving power MOSFETs and IGBTs used in a wide variety of inverter and motor control applications. The Si8285 and Si8286 isolated gate drivers utilize Silicon Labs' proprietary silicon isolation technology, supporting up to 5.0 kVrms withstand voltage per UL1577. This technology enables higher-performance, reduced variation with temperature and age, tighter part-to-part matching, and superior common-mode rejection compared to other isolated gate driver technologies. * Enables use with IGBTs rated for 1200 V VCE, 300 A IC * System Safety Features * DESAT detection * FAULT feedback * Undervoltage Lock Out (UVLO) * Soft shutdown on fault condition The input to the device is a complementary digital input that can be utilized in several configurations. The input side of the isolation also has several control and feedback digital signals. The controller to the device receives information about the driver side power state (Si8285) and fault state of the device and recovers the device from fault through an active-low reset pin. * Silicon Labs' high-performance isolation technology * Industry leading noise immunity On the output side, the Si8285 provides separate pull-up and pull-down pins for the gate. The Si8286 has a single pin for both functions. A dedicated DSAT pin detects the desaturation condition and immediately shuts down the driver in a controlled manner. The Si8285 device also integrates a Miller clamp to facilitate a strong turn-off of the power switch. * 30 V driver-side supply voltage Automotive Grade is available for certain part numbers. These products are built using automotive-specific flows at all steps in the manufacturing process to ensure the robustness and low defectivity required for automotive applications. Industrial Applications Safety Regulatory Approvals (Pending) * IGBT/ MOSFET gate drives * UL 1577 recognized * Industrial and renewable energy inver* Up to 5000 VRMS for 1 minute ters * CSA component notice 5A approval * AC, Brushless, and DC motor controls * IEC 60950-1 (reinforced insulation) and drives * VDE certification conformity * Variable speed motor control in consum* VDE0884 Part 10 (basic insulation) er white goods * CQC certification approval * Isolated switch mode and UPS power * GB4943.1 (reinforced insulation) supplies * High speed, low latency and skew * Best reliability available * Integrated Miller clamp (Si8285 only) * Power ready pin (Si8285 only) * Complementary driver control input * Si8286 pin-out compatible with HCPL-316J * Compact package: 16-pin wide-body SOIC * Industrial temperature range: -40 to 125 C * Automotive-grade OPNs available * AIAG compliant PPAP documentation support * IMDS and CAMDS listing support * AEC-Q100 Qualified Automotive Applications * Hybrid electric and electric vehicles * Traction inverters * Electric motor controllers * Inductive chargers silabs.com | Building a more connected world. Rev. 1.0 Si8285/86 Data Sheet Ordering Guide 1. Ordering Guide Table 1.1. Si8285, Si8286 Ordering Guide New Ordering Part Number (OPN) Ordering Options Output Pin Compatibility UVLO Voltage Insulation Rating Package Type Configuration Available Now Si8285BC-IS 4.0 A driver -- 9V 3.75 kVrms WB SOIC-16 Si8285CC-IS 4.0 A driver -- 12 V 3.75 kVrms WB SOIC-16 Si8286BC-IS 4.0 A driver HCPL-316J 9V 3.75 kVrms WB SOIC-16 Si8286CC-IS 4.0 A driver HCPL-316J 12 V 3.75 kVrms WB SOIC-16 Si8285BD-IS 4.0 A driver -- 9V 5.0 kVrms WB SOIC-16 Si8285CD-IS 4.0 A driver -- 12 V 5.0 kVrms WB SOIC-16 Si8286BD-IS 4.0 A driver HCPL-316J 9V 5.0 kVrms WB SOIC-16 Si8286CD-IS 4.0 A driver HCPL-316J 12 V 5.0 kVrms WB SOIC-16 Sample Now Note: 1. Visit www.silabs.com for detailed quality data. 2. "Si" and "SI" are used interchangeably. 3. AEC-Q100 qualified. 4. Add an "R" at the end of the Part Number to denote Tape and Reel option. silabs.com | Building a more connected world. Rev. 1.0 | 2 Si8285/86 Data Sheet Ordering Guide 1.1 Automotive Grade OPNs Automotive-grade devices are built using automotive-specific flows at all steps in the manufacturing process to ensure robustness and low defectivity. These devices are supported with AIAG-compliant Production Part Approval Process (PPAP) documentation, and feature International Material Data System (IMDS) and China Automotive Material Data System (CAMDS) listing. Qualifications are compliant with AEC-Q100, and a zero-defect methodology is maintained throughout definition, design, evaluation, qualification, and mass production steps. Table 1.2. Ordering Guide for Automotive Grade OPNs New Ordering Part Number (OPN) Ordering Options Output Pin Compatibility UVLO Voltage Insulation Rating Package Type Configuration Available Now SI8285CC-AS 4.0 A driver -- 12 V 3.75 kVrms WB SOIC-16 SI8286CC-AS 4.0 A driver HCPL-316J 12 V 3.75 kVrms WB SOIC-16 SI8285CD-AS 4.0 A driver -- 12 V 5.0 kVrms WB SOIC-16 SI8286CD-AS 4.0 A driver HCPL-316J 12 V 5.0 kVrms WB SOIC-16 Sample Now Note: 1. All packages are RoHS-compliant. 2. "Si" and "SI" are used interchangeably. 3. An "R" at the end of the part number denotes tape and reel packaging option. 4. Automotive-Grade devices (with an "-A" suffix) are identical in construction materials, topside marking, and electrical parameters to their Industrial-Grade (with a "-I" suffix) version counterparts. Automotive-Grade products are produced utilizing full automotive process flows and additional statistical process controls throughout the manufacturing flow. The Automotive-Grade part number is included on shipping labels. 5. Additional Ordering Part Numbers may be available in Automotive-Grade. Please contact your local Silicon Labs sales representative for further information. silabs.com | Building a more connected world. Rev. 1.0 | 3 Table of Contents 1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 Automotive Grade OPNs . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Isolation Channel Description . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.5 Desaturation Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 Soft Shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.7 Fault (FLTb) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.8 Reset (RSTb) Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.9 Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . 9 2.10 Ready (RDY) Pin (Si8285 Only) . . . . . . . . . . . . . . . . . . . . . . . 9 2.11 Miller Clamp . . . . . . . . . . . . . . . . . . . . . . . 9 . . . . . . . 3. Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Recommended Application Circuits. 3.1.1 Power . . . . . . . . 3.1.2 Inputs . . . . . . . . 3.1.3 Reset, RDY, and Fault . . . 3.1.4 Desaturation . . . . . . 3.1.5 Driver Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 .11 .11 .12 .12 .12 3.2 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . .12 3.3 Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . .13 4. Electrical Specifications 4.1 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 . . . . . . . . . . . . . . . . . . . . . . .20 4.2 Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . .21 4.3 Regulatory Information . . . . . . . . . . . . . . . . . . . . . . .24 5. Pin Descriptions 6. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . .28 6.2 Land Pattern: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . .30 6.3 Top Marking: 16-Pin Wide Body SOIC. . . . . . . . . . . . . . . . . . . . . .31 7. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.1 Revision 0.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 7.2 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 silabs.com | Building a more connected world. Rev. 1.0 | 4 Si8285/86 Data Sheet System Overview 2. System Overview 2.1 Isolation Channel Description The operation of a Si8285 or Si8286 channel is analogous to that of an optocoupler and gate driver, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single Si828x channel is shown in the figure below. Transmitter Receiver RF OSCILLATOR A Input Logic MODULATOR VDD SemiconductorBased Isolation Barrier VH DEMODULATOR + NOISE FILTER VL Gnd Figure 2.1. Simplified Channel Diagram A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. silabs.com | Building a more connected world. Rev. 1.0 | 5 Si8285/86 Data Sheet System Overview 2.2 Device Behavior The following tables show the truth tables for the Si8285 and Si8286. Table 2.1. Si8285 Truth Table IN+ IN- VDDA State VDDB-VMID State Desaturation State VH VL RDY FLTb H H Powered Powered Undetected Hi-Z Pull-down H H H L Powered Powered Undetected Pull-up Hi-Z H H L X Powered Powered Undetected Hi-Z Pull-down H H X X Powered Unpowered -- -- -- L H X X Powered Powered Detected Hi-Z Pull-down1 H L Note: 1. Driver state after soft shutdown. Table 2.2. Si8286 Truth Table IN+ IN- VDDA State VDDB-VMID State Desaturation State VO FLTb H H Powered Powered Undetected Low H H L Powered Powered Undetected High H L X Powered Powered Undetected Low H X X Powered Powered Detected Low1 L Note: 1. Driver state after soft shutdown. silabs.com | Building a more connected world. Rev. 1.0 | 6 Si8285/86 Data Sheet System Overview 2.3 Input The IN+ and IN- inputs to the Si828x devices act as a complementary pair. If the IN- is held low, the IN+ will act as a active-high input for the driver control. Alternatively, if IN+ is held high, then the IN- can be used as an active-low input for driver control. When the IN- is used as the control signal, taking the IN+ low will hold the output driver low. HIGH IN+ LOW IN _ HIGH LOW VH Pull-up Hi-Z Hi-Z VL Pull-down Figure 2.2. Si828x Complementary Input Diagram 2.4 Output The Si8285 and Si8286 devices are different in how the driver output is presented. The Si8285 has separate pins for gate drive high (VH) and gate drive low (VL). This makes it simple for the user to use different gate resistors to control IGBT VCE rise and fall time. The Si8286 has both actions combined in the single VO pin. A weak internal pulldown resistor of about 200 k is provided to ensure that the driver output defaults to low if power on the secondary side is interrupted. silabs.com | Building a more connected world. Rev. 1.0 | 7 Si8285/86 Data Sheet System Overview 2.5 Desaturation Detection The Si828x provides sufficient voltage and current to drive and keep the IGBT in saturation during on time to minimize power dissipation and maintain high efficiency operation. However, abnormal load conditions can force the IGBT out of saturation and cause permanent damage to the IGBT. To protect the IGBT during abnormal load conditions, the Si828x detects an IGBT desaturation condition, shuts down the driver upon detecting a fault, and provides a fault indication to the controller. These integrated features provide desaturation protection with minimum external BOM cost. The figure below illustrates the Si828x desaturation circuit. When the Si828x driver output is high, the internal current source is on, and this current flows from the DSAT pin to charge the CBL capacitor. The voltage on the DSAT pin is monitored by an internal comparator. Since the DSAT pin is connected to the IGBT collector through the DDSAT and a small RDSAT, its voltage is almost the same as the VCE of the IGBT. If the VCE of the IGBT does not drop below the Si828x desaturation threshold voltage within a certain time after turning on the IGBT (blanking period) the block will generate a fault signal. The Si828x desaturation hysteresis is fixed at 220 mV and threshold is nominally 7 V. Driver ControlSignal Ichg DSAT DDSAT RDSAT CBL Fault Signal DESAT Sense Driver Disable VMID 7V Figure 2.3. Desaturation Circuit As an additional feature, the block supports a blanking timer function to mask the turn-on transient of the external switching device and avoid unexpected fault signal generation. This function requires an external blanking capacitor, CBL, of typically 100 pF between DSAT and VMID pins. The block includes a 1 mA current source (IChg) to charge the CBL. This current source, the value of the external CBL, and the programmed fault threshold, determine the blanking time (tBlanking). t Blanking = C BI x V DESAT I chg An internal nmos switch is implemented between DSAT and VMID to discharge the external blanking capacitor, CBL, and reset the blanking timer. The current limiting RDSAT resistor protects the DSAT pin from large current flow toward the IGBT collector during the IGBT's body diode freewheeling period (with possible large collector's negative voltage, relative to IGBT's emitter). 2.6 Soft Shutdown To avoid excessive dV/dt on the IGBT's collector during fault shut down, the Si828x implements a soft shut down feature to discharge the IGBT's gate slowly. When soft shut down is activated, the high power driver goes inactive, and a weak pull down via VH and external RH discharges the gate until the gate voltage level is reduced to the VSSB + 2 V level. The high power driver is then turned on to clamp the IGBT gate voltage to VMID. After the soft shut down, the Si828x driver output voltage is clamped low to keep the IGBT in the off state. 2.7 Fault (FLTb) Pin FLTb is an open-drain type output. A pull-up resistor takes the pin high. When the desaturation condition is detected, the Si828x indicates the fault by bringing the FLTb pin low. FLTb stays low until the controller brings the RSTb pin low. silabs.com | Building a more connected world. Rev. 1.0 | 8 Si8285/86 Data Sheet System Overview 2.8 Reset (RSTb) Pin The RSTb pin is used to clear the desaturation condition and bring the Si828x driver back to an operational state. Even though the input may be toggling, the driver will not change state until the fault condition has been reset. 2.9 Undervoltage Lockout (UVLO) The UVLO circuit unconditionally drives VL low when VDDB is below the lockout threshold. The Si828x is maintained in UVLO until VDDB rises above VDDBUV+. During power down, the Si828x enters UVLO when VDDB falls below the UVLO threshold plus hysteresis (i.e., VDDB < VDDBUV+ - VDDBHYS). 2.10 Ready (RDY) Pin (Si8285 Only) The ready pin indicates to the controller that power is available on both sides of the isolation, i.e., at VDDA and VDDB. RDY goes high when both the primary side and secondary side UVLO circuits are disengaged. If the UVLO conditions are met on either side of the isolation barrier, the ready pin will return low. RDY is a push-pull output pin and can be floated if not used. 2.11 Miller Clamp IGBT power circuits are commonly connected in a half bridge configuration with the collector of the bottom IGBT tied to the emitter of the top IGBT. When the upper IGBT turns on (while the bottom IGBT is in the off state), the voltage on the collector of the bottom IGBT flies up several hundred volts quickly (fast dV/dt). This fast dV/dt induces a current across the IGBT collector-to-gate capacitor (CCG that constitutes a positive gate voltage spike and can turn on the bottom IGBT. This behavior is called Miller parasitic turn on and can be destructive to the switch since it causes shoot through current from the rail right across the two IGBTs to ground. The Si828x Miller clamp's purpose is to clamp the gate of the IGBT device being driven by the Si828x to prevent IGBT turn on due to the collector CCG coupling. VDDB Driver Control CCG VH RSS Soft Shutdown VL VSSB RH RL Driver Control VSSB CLMP 2.0 V VSSB Figure 2.4. Miller Clamp Device The Miller clamp device (Clamp) is engaged after the main driver had been on (VL) and pulled IGBT gate voltage close to VSSB, such that one can consider the IGBT being already off. This timing prevents the Miller clamp from interfering with the driver's operation. The engaging of the Miller Clamp is done by comparing the IGBT gate voltage with a 2.0 V reference (relative to VSSB) before turning on the Miller clamp NMOS. silabs.com | Building a more connected world. Rev. 1.0 | 9 Si8285/86 Data Sheet Applications Information 3. Applications Information The following sections detail the input and output circuits necessary for proper operation. 3.1 Recommended Application Circuits Place RDSAT, CBL, and DDSAT as close to Q1 as possible + RAIL RDSAT U1 +3.3V 0.1uF 1 2 3 5 VDDA DSAT VDDB RSTb VH FLTb VL RDY CLMP IN+ VMID 6 7 100pF NC NC 4 MCU GNDA 8 IN- VSSB DDSAT 16 15 15V 0.1uF CBL 14 Q1 RH 13 RL 12 11 10 9 10uF 0.1uF 9V Q2 Si8285 - RAIL Figure 3.1. Recommended Si8285 Application Circuit Place RDSAT, DDSAT, CBL as close to Q1 as possible RDSAT 0.1uF 1 +3.3V 2 3 MCU 0.1uF 4 5 6 100pF 7 8 IN+ IN- VMID NC VDDA DSAT GNDA VDDB RSTb VDDB FLTb NC NC VO VSSB VSSB DDSAT + RAIL 15V 16 15 Q1 CBL 14 13 12 Rg 11 10 9 10uF 0.1uF 9V Si8286 Q2 - RAIL Figure 3.2. Recommended Si8286 Application Circuit silabs.com | Building a more connected world. Rev. 1.0 | 10 Si8285/86 Data Sheet Applications Information Place RDSAT, DDSAT, CBL as close to Q1 as possible RDSAT 0.1uF 1 +3.3V 2 3 MCU 0.1uF 4 5 6 7 8 IN+ IN- VMID NC VDDA DSAT GNDA VDDB RSTb VDDB FLTb NC NC VO VSSB VSSB DDSAT + RAIL 15V 16 15 Q1 CBL 14 13 12 RH 11 RL 10 9 10uF 0.1uF 9V Si8286 Q2 - RAIL Figure 3.3. Recommended Si8286 Application Circuit with RH and RL The Si828x has both inverting and non-inverting gate control inputs (IN- and IN+). In normal operation, one of the inputs is not used, and should be connected to GNDA (IN-) or VDDA (IN+) respectively for proper logic termination. The Si828x has an active low reset input (RSTb), an active high ready (RDY) push pull output, and an open drain fault (FLTb) output that requires a weak 10 k pull-up resistor. The FLTb outputs from multiple Si828x devices can be connected in an OR wiring configuration to provide one single FLTb signal to the MCU. The Si828x gate driver will shut down when a fault is detected. It then provides FLTb indication to the MCU, and remains in the shutdown state until the MCU applies a reset signal. To power the Si828x, the supply for VDDA should be able to handle 10 mA of current and the supplies to VDDB, and VSSB have to be able to handle 20 mA. Each supply should have 0.1 F bypass capacitors to provide large switching transient current. The VSSB supply is optional but it operates better with the CLMP circuit to secure the IGBT in the off state against the collector to gate Miller current. VSSB should be shorted to VMID if VSSB supply is not available. The desaturation sensing circuit consisted of the 100 pF blanking capacitor, 100 current limiting resistor, and DSAT diode. These components provide current and voltage protection for the Si828x desaturation DSAT pin and it is critical to place these components as close to the IGBT as possible. Also, on the layout, make sure that the loop area forming between these components and the IGBT be minimized for optimum desaturation detection. The Si8285 has VH and VL gate drive outputs with external 10 resistors to limit output gate current. The value of these resistors can be adjusted to independently control IGBT collector voltage rise and fall time. The Si8286 only has one VO gate drive output with an external 10 resistor to control IGBT collector voltage rise and fall time. The CLMP output should be connected to the gate of the IGBT directly to provide clamping action between the gate and VSSB. This clamping action dissipates IGBT Miller current from collector to the gate to secure the IGBT in the off-state. 3.1.1 Power To power the Si828x, the supply for VDDA should be able to handle 10 mA of current, the VDDB, and VSSB have to be able to handle the Si828x biasing current plus the average IGBT gate current drive (see 3.3 Power Dissipation Considerations). Each supply should have 0.1 F bypass capacitor to provide large switching transient current in parallel with a 10 F capacitor. The VSSB supply is optional, but it operates better with the CLMP circuit to secure the IGBT in the off state against the collector to gate Miller current. The VSSB pin should be shorted to VMID if VSSB supply is not available. 3.1.2 Inputs The Si828x has both inverting and non-inverting gate control inputs (IN- and IN+). In normal operation, one of the inputs is not used and should be connected to GNDA (IN-) or VDDA (IN+) for proper logic termination. Inputs should be driven by CMOS level push-pull output. If input is driven by the MCU GPIO, it is recommended that the MCU be located as closed to the Si828x as possible to minimize PCB trace parasitic and noise coupling to the input circuit. silabs.com | Building a more connected world. Rev. 1.0 | 11 Si8285/86 Data Sheet Applications Information 3.1.3 Reset, RDY, and Fault The Si828x has an active high ready (RDY) push pull output, an open drain fault (FLTb) output, and an active low reset input (RSTb) that require pull-up resistors. Fast common-mode transients in high-power circuits can inject noise and glitches into these pins due to parasitic coupling. Depending on the IGBT power circuit layout, additional capacitance (100 pF to 470 pF) can be included on these pins to prevent faulty RDY and FLTb indications as well as unintended reset to the device. The FLTb outputs from multiple Si828x devices can be connected in an OR wiring configuration to provide a single FLTb signal to the MCU. The Si828x gate driver will shut down when a fault is detected. It then provides FLTb indication to the MCU and remains in the shutdown state until the MCU applies a reset signal. 3.1.4 Desaturation The desaturation sensing circuit consists of the blanking capacitor (100 pF for Si8286 and 390 pF for Si8285), 100 current limiting resistor, and DSAT diode. These components provide current and voltage protection for the Si828x desaturation DSAT pin, and it is critical to place these components as close to the IGBT as possible. Also, on the layout, make sure that the loop area forming between these components and the IGBT is minimized for optimum desaturation detection. 3.1.5 Driver Outputs The Si8285 has VH and VL gate drive outputs (see Figure 3.1 Recommended Si8285 Application Circuit on page 10). They work with external RH and RL resistors to limit output gate current. The value of these resistors can be adjusted to independently control IGBT collector voltage rise and fall time. The Si8286 only has one VO gate drive output with an external gate resistor to control IGBT collector voltage rise and fall time (see Figure 3.2 Recommended Si8286 Application Circuit on page 10). To achieve independent rise and fall time control, it is suggested to add a pair of fast diodes to the Si8286 VO circuit (see Figure 3.3 Recommended Si8286 Application Circuit with RH and RL on page 11). The CLMP output should be connected to the gate of the IGBT directly to provide clamping action between the gate and VSSB pin. This clamping action dissipates IGBT Miller current from the collector to the gate to secure the IGBT in the off-state. Negative VSSB provides further help to ensure the gate voltage stays below the IGBT's Vth during the off state. 3.2 Layout Considerations It is most important to minimize ringing in the drive path and noise on the supply lines. Care must be taken to minimize parasitic inductance in these paths by locating the Si828x as close as possible to the device it is driving. In addition, the supply and ground trace paths must be kept short. For this reason, the use of power and ground planes is highly recommended. A split ground plane system having separate ground and power planes for power devices and small signal components provides the best overall noise performance. silabs.com | Building a more connected world. Rev. 1.0 | 12 Si8285/86 Data Sheet Applications Information 3.3 Power Dissipation Considerations Proper system design must assure that the Si828x operates within safe thermal limits across the entire load range. The Si828x total power dissipation is the sum of the power dissipated by bias supply current, internal parasitic switching losses, and power dissipated by the series gate resistor and load. Equation 1 shows total Si828x power dissipation. PD = (VDDA)(IDDA) + (VDDB)(IDDB) + f x Qint x VDDB + 1 Rp Rn f Q (VDDB) + 2 ( )( IGBT ) Rp + RH Rn + RL where: PD is the total Si828x device power dissipation (W). IDDA is the input-side maximum bias current (5 mA). IDDB is the driver die maximum bias current (5 mA). Qint is the internal parasitic charge (3 nC). VDDA is the input-side VDD supply voltage (2.7 to 5.5 V). VDDB is the total driver-side supply voltage (VDDB + VSSB: 12.5 to 30 V). f is the IGBT switching frequency (Hz). RH is the VH external gate resistor, RL is the VL external gate resistor. For Si8286, RG works for both RH and RL. RP is the RDS(ON) of the driver pull-up switch: (2.6 ). Rn is the RDS(ON) of the driver pull-down switch: (0.8 ). Equation 1 The maximum power dissipation allowable for the Si828x is a function of the package thermal resistance, ambient temperature, and maximum allowable junction temperature, as shown in Equation 2: PDmax Tjmax - TA ja where: PDmax = Maximum Si828x power dissipation (W). Tjmax = Si828x maximum junction temperature (150 C). TA = Ambient temperature (C) ja = Si828x junction-to-air thermal resistance (60 C/W for four-layer PCB) f = Si828x switching frequency (Hz) Equation 2 Substituting values for PDmax Tjmax (150 C), TA (125 C), and ja (90 C/W) into Equation 2 results in a maximum allowable total power dissipation of 0.42 W. PDmax 150 - 125 = 0.42W 60 Maximum allowable load is found by substituting this limit and the appropriate data sheet values from Table 4.1 into Equation 1 and simplifying. The result is Equation 3. PD = (VDDA)(IDDA) + (VDDB)(IDDB) + f x Qint x VDDB + 1 Rp Rn f Q (VDDB) + 2 ( )( L ) Rp + RH Rn + RL ( )( )(VDDB2) RpRp+ RH + Rn Rn+ RL 1 2.6 0.8 0.42 = (VDDA)(0.005) + (VDDB)(0.004) + f x 3 x 10-9 x VDDB + ( f )(C L )(VDDB 2) + 2 2.6 + 15 0.8 + 10 PD = (VDDA)(IDDA) + (VDDB)(IDDB) + f x Qint x VDDB + 1 f CL 2 0.42 - (VDDA + VDDB)5 x 10-3 - f x 3 x 10-9 x VDDB = 0.111VDDB 2 f (C L silabs.com | Building a more connected world. ) Rev. 1.0 | 13 Si8285/86 Data Sheet Applications Information CL = 0.42 - (VDDA + VDDB )5 x 10-3 0.111 x VDDB 2( f ) - 2.703 x 10-8 VDDB Equation 3 Power dissipation example for Si828x driver using Equation 1 with the following givens: VDDA = 5.0 V VDDB = 18 V f = 30 kHz RH = 10 RL = 15 Ohms QG = 85 nC PD = (5)(0.005) + (15)(0.005) + (2 x 104)(3 x 10-9)(18) + ( )( )( ) 1 2.6 0.8 2 x 104 25 x 10-9 18 + = 100mW 2 2.6 + 10 0.8 + 15 From which the driver junction temperature is calculated using Equation 2, where: Pd is the total Si828x device power dissipation (W) ja is the thermal resistance from junction to air (60 C/W in this example) TA is the maximum ambient temperature (125 C) Tj = Pd x ja + TA Tj = (0.1) x (90) + 125 = 134C Calculate maximum loading capacitance from equation 3: 1. VDDA = 5 V and VDDB = 12.5 V. CL = 1.92 x 10-2 - 2.16 x 10-9 f CL = 8.48 x 10-3 - 1.5 x 10-9 f 2. VDDA = 5 V and VDDB = 18 V. 3. VDDA = 5 V and VDDB = 30 V. CL = 2.45 x 10-3 - 9.01 x 10-10 f Graphs are shown in the following figure. All points along the load lines in these graphs represent the package dissipation-limited value of CL for the corresponding switching frequency. silabs.com | Building a more connected world. Rev. 1.0 | 14 Si8285/86 Data Sheet Applications Information Figure 3.4. Maximum Load vs. Switching Frequency (25 C) silabs.com | Building a more connected world. Rev. 1.0 | 15 Si8285/86 Data Sheet Electrical Specifications 4. Electrical Specifications Table 4.1. Electrical Specifications VDDA = 2.8 V - 5.5 V (See Figure 3.1 for Si8285, Figure 3.2 for Si8286); TA = -40 to +125 C unless otherwise noted. Parameter Symbol Test Condition Min Typ Max Units VDDA 2.8 -- 5.5 V (VDDB - VSSB) 9.5 -- 30 V (VMID - VSSB) 0 -- 15 V IDDA(Q) -- 2.6 3.7 mA -- 5.2 -- mA -- 5.3 6.5 mA -- 3.5 4.5 mA DC Parameters Input Supply Voltage Driver Supply Voltage Input Supply Quiescent Current Input Supply Active Current Output Supply Quiescent Current (Si8285) Output Supply Quiescent Current (Si8286) IDDA f = 10 kHz IDDB(Q) Drive Parameters High Drive Transistor RDS(ON) ROH -- 2.48 -- Low Drive Transistor RDS(ON) ROL -- 0.86 -- High Drive Peak Output Current IOH 2.5 2.8 -- A Low Drive Peak Output Current IOL 3.0 3.4 -- A VH = VDDB - 15 V TPW_IOH < 250 ns VL = VSSB + 6.0 V TPW_IOL< 250 ns UVLO Parameters UVLO Threshold + VDDAUV+ 2.4 2.7 3.0 UVLO Threshold - VDDAUV- 2.3 2.6 2.9 UVLO Lockout Hysteresis- (Input Side) VDDAHYS -- 100 -- mV 8.0 9.0 10.0 V 10.8 12.0 13.2 V 7.0 8.0 9.0 V 9.8 11.0 12.2 V VDDBHYS -- 1 -- V UVLO+ to RDY High Delay tUVLO+ to RDY -- 100 s ULVO- to RDY Low Delay tUVLO- to RDY -- 0.79 s 7.3 V UVLO Threshold + (Driver Side) 9 V Threshold (Si828xBD) VDDBUV+ 12 V Threshold (Si828xCD) UVLO Threshold - (Driver Side) 9 V Threshold (Si828xBD) VDDBUV- 12 V Threshold (Si828xCD) UVLO lockout hysteresis (Driver Side) Desaturation Detector Parameters DESAT Threshold silabs.com | Building a more connected world. VDESAT VDDB - VSSB > VDDBUV+ 6.5 6.9 Rev. 1.0 | 16 Si8285/86 Data Sheet Electrical Specifications Parameter CBl charging current (Si8285) CBl charging current (Si8286) Symbol Test Condition IChg Min Typ Max Units -- 1 -- mA -- 0.25 -- mA DESAT Sense to 90% VOUT Delay tDESAT(90%) -- 220 300 ns DESAT Sense to 10% VOUT Delay tDESAT(10%) 0.77 2.5 2.7 s tDESAT to FLTb -- 220 300 ns tRSTb to FLTb -- 37 45 ns Vt Clamp -- 2.0 -- V Miller Clamp Transistor RDS (ON) RMC -- 1.07 -- Clamp Low Level Sinking Current ICL 3.0 3.4 -- A DESAT Sense to FLTb Low Delay Reset to FLTb High Delay Miller Clamp Parameters (Si8285 Only) Clamp Pin Threshold Voltage VCLMP = VSSB + 6.0 Digital Parameters Logic High Input Threshold VIH 2.0 -- -- V Logic Low Input Threshold VIL -- -- 0.8 V VIHYST -- 440 -- mV Input Hysteresis High Level Output Voltage (RDY pin only) VOH IO = -4 mA VDDA - 0.4 -- -- V Low Level Output Voltage (RDY pin only) VOL IO = 4 mA -- -- 0.4 V -- -- 200 mV VDDA = 5 V, Open-Drain Low Level Output Voltage (FLTb pin only) 5 k pull-up resistor AC Switching Parameters Propagation Delay (Low-to-High) tPLH CL = 200 pF 30 40 50 ns Propagation Delay (High-to-Low) tPHL CL = 200 pF 30 40 50 ns Pulse Width Distortion PWD |tPLH - tPHL| -- 1 5 ns Propagation Delay Difference4 PDD tPHLMAX - tPLHMIN -1 -- 25 ns Rise Time tR CL = 200 pF -- 5.5 15 ns Fall Time tF CL = 200 pF -- 8.5 20 ns Output = low or high (VCM = 1500 V) 35 50 -- kV/s Common Mode Transient Immunity 1. See 1. Ordering Guide for more information. 2. Minimum value of (VDD - GND) decoupling capacitor is 1 F. 3. When performing this test, it is recommended that the DUT be soldered to avoid trace inductances, which may cause overstress conditions. 4. Guaranteed by characterization. silabs.com | Building a more connected world. Rev. 1.0 | 17 Si8285/86 Data Sheet Electrical Specifications VDDA VDDB Si8285/6 VDDA SW1 VDDB IN+ Scope VO IN- SW2 GNDA VSSB VCMTI Probe Figure 4.1. Common-Mode Transient Immunity Characterization Circuit +3.3V 0.1uF H to L V/FAULT 1k GNDA NC VDDA DSAT NC VDDB RSTb VH FLTb VL RDY CLMP IN+ VMID IN- VSSB 8V Strobe 0.1uF 30V 0.1uF 30V 0.1uF Si828x Figure 4.2. Si828x RSTb FLTb CLEAR Test Circuit silabs.com | Building a more connected world. Rev. 1.0 | 18 Si8285/86 Data Sheet Electrical Specifications IN+ VMID IN0.1uF +3.3V 10mA NC VDDA DSAT GNDA VDDB RSTb VDDB FLTb 0.1uF 0.1uF SWEEP 0.1uF 0.1uF VO NC VSSB NC VSSB 15V 15V Si828x Figure 4.3. Si828x DSAT Threshold Test Circuit Table 4.2. Absolute Maximum Ratings1 Parameter Symbol Min Max Unit Storage Temperature TSTG -65 +150 C Operating Temperature TA -40 +125 C Junction Temperature TJ -- +140 C Peak Output Current (tPW = 10 s) IOPK -- 4.0 A Supply Voltage VDD -0.5 36 V Output Voltage VOUT -0.5 36 V Input Power Dissipation PI -- 100 mW Output Power Dissipation PO -- 800 mW Total Power Dissipation (All Packages Limited by Thermal Derating Curve) PT -- 900 mW Lead Solder Temperature (10 s) -- 260 C HBM Rating ESD 4 -- kV CDM 1600 -- V Maximum Isolation (Input to Output) (1 sec) WB SOIC-16 -- 6500 VRMS Note: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. silabs.com | Building a more connected world. Rev. 1.0 | 19 Si8285/86 Data Sheet Electrical Specifications 4.1 Timing Diagrams UVLO Threshold + UVLO Threshold - VDDB - VMID tUVLO- to RDY tUVLO+ to RDY VDDA RDY GNDA Figure 4.4. UVLO Condition to RDY Output VDESAT DSAT tFLTb FLTb tDSAT to SS VH VSSB + 2 V VL tRSTb-FLTb RSTb Figure 4.5. Device Reaction to Desaturation Event silabs.com | Building a more connected world. Rev. 1.0 | 20 Si8285/86 Data Sheet Electrical Specifications 4.2 Typical Operating Characteristics silabs.com | Building a more connected world. Rev. 1.0 | 21 Si8285/86 Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.0 | 22 Si8285/86 Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.0 | 23 Si8285/86 Data Sheet Electrical Specifications 4.3 Regulatory Information Table 4.3. Regulatory Information (Pending)1, 2 CSA The Si828x is certified under CSA Component Acceptance Notice 5A. For more details, see Master Contract Number 232873. 60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. VDE The Si828x is certified according to VDE0884. For more details, see File 5006301-4880-0001. VDE 0884-10: Up to 1414 Vpeak for basic insulation working voltage. UL The Si828x is certified under UL1577 component recognition program. For more details, see File E257455. Rated up to 5000 VRMS isolation voltage for basic protection. CQC The Si828x is certified under GB4943.1-2011. Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. Note: 1. Regulatory Certifications apply to 3.75 and 5.0 kVRMS rated devices, which are production tested to 4.5 and 6.0 kVRMS for 1 sec, respectively. 2. For more information, see 1. Ordering Guide. Table 4.4. Insulation and Safety-Related Specifications Parameter Symbol Test Condition Value Unit WB SOIC-16 Nominal External Air Gap (Clearance)1 CLR 8.0 mm Nominal External Tracking (Creepage) CPG 8.0 mm Minimum Internal Gap (Internal Clearance) DTI 0.016 mm Tracking Resistance PTI or CTI 600 V Erosion Depth ED 0.019 mm Resistance (Input-Output)2 RIO 1012 Capacitance (Input-Output)2 CIO 1 pF IEC60112 f = 1 MHz Note: 1. The values in this table correspond to the nominal creepage and clearance values as detailed in PACKAGE OUTLINE: 16-PIN WIDE BODY SOIC. VDE certifies the clearance and creepage limits as 8.5 mm minimum for the WB SOIC-16. UL does not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance and creepage limits as 7.6 mm minimum for the WB SOIC package. 2. To determine resistance and capacitance, the Si828x is converted into a 2-terminal device. Pins 1-8 are shorted together to form the first terminal, and pins 9-16 are shorted together to form the second terminal. The parameters are then measured between these two terminals. silabs.com | Building a more connected world. Rev. 1.0 | 24 Si8285/86 Data Sheet Electrical Specifications Table 4.5. IEC 60664-1 Ratings Parameter Test Condition Specification WB SOIC-16 Basic Isolation Group Material Group I Installation Classification Rated Mains Voltages 150 VRMS I-IV Rated Mains Voltages 300 VRMS I-IV Rated Mains Voltages 600 VRMS I-IV Table 4.6. VDE0884-10 Insulation Characteristics1 Parameter Symbol Test Condition Characteristic Unit WB SOIC Maximum Working Insulation Voltage VIORM 1414 V peak Input to Output Test Voltage VPR Method b1 (VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC) 2652 V peak Transient Overvoltage VIOTM t = 60 sec 8000 V peak Surge Voltage VIOSM Tested per IEC 60065 with surge voltage of 1.2 s/50 s 3077 V peak Tested with 4000 V Pollution Degree (DIN VDE 0110) Insulation Resistance at TS, VIO = 500 V 2 RS >109 Note: 1. Maintenance of the safety data is ensured by protective circuits. The Si828x provides a climate classification of 40/125/21. Table 4.7. IEC Safety Limiting Values1, 2 Parameter Symbol Test Condition Max Unit WB SOIC-16 Safety Temperature TS Safety Current IS JA = 60 C/W 150 C 36 mA 1.1 W VDDA = 5.5 V, VDDB-VSSB = 30 V TJ = 150 C, TA = 25 C Device Power Dissipation PS Note: 1. Maximum value allowed in the event of a failure. 2. The Si828x is tested with RH = RL = 0 , CL = 5 nF, and a 200 kHz, 50% duty cycle square wave input. 3. See Figure 4.6 for Thermal Derating Curve. silabs.com | Building a more connected world. Rev. 1.0 | 25 Si8285/86 Data Sheet Electrical Specifications Table 4.8. Thermal Characteristics Parameter Symbol Typ Unit WB SOIC-16 IC Junction-to-Air Thermal Resistance JA 60 C/W Figure 4.6. WB SOIC-16 Thermal Derating Curve silabs.com | Building a more connected world. Rev. 1.0 | 26 Si8285/86 Data Sheet Pin Descriptions 5. Pin Descriptions GNDA NC IN+ VMID VDDA DSAT IN _ NC NC VDDB VDDA VH GNDA VL RSTb RDY CLMP FLTb IN+ VMID NC VSSB VSSB NC VSSB RSTb FLTb IN Si8285 _ DSAT Si8286 VDDB VDDB VO Table 5.1. Si8285/86 Pin Descriptions Name Si8285 Pin # Si8286 Pin # Description GNDA 1 4 Input side ground VDDA 2 3 Input side power supply RSTb 4 5 Reset fault condition pin FLTb 5 6 Driver fault condition signal RDY 6 -- UVLO ready signal IN+ 7 1 Driver control complementary input (+) IN- 8 2 Driver control complementary input (-) VSSB 9 9, 10 Driver output side ground VMID 10 16 IGBT source reference CLMP 11 -- Miller clamp drain VL 12 -- Pull-low driver output VH 13 -- Pull-high driver output VO -- 11 Driver output VDDB 14 12, 13 Driver output power supply DSAT 15 14 Desaturation detection sensor input NC1 16 7, 8, 15 No Connect Note: 1. No Connect. These pins may be internally connected. To maximize CMTI performance, these pins should be connected to the ground plane. silabs.com | Building a more connected world. Rev. 1.0 | 27 Si8285/86 Data Sheet Packaging 6. Packaging 6.1 Package Outline: 16-Pin Wide Body SOIC The figure below illustrates the package details for the Si828x in a 16-Pin Wide Body SOIC. The table lists the values for the dimensions shown in the illustration. Figure 6.1. 16-Pin Wide Body SOIC Symbol Millimeters Min Max A -- 2.65 A1 0.10 0.30 A2 2.05 -- b 0.31 0.51 c 0.20 0.33 D 10.30 BSC E 10.30 BSC E1 7.50 BSC e 1.27 BSC L 0.40 1.27 h 0.25 0.75 0 8 aaa -- 0.10 bbb -- 0.33 silabs.com | Building a more connected world. Rev. 1.0 | 28 Si8285/86 Data Sheet Packaging Symbol Millimeters Min Max ccc -- 0.10 ddd -- 0.25 eee -- 0.10 fff -- 0.20 Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Outline MS-013, Variation AA. 4. Recommended reflow profile per JEDEC J-STD-020C specification for small body, lead-free components. silabs.com | Building a more connected world. Rev. 1.0 | 29 Si8285/86 Data Sheet Packaging 6.2 Land Pattern: 16-Pin Wide Body SOIC The figure below illustrates the recommended land pattern details for the Si828x in a 16-Pin Wide Body SOIC. The table lists the values for the dimensions shown in the illustration. Figure 6.2. PCB Land Pattern: 16-Pin Wide Body SOIC Table 6.1. 16-Pin Wide Body SOIC Land Pattern Dimensions1, 2 Dimension Feature (mm) C1 Pad Column Spacing 9.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.90 Note: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC), and a card fabrication tolerance of 0.05 mm is assumed. silabs.com | Building a more connected world. Rev. 1.0 | 30 Si8285/86 Data Sheet Packaging 6.3 Top Marking: 16-Pin Wide Body SOIC Si828xUV YYWWRTTTTT e4 TW Si8285/86 Top Marking Table 6.2. Si8285/86 Top Marking Explanation Line 1 Marking: Customer Part Number Si8285, Si8286 = Product Configuration U = UVLO level B = 9 V; C = 12 V V = Isolation rating C = 3.75 kV D = 5.0 kV Line 2 Marking: YY = Year WW = Workweek RTTTTT = Mfg Code Assigned by the assembly house. Corresponds to the year and workweek of the mold date. Manufacturing code from the Assembly Purchase Order form "R" indicates revision silabs.com | Building a more connected world. Rev. 1.0 | 31 Si8285/86 Data Sheet Revision History 7. Revision History 7.1 Revision 0.6 November, 2016 * Corrected junction temperature in Table 4.2 Absolute Maximum Ratings1 on page 19. 7.2 Revision 1.0 March, 2018 * Updated Safety Regulatory Approvals section on page 1, and Tables 4.3, 4.4, and 4.6 to conform with isolation component standard terminology. * Removed references to IEC 60747-5-5 throughout the document and replaced with VDE 0884. * Added automotive (-A) OPNs. * Updated Thermal Derating Curve, Figure 4.6. silabs.com | Building a more connected world. Rev. 1.0 | 32 Smart. Connected. Energy-Friendly. Products Quality www.silabs.com/products www.silabs.com/quality Support and Community community.silabs.com Disclaimer Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of Silicon Labs. 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