IMAGE SENSOR InGaAs linear image sensor G8050 to G8053 series Image sensor for DWDM wavelength monitor G8050 to G8053 series InGaAs linear image sensors are specifically designed as detectors for monitoring WDM in optical communications. These linear image sensors consist of an InGaAs photodiode array with each pixel connected to a charge amplifier array comprised of CMOS transistors, a CDS circuit, an offset compensation circuit, a shift register and a timing generator. These sensors deliver high sensitivity and stable operation in the near infrared spectral range. The package is hermetically sealed for high reliability and the window has an anti-reflective coating for efficient light detection. Signal processing circuits on the CMOS chip allow selecting a feedback capacitance (Cf) of 10 pF or 0.5 pF by supplying an external voltage. The image sensor operates over a wide dynamic range when Cf=10 pF and delivers high gain when Cf=0.5 pF. Features Applications l DWDM wavelength monitor l Optical spectrum analyzer l Wide dynamic range l Low noise and low dark current l Selectable gain l Anti-saturation circuit l CDS circuit *1 l Offset compensation circuit l Simple operation (by built-in timing generator) *2 l High resolution: 25 m pitch (512 ch) l Low cross-talk l 256 ch: 1 video line 512 ch: 2 video lines S e le c tio n g u id e Typ e N o . C o o ling G 8 0 5 0- 2 5 6 R G 8 0 5 0- 2 5 6 S G 8 0 5 1- 5 1 2 R G 8 0 5 1- 5 1 2 S G 8 0 5 2- 2 5 6 D * 3 G 8 0 5 2- 2 5 6 R G 8 0 5 2- 2 5 6 S G 8 0 5 3- 5 1 2 D * 3 G 8 0 5 3- 5 1 2 R G 8 0 5 3- 5 1 2 S N o n -c oo led O n e -s tag e T E -c o ole d N o n -c oo led O n e -s tag e T E -c o ole d N o n -c oo led Num ber of p ixe ls P ixe l p itc h ( m ) P ixe l s ize [ m (H ) x m (V )] 256 50 5 0 x 25 0 512 25 2 5 x 25 0 256 50 5 0 x 50 0 O n e -s tag e T E -c o ole d N o n -c oo led S p e c tra l res p on se ra ng e ( m ) 0 .9 to 1 .7 (2 5 C ) 0 .9 to 1 .67 (-1 0 C ) 0 .9 to 1 .7 (2 5 C ) 0 .9 to 1 .67 (-1 0 C ) D e fe c tive p ixe l 0 .9 to 1 .7 (2 5 C ) 0 0 .9 to 1 .67 (-1 0 C ) 512 25 0 .9 to 1 .7 (2 5 C ) 2 5 x 50 0 O n e -s tag e T E -c o ole d 0 .9 to 1 .67 (-1 0 C ) Spectral response (Typ.) 1.0 T=25 C T= -10 C PHOTO SENSITIVITY (A/W) *1: CDS (Correlated Double Sampling) circuit A major source of noise in charge amplifiers is the reset noise generated when the integration capacitance is reset. A CDS circuit greatly reduces this reset noise by holding the signal immediately after reset to find the noise differential. *2: Timing generator Different signal timings must be properly set in order to operate a shift register. In conventional image sensor operation, external PLDs (Programmable Logic Devices) are used to input the required timing signals. However, G8050 to G8053 series image sensors internally generate all timing signals on the CMOS chip just by supplying CLK and RESET pulses. This makes it simple to set the timings. *3: For G8052-256D and G8053-512D specifications, see the separate data sheets available from Hamamatsu. 0.5 0 0.5 1.0 1.5 WAVELENGTH (m) 2.0 KMIRB0011EA 1 InGaAs linear image sensor G8050 to G8053 series Absolute maximum ratings Parameter Clock pulse voltage Operating temperature *1 Storage temperature *1 *1: Non condensation Symbol V Topr Tstg Value 5.5 -40 to +70 -40 to +85 Unit V C C Electrical characteristics (Ta=25 C, V=5 V ) Parameter Symbol Vdd Vref Vss INP f Supply voltage Ground Element bias Clock frequency Clock pulse voltage high low V tr tf tpw Clock pulse rise/fall times Clock pulse width Reset pulse voltage high low Reset pulse rise/fall times Reset pulse width Video output voltage Data rate high low V (RES) tr (RES) tf (RES) tpw (RES) VH VL fV Min. 4.9 3.5 0.1 V - 0.5 0 Typ. 5.0 1.26 0 4.5 V 0 Max. 5.1 4.6 4 V + 0.5 0.4 Unit V V MHz V V 0 20 100 ns 200 V - 0.5 0 V 0 V + 0.5 0.4 ns V V 0 20 100 ns 6000 Vref - 4.4 1.26 f/8 INP - ns V V Hz Electrical and optical characteristics General ratings (T=25 C) Parameter Symbol Min. Typ. Max. Peak sensitivity wavelength 1.55 p Saturation charge *2 Qsat 30 Photo response non-uniformity *3 PRNU 5 *2: V=5 V, Cf=10 pF *3: 50 % of saturation, 10 ms integration time, after dark output subtraction, excluding first and last pixels. Unit m pC % Dark current characteristics (T=25 C) Parameter G8050 series G8051 series G8052 series G8053 series 2 Symbol ID Min. - Typ. 2 1.5 4 6 Max. 20 15 40 60 Unit pA InGaAs linear image sensor G8050 to G8053 series Equivalent circuit q ( ) 1 PIXEL Cf=10 pF Cf=0.5 pF SHIFT REGISTER OFFSET COMPENSATION CDS VIDEO PHOTODIODE AD-TRIG TIMING GENERATOR Vdd INP Vss CLK RESET Vref EXTERNAL INPUT KMIRC0010EB Timing chart CLK (INPUT) RESET (INPUT) INTEGRATION 2 CLOCKS TIME 8 CLOCKS 8 CLOCKS 8 x N CLOCKS (READOUT TIME) TRIGGER (OUTPUT) VIDEO (OUTPUT) 1 ch (n-1) ch 2 ch Basic circuit connection n ch KMIRC0011EA CLK RESET BUFFER Vref VIDEO Vdd Cf SELECT INP AD-TRIG Vss BUFFER KMIRC0012EA 3 InGaAs linear image sensor G8050 to G8053 series Dimensional outline (unit: mm) 63.5 0.15 53.3 0.15 38.1 0.15 35.6 0.15 15 3.0 0.15 27.2 0.15 20.3 0.15 10.2 0.15 22.9 0.15 25.4 0.15 28 1 2 14 A NON-COOLED 6.4 1 1.0 0.2 B A INDEX MARK B 4.35 1.8 ONE-STAGE TE-COOLED 6.15 3.6 (28 x) 2.54 (28 x) 0.46 KMIRA0010EA Pin connection (top view) 256 PIXELS TE + THERM THERM CASE 512 PIXELS Cf SELECT RESET TE AD-TRIG Vdd Vss INP CLK RESET-EVEN TE + AD-TRIG-EVEN THERM THERM CASE CLK-EVEN Vref VIDEO Cf SELECT RESET-ODD TE AD-TRIG-ODD Vdd Vss INP CLK-ODD Vref VIDEO-EVEN VIDEO-ODD KMIRC0013EA Terminal name CLK RESET Input/Output Function and recommended connection Input Clock pulse for operating the CMOS shift register (CMOS logic compatible) Input Reset pulse for initializing the feedback capacitance in the charge amplifier (CMOS logic compatible) formed on the CMOS chip. The width of the reset pulse is integration time. Vdd Input Vss - Supply voltage for operating the signal processing circuit on the CMOS chip. INP Input Cf SELECT Input CASE - THERM - TE+, TE- - AD-TRIG Output Reset voltage for the charge amplifier array on the CMOS chip. Voltage that determines the feedback capacitance (Cf) on the CMOS chip. Cf=10 pF at 0 V, and Cf=0.5 pF at 5 V. This terminal is electrically connected to the package. Thermistor for monitoring temperature inside the package. No connection for room temperature operation type. Power supply terminal for the thermoelectric cooler that cools the photodiode array. No connection for room temperature operation type. Digital signal for AD conversion; positive polarity VIDEO Output Analog video signal; positive polarity Vref Input Ground for the signal processing circuit on the CMOS chip. Reset voltage for the offset compensation circuit on the CMOS chip Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions. Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. (c)2002 Hamamatsu Photonics K.K. HAMAMATSU PHOTONICS K.K., Solid State Division 1126-1 Ichino-cho, Hamamatsu City, 435-8558 Japan, Telephone: (81) 053-434-3311, Fax: (81) 053-434-5184, http://www.hamamatsu.com U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218 Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658 France: Hamamatsu Photonics France S.A.R.L.: 8, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10 United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777 North Europe: Hamamatsu Photonics Norden AB: Smidesvagen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01 Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741 4 Cat. No. KMIR1009E04 Feb. 2002 DN