DEMO MANUAL DC2405A LTM2893 Isolated 100MHz ADC Serial Interface and LTC2328-18 DESCRIPTION Demonstration circuit 2405A shows an LTM(R)2893 isolating and interfacing an LTC(R)2328-18. The LTM2893 is a high speed SPI isolator for interfacing read only ADCs with a full complement of control signals. The LTC2328-18 is a low noise, high speed 18-bit successive approximation register (SAR) ADC. Low noise isolated power is delivered to the isolated side with an LT3999 push-pull driver and isolation transformer. at a maximum 100MHz SCK frequency. The LTM2893 is compatible with many ADCs with SPI clock frequencies up to 100MHz. The DC2405A demonstrates the DC and AC operation of the LTC2328-18 without performance degradation with the LTM2893. The Serial Peripheral Interface (SPI) runs Design files for this circuit board are available at http://www.linear.com/demo/DC2405A PERFORMANCE SUMMARY The DC2405A connects to either the DC890 for measurements with PScopeTM, or DC590 for measurements with QuikEvalTM, or DC2026 for measurements with QuikEval and a DC590 sketch or single sample measurements with an example sketch. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope and QuikEval are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Specifications are at TA = 25C PARAMETER CONDITIONS MIN Input Supply Range VCC - GND 4.75 TYP Analog Signal Input Range (AIN) Clock Frequency (CLK IN) 10 DC590 Interface Voltage Supply 3.0 3.3 MAX UNITS 5.25 V 10.24 V 100 MHz 3.6 V dc2405af 1 DEMO MANUAL DC2405A DC2405A CONNECTION DIAGRAM 100MHz CLK IN 5V GND DC890 ANALOG INPUT Figure 1. DC2405A Setup DC2405A JUMPERS DEFINITIONS JP1 - GND2, Isolated ground connection JP2 - VCC, 5V Power supply input connection JP3 - GND, Power supply return connection JP4 - CFG, Default 0, when CFG = 1 a secondary image in U10 is selected, currently not implemented. 2 JP5 - OE, Output enable for U10, default ON. When OE is ON, U10 drives the signals to U1 (for use with the DC890, DC590, and DC2026). When OE is OFF the signals to U1 are high impedance from U10 and the interface signals can be driven externally. JP6 - JTAG, header for factory use only JP7 - EEPROM, is for factory use only, default WP. dc2405af DEMO MANUAL DC2405A DC890 QUICK START PROCEDURE Check to make sure that all switches and jumpers are set to their default settings as described in the DC2405A Jumpers section and Figure 1 of this manual. The demo board is designed to use the onboard isolated power supply to generate all the required bias voltages. The analog input is DC coupled. 1.Connect the DC2405A to a DC890 USB High Speed Data Collection Board using the edge connector J4. 2.Connect the DC890 to a host PC with a standard USB A/B cable. 3.Apply +5V and ground to the VCC and GND terminals. 4.Apply a low jitter signal source to J1. Observe the recommended input voltage range for the analog input. 5. Connect a low jitter 100MHz 2.5VP-P sine wave or square wave to connector J2. Note that J2 has a 50 termination resistor to ground. Alternatively, a DC1216A 100MHz fixed frequency clock source board can be used. 6.Run the PScope software (Pscope.exe version K83 or later), which can be downloaded from www.linear.com/ designtools/software. The PScope software should recognize the DC2405A and configure itself automatically. 7. Click the Collect button (see Figure 2) to begin acquiring data. The Collect button then changes to Pause, which can be clicked to stop data acquisition. Complete PScope software documentation is available from the Help menu. Updates can be downloaded from the Tools menu. Check for updates periodically as new features may be added. Figure 2. PScope Display Capturing 2kHz Input Tone dc2405af 3 DEMO MANUAL DC2405A DC590/DC2026 QUICK START PROCEDURE IMPORTANT! To avoid damage to the DC2405A, make sure that VCCIO (JP6 of the DC590, JP3 of the DC2026) of the DC590/DC2026 is set to 3.3V before connecting the DC590/DC2026 to the DC2405A. 3.Connect the DC2405A to a DC590/DC2026 USB serial controller using the supplied 14-conductor ribbon cable. 1.To use the DC590/DC2026 with the DC2405A, it is necessary to apply 5V and ground to the VCC and GND terminals of the DC2405A. 5.Run the QuikEval software (QuikEval.exe version K107 or later), which is available from www.linear.com/ designtools/software. The correct control panel will be loaded automatically. 2. Connect the DC590/DC2026 to a host PC with a standard USB A/B cable. 4. Apply a signal source to J1. A clock source on J2 is not necessary. 6.Click the COLLECT button (Figure 3) to begin reading the ADC. Figure 3. QuikEval Screenshot Captured with a 50 Terminator on AIN 4 dc2405af DEMO MANUAL DC2405A DC2405A SETUP DC POWER The DC2405A requires +5VDC and draws ~265mA. This current is split between the isolated side and the logic side. The isolated side current consumption is through the DC/ DC power converter supplying the LT1468, input buffer, LTC2328-18 ADC, and the isolated side of the LTM2893. The logic side current supplies the FPGA, clock input path, and the LTM2893. CLOCK SOURCE You must provide a low jitter 2.5VP-P sine or square wave to the clock input J2 for data collection with the DC890. The clock input is AC-coupled so the DC level of the clock signal is not important. A generator, such as the Rohde & Schwarz SMB100A high speed clock source, is recommended to drive the clock input. Drive J2 with a 100MHz clock frequency. The ratio between the clock source and the sampling frequency is 100:1. A 100MHz clock source results in a 1Msps sampling rate. DATA OUTPUT If not connected to a DC890, parallel data output from this board (0V to 2.5V by default), can be acquired by a logic analyzer, and subsequently imported into a spreadsheet, or mathematical package depending on what form of digital signal processing is desired. Alternatively, the data can be fed directly into an application circuit. Use pin 50 of J4, edge connector, to latch the data. The data should be latched using the negative edge of this signal. ANALOG INPUTS The DC2405A analog input AIN is a single-ended input referenced to GND2. AIN has a high input impedance buffer (LT1468) before the LTC2328-18 ADC. The default setup for the DC2405A requires that AIN be driven with a low noise, low distortion generator for SINAD, THD, or SNR testing. Use an analog source such as the Stanford Research DS360 or SR1. Synchronize the clock source to the analog source through an external reference input to generate SNR and SINAD results similar to Figure 2 without windowing. LTM2893 DIGITAL INTERFACE The demo board has an unpopulated header placeholder in-between U10 and U1. All interface signals between the FPGA (U10) and the logic interface of the LTM2893 (U1) are exposed. An external interface may be connected to this header location by setting the OE jumper JP5 off. When JP5 is low, all signals to the LTM2893 will be high impedance from the FPGA. The header placeholder pin pitch is on 0.100-inch centers. dc2405af 5 DEMO MANUAL DC2405A DC2405A DATA COLLECTION This demo board is tested in-house by attempting to duplicate the FFT plot shown in Figure 2. This involves a 100MHz clock source synchronized with a reference clock to an SR1 sinusoidal generator. The SR1 sinusoidal generator is set at a frequency of 2.01416kHz. The input signal level is approximately -1dBFS. A typical FFT obtained with DC2405A is shown in Figure 2. Note that to calculate the real SNR, the signal level (F1 amplitude = -1.006dB) has to be added back to the SNR that PScope displays. With the example shown in Figure 2, this means that the actual SNR would be 94.76dB instead of the 93.76dB that PScope displays. There are a number of scenarios that can produce misleading results when evaluating an ADC. One that is common 6 is feeding the converter with an input frequency that is a sub-multiple of the sample rate and will only exercise a small subset of the possible output codes. The proper method is to pick an M/N frequency for the input sine wave frequency. N is the number of samples in the FFT. M is a prime number between one and N/2. Multiply M/N by the sample rate to obtain the input sine wave frequency. Another scenario that can yield poor results is if you do not have a signal generator capable of ppm frequency accuracy or if it cannot be locked to the clock frequency. You can use an FFT with windowing to reduce the "leakage" or spreading of the fundamental, to get a close approximation of the ADC performance. If an amplifier or clock source with poor phase noise is used, the windowing will not improve the SNR. dc2405af DEMO MANUAL DC2405A DC590/DC2026 DATA COLLECTION Due to the relatively low and somewhat unpredictable sample rate of the DC590/DC2026, its usefulness is limited to noise measurement and data collection of slowly moving signals. To observe measurements from QuikEval, use a DC590 or program a DC2026 with a DC590 sketch from an Arduino IDE. Then launch QuikEval, a typical data capture and histogram are shown in Figure 3. To observe measurements and see example code for reading and configuring the LTM2893 from the DC2026, run an Arduino IDE and select File > Sketchbook > Part Number > 2000 > 2800 > 2893 >DC2405A. Upload the program to the DC2026 and launch the Serial Monitor from the tools menu. A brief menu will display on the serial monitor output. Selecting 1 and sending to the DC2026 will result in a single conversion and the result will be displayed in the Serial Monitor window. dc2405af 7 DEMO MANUAL DC2405A PARTS LIST ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER CAPACITOR, CERAMIC, 3.3nF 5% 1206 250V NPO TDK/C3216C0G2E332J085AA 40 C2, C8, C15, C17, C18, C20, CAPACITOR, CERAMIC, 100nF 10% 0402 50V X7R C23-C28, C34, C45-46, C48-71, C73 TDK/C1005X7R1H104K050BB 9 C3, C7, C10-13, C43, C47, C72 CAPACITOR, CERAMIC, 1F 10% 0603 35V X7R TDK/C1608X7R1V105K080AC TDK/C3216X7R1V106K160AC 1 1 C1 2 3 4 4 C4-5, C29, C36 CAPACITOR, CERAMIC, 10F 10% 1206 35V X7R 5 0 C6, C9 OPTIONAL 6 1 C14 CAPACITOR, CERAMIC, 47F 20% 1210 6.3V X7S TDK/C3225X7S0J476M250AC 7 1 C16 CAPACITOR, CERAMIC, 2.2F 10% 0603 10V X7R TDK/C1608X7R1A225K080AC 8 4 C19, C38, C40, C44 CAPACITOR, CERAMIC, 10F 10% 0805 16V X6S TDK/C2012X6S1C106K085AC 2 C21-22 CAPACITOR, CERAMIC, 150pF 10% 1808 250V X7R MURATA/GA342QR7GF151KW01L 9 7 C30-32, C35, C37, C39, C41 CAPACITOR, CERAMIC, 10nF 10% 0402 50V X7R TDK/C1005X7R1H103K050BB 10 1 C33 CAPACITOR, CERAMIC, 1F 10% 1206 100V X7R TDK/C3216X7R2A105K160AA 11 1 C42 CAPACITOR, TANTALUM, 47F 10% 2413 16V KEMET/T494C476K016AT 12 2 D1-2 DIODE, ARRAY, 75V 215mA SOT363 DIODES INC/BAV99DW-7-F 13 2 J1-2 CONNECTOR, BNC JACK, EDGE MOUNT TE CONNECTIVITY/1274727-1 14 1 J3 HEADER, 2 x 7 2mm SHROUDED MOLEX/87831-1420 15 3 JP1-3 HEADER, LOOP 1 x 2, 0.2mm AAVID/125700D00000G 16 3 JP4-5, JP7 HEADER, 1 x 3, 2mm WURTH/62000311121 17 3 JP4-5, JP7 SHUNT, 1 x 2, 2mm WURTH/60800213421 18 1 JP6 HEADER, 2 x5, 0.1mm WURTH/61301021121 19 2 L1-2 INDUCTOR, COUPLED, 22H 3 x 3mm 1.9 0.44A COILCRAFT/LPD3015-223MRB 20 6 MH1-6 STANDOFF, NYLON 0.25" KEYSTONE, 8831 (SNAP ON) VISHAY/CRCW06030000Z0EA 21 2 R3-4 RESISTOR, 0 1% 0603 22 1 R2 OPTIONAL 23 3 R9-10, R35 RESISTOR, 1k 1% 0603 VISHAY/CRCW06031K00FKEA 24 4 R7-8, R12, R25 RESISTOR, 33 1% 0402 VISHAY/CRCW040233R0FKED 25 1 R11 RESISTOR, 49.9 1% 1206 VISHAY/CRCW120649R9FKEA 26 1 R6 RESISTOR, 28k 1% 0603 VISHAY/CRCW060328K0FKEA 27 1 R5 RESISTOR, 49.9k 1% 0603 VISHAY/CRCW060349K9FKEA 28 7 R13, R16, R22, R36-38, R40 RESISTOR, 4.99k 1% 0603 VISHAY/CRCW06034K99FKEA 29 14 R14-15, R17-21, R24, R26, R28, R31-33, R34 RESISTOR, 10k 1% 0402 VISHAY/CRCW040210K0FKED 30 2 R1, R23 RESISTOR, 100k 1% 0603 VISHAY/CRCW0603100RFKEA 31 3 R27, R29-30 RESISTOR, 100k 1% 0402 VISHAY/CRCW0402100KFKED 32 1 R39 RESISTOR, 2k 1% 0603 VISHAY/CRCW06032K00FKEA 33 11 RA1-11 RESISTOR ARRAY, 33k 4 RES 1206 PANASONIC/EXB-38V330JV 34 1 TR1 TRANSFORMER, 5kV 2:1 WURTH/750313626 35 1 U1 IC, 100MHz ADC-SPI ISOLATOR LINEAR TECH/LTM2893CY#PBF 36 1 U2 IC, OPAMP LINEAR TECH/LT1468CS8#PBF 37 1 U3 IC, ADC, 1MSPS, 18-BIT, BIPOLAR, 10.24V LINEAR TECH/LTC2328CMS-18#PBF 38 1 U4 IC, PUSH-PULL DC/DC DRIVER, 1A, 1MHz LINEAR TECH/LT3999EMSE#PBF 8 dc2405af DEMO MANUAL DC2405A PARTS LIST ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER 39 1 U5 IC, BUS SWITCH, SPST, SC70-5 FAIRCHILD SEMI/NC7SZ66P5X 40 1 U6 IC, INVERTER, SC70-5 FAIRCHILD SEMI/NC7SZ04P5X 41 1 U7 IC, D-TYPE POS TRG, MSOP8 ON SEMI/NL17SZ74USG 42 2 U8-9 IC, UNBUFFERED INVERTER, SC70-5 FAIRCHILD SEMI/NC7SVU04P5X 43 1 U10 IC, FPGA/CPLD 130 I/O 169UBGA ALTERA/10M08SAU169C8GES 44 2 U11-12 IC, LDO, 15V, 100mA LINEAR TECH/LT3060ETS8-15#PBF 45 2 U13-14 IC, LDO, 5V, 100mA LINEAR TECH/LT1761ES5-5#PBF 46 1 U15 IC, LDO, 3.3V, 500mA LINEAR TECH/LT1763CDE-3.3#PBF 47 1 U16 IC, BUFFER, TRI-STATE, QUAD, 14TSSOP NXP/74LVT126PW,118 48 2 U17-18 IC, BUS TRANSCEIVER, TRI-STATE, SOT-563 TI/SN74LVC1T45DRLR U19 IC, EEPROM, 2-KBIT, I2C, 8TSSOP MICROCHIP/24LC024-I/ST 49 1 dc2405af 9 10 9 8 7 6 5 4 3 2 A AIN +/- 10.24V GND2 5VD 10uF C38 10uF C40 JP1 J1 5VA 5VD 5VA R1 100 10nF C39 10nF C37 3.3nF NPO C1 B -15V 2 OUT IN BYP SHDN GND U14 LT1761-5 2 IN OUT BYP SHDN GND U13 LT1761-5 OPT R2 5 4 5 4 OPT C6 1uF 100nF C3 C2 2 3 100nF 1uF C8 C7 1uF C33 1 3 1 3 15V 100nF C34 0 R3 C -15V 6 U2 LT1468 15V 10uF 35V C29 10uF 35V C36 R4 0 10nF C30 10nF C35 10nF C31 5 6 7 8 10nF C32 5 6 7 8 C9 OPT 5 4 D IN- IN+ 100nF C15 LT3060-15 GND IN GND OUT ADJ GND REF/BYP SHDN U11 LT3060-15 GND IN OUT GND ADJ GND REF/BYP SHDN U12 5VA 2 1 4 3 2 1 4 3 2 1 15 14 10 12 13 11 9 N1 N2 N3 N4 N5 N6 P1 P2 P3 P4 P5 P6 R1 R2 R3 R4 R5 R6 1uF 1uF C10 C11 1uF 1uF C12 C13 F E 1. INSTALL SHUNTS AS SHOWN. F 4 5 6 ISOLATION BARRIER 150pF C21 GND2 LTM2893CY VCC2 GND2 GND2 SA2 SB2 SC2 VL2 MISOA2 MISOB2 VL2 GND2 BUSYS ON2 SS2 MOSI2 SCK2 BUSY2 CNV2 U1 NOTE: UNLESS OTHERWISE SPECIFIED 2.2uF C16 LTC2328-18 OVDD SDO CHAIN RDL/SDI SCK BUSY CNV 100nF 100nF D1:A D1:B BAV99DW C18 U3 L1 22uH D2:A D2:B BAV99DW 47uF C17 C14 10uF 35V C4 10uF 35V C5 L2 22uH 5VD +VI -VI E 5VD D 3 2 1 150pF C22 GND VCC GND GND SA SB SC VL MISOA MISOB CSC GND FAULT ON SS MOSI SCK BUSY CNV TR1 C20 100nF 10uF 100nF 100nF C19 C25 C27 GND CUSTOMER NOTICE 4.99k R13 CS SDI SCK BUSY FAULT SDOA SDOB CSC SA SB SC R6 28k 3V3 LT3999 11 G H THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. 2 4.99k R16 100nF 100nF 10/11 8 3V3 1uF C43 C26 C28 U4 49.9k R5 100nF C23 H LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMERS RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. C1 C2 C3 C4 C5 C6 B1 B2 B3 B4 B5 B6 A1 A2 A3 A4 A5 A6 G 3V3 1 2 3 4 5 SWA RBIAS VIN UVLO OVLO/DC SWB ILIM/SS SYNC RT RDC 10 9 8 7 6 CSC SOB SOA SC SB SA CNV BSY SCK SDI CS FLT 15V -15V 5 7 1 4 CNV I KWB KWB CLK 3 5 6 Q Q 33 R25 U7 NL17SZ74 BYP R7 OUT SEN IN SHDN 2/3 5 2 - C42 47uF 2413 REV ECO U15 LT1763-3.3 I 1 33 U5 NC7SZ66P5X 4 GND GND 13 7 C CNV2 BSY2 SCK2 SDO2 7 4 2 1 2 10uF U9 2 U6 2 NC7SZ04P5X 4 R8 33 NC7SVU04P5X 4 3V3 3V3 K 100nF C24 R10 1k R9 1k J K LTM2893CY DEMO CIRCUIT 2405A Wednesday, November 4th, 2015 R11 49.9 J2 CNVST_33 Q_DETECT 1 L 2 2 CLK 100MHz MAX 3.3VPP DATE 11-4-15 KWB L APPROVED ISOLATED 100MHz ADC - SPI INTERFACE SCHEMATIC GND VCC 4.75V to 5.25V 3V3 JP3 JP2 NC7SVU04P5X U8 CP D 33 DESCRIPTION 2ND PROTOTYPE C44 R12 J 10nF C41 PR CLR 6 3V3 B 7 8 GND VDD GND GND REFBUF VDDLBYP REFIN 3 6 16 1 CNV33 10 CLK A 10 9 8 7 6 5 4 3 2 1 DEMO MANUAL DC2405A SCHEMATIC DIAGRAM dc2405af Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 10 9 8 7 6 5 4 3 2 D9 D10 D7 D8 D6 D5 D3 D4 D2 33 M7 33 N8 RA10:A RA9:B A 33 N7 RA9:D 33 K6 M8 J6 33 N6 RA10:B J5 N4 K5 M5 L4 M4 L5 33 N5 RA9:C IOE5 IOH3 IOH2 IOG4 IOF4 IOF6 IOF5 IOG2 IOH1 IOG1 IOJ7 IOM9 IOL10 IOM10 IOK8 IOJ8 IOL11 IOM11 ION9 IOM12 ION10 IOM13 ION12 IOK7 ION11 BANK3 H3 H2 G4 F4 F6 F5 G2 H1 G1 E5 B 10M08SAU169C8GES IOK6 IOM8 IOJ6 ION8 IOM7 ION7 ION6 ION5 IOJ5 ION4 IOK5 IOM5 IOL4 IOM4 IOL5 U10:C 33 RA6:B 33 RA6:C 33 RA6:D 10M08SAU169C8GES IOE1 IOF1 IOB1 IOC1 IOE4 IOE3 IOC2 IOD1 U10:A BANK 1A, 1B RA10:C 33 RA11:A 33 RA10:D 33 RA11:B Q_SDO Q_SPARE Q_SPARE_DIR E1 F1 B1 C1 E4 E3 C2 D1 QSDO QSPR QDIR 33 RA8:A 33 RA9:A L10 M10 K8 J8 L11 33 RA8:B M11 RA7:D RA8:D M12 RA7:B N10 RA8:C M13 RA7:A N9 IOG12 IOH8 IOG13 33 33 33 33 33 33 G12 H8 G13 H9 H13 H10 J13 J9 R35 1k 1 3 5 7 9 CLK2 D12 D16 D13 D17 JP6 OFF 0 3V3 CSC 3V3 1uF C72 CLK Q_EN Q_SDI Q_CS Q_SCK SDI D R24 RA2:A R14 R15 RA1:A R17 RA1:B SDOB 3V3 D 3V3 CNVST_33 CS JP4 CONFIG 1 2 4 6 8 10 SDOA ON JP5 OE 33 RA4:B 33 RA4:C 33 RA4:D 33 RA6:A R31 10k CLKOUT 3V3 C D14 D15 D11 10M08SAU169C8GES IOK13 IOJ12 IOL13 IOH9 IOH13 IOK12 IOL12 IOJ13 IOH10 IOJ10 IOK11 IOJ9 R26 10k 33 TCK 33 TDO 33 TDI 33 TMS BANK5 IOK10 N12 RA7:C K7 N11 J7 M9 K13 J12 L13 K12 L12 J10 K11 K10 U10:D RA5:A RA5:C RA5:D RA5:B R28 10k JTAGEN 3V3 3V3 10k 33 10k 10k 33 10k 33 33 RA1:C 33 RA1:D 33 RA4:A E7 A7 D7 B7 E8 D8 A11 B9 A10 B10 A9 C9 A8 C10 F8 C13 F10 D13 F9 E12 F12 E13 F13 G10 G9 IOE9 IOD11 IOD12 IOD9 IOE10 IOA12 IOC11 IOB13 IOC12 IOB11 BANK8 IOB3 IOB4 IOB2 IOA2 IOC5 IOA5 IOC4 E 10M08SAU169C8GES IOE7 IOA7 IOD7 IOB7 IOE8 IOD8 IOD6 IOB9 IOA11 IOE6 IOA10 IOA3 IOB5 IOA9 IOB10 IOA4 IOB6 IOA6 IOC9 IOA8 IOC10 U10:F 10M08SAU169C8GES IOF8 IOC13 IOF10 IOD13 IOF9 IOE12 IOF12 IOE13 IOF13 3V3 IOB12 BANK6 IOG10 IOG9 U10:E E B2 A2 C5 A5 C4 B4 D6 B3 E6 A3 B5 A4 B6 A6 D11 D12 D9 E10 A12 C11 B13 C12 B11 E9 B12 33 C56 100nF C51 100nF C57 100nF C50 100nF 10k R21 RA3:D F 33 RA3:C 10k 33 R19 33 10k J1 IOK2 IOL3 IOK1 3V3 3V3 SC SB SA 3 K2 L3 K1 M3 L2 N3 L1 N2 100nF C46 100nF C65 100nF C61 100nF C59 100nF C64 D0 D1 1 3 5 7 9 11 13 100k R30 G H THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. 100k R27 R29 E2 D2 A1 A13 B8 C3 D5 E11 F3 G7 H12 J4 L9 M6 N1 N13 10k R33 4.99k R22 R23 100 C47 1uF 2 4 6 8 10 12 14 100k C45 100nF J3 QEVAL 10M08SAU169C8GES ADC_VREF VCCIO8 VCCIO8 VCCIO8 VCCIO6 VCCIO6 VCCIO5 VCCIO5 VCCIO3 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO1A VCCIO1B VCCA1 VCCA2 VCCA3 VCCA4 GND GND GND GND GND GND GND GND GND GND GND GND GND GND REFGND ANAIN1 PWR/GND VCC_ONE VCC_ONE VCC_ONE VCC_ONE CUSTOMER NOTICE 4 33 RA11:D 33 RA11:C D3 C6 C7 C8 F11 G11 H11 J11 L6 L7 L8 J3 K3 F2 G3 K4 D10 D4 K9 F7 G6 G8 H7 H 12 9 5 2 I KWB 13 11 10 8 4 6 1 3 4 D5 D4 D3 D2 D1 D0 Q_CS 3V3 Q_SPARE 24LC024-I/ST J4 100nF PG WP R40 4.99k JP7 EEPROM R36 4.99k SCL SDA 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 J Wednesday, November 4th, 2015 K LTM2893IY DEMO CIRCUIT 2405A ISOLATED 100MHz ADC - SPI INTERFACE 8 7 6 5 C73 D7 D6 Q_SDI A0 VCC A1 WP A2 SCL VSS SDA U19 D9 D8 Q_SPARE_DIR D11 D10 D13 D12 D15 D14 Q_EN SCHEMATIC 1 2 3 4 D17 D16 CLKOUT CLK2 Q_SCK 100nF R20 10k C52 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 R37 4.99k 2 KWB 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 APPROVED DESCRIPTION K 2ND PROTOTYPE 100nF J 3V3 C71 LVC1T45 U18 3 2 REV 74LVT126 U16 - ECO KWB I 3V3 U10:G LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMERS RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. U17 LVC1T45 Q_SDO 10M08SAU169C8GES IOM2 IOH4 IOM1 IOL2 IOM3 IOH5 ION3 IOL1 ION2 IOJ2 IOH6 IOJ1 IOG5 100nF C48 100nF C53 100nF C60 BANK2 100nF C49 100nF C54 100nF C66 U10:B 3V3 M2 H4 M1 H5 J2 H6 FAULT CNV BUSY SCK R18 RA2:C RA3:B 33 RA3:A 33 RA2:D 33 100nF 100nF G5 C69 C62 100nF 100nF 100nF 100nF C70 C55 C63 C67 Q_DETECT RA2:B 100nF C58 100nF C68 G F L DATE L 2 SCL SDA 2 R39 2k R38 4.99k 11-4-15 3V3 1 10k 10k R32 R34 QSCK QCS QEN QSDI C CFG CLR 6 2 B CFGD STAT CRC 6 2 3V3 1 5 3V3 1 5 A 10 9 8 7 6 5 4 3 2 1 DEMO MANUAL DC2405A SCHEMATIC DIAGRAM dc2405af 11 DEMO MANUAL DC2405A DEMONSTRATION BOARD IMPORTANT NOTICE Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions: This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations. If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user's responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive. Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer. Mailing Address: Linear Technology 1630 McCarthy Blvd. Milpitas, CA 95035 Copyright (c) 2004, Linear Technology Corporation 12 Linear Technology Corporation dc2405af LT 0516 * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2016