1
dc2405af
DEMO MANUAL DC2405A
DESCRIPTION
LTM2893
Isolated 100MHz ADC Serial
Interface and LTC2328-18
Demonstration circuit 2405A shows an LT M
®
2893 isolating
and interfacing an LT C
®
2328-18. The LTM2893 is a high
speed SPI isolator for interfacing read only ADCs with a
full complement of control signals. The LTC2328-18 is a
low noise, high speed 18-bit successive approximation
register (SAR) ADC. Low noise isolated power is delivered
to the isolated side with an LT3999 push-pull driver and
isolation transformer.
The DC2405A demonstrates the DC and AC operation of
the LTC2328-18 without performance degradation with
the LTM2893. The Serial Peripheral Interface (SPI) runs L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope
and QuikEval are trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
PERFORMANCE SUMMARY
at a maximum 100MHz SCK frequency. The LTM2893 is
compatible with many ADCs with SPI clock frequencies
up to 100MHz.
The DC2405A connects to either the DC890 for measure-
ments with PScope™, or DC590 for measurements with
QuikEval™, or DC2026 for measurements with QuikEval
and a DC590 sketch or single sample measurements with
an example sketch.
Design files for this circuit board are available at
http://www.linear.com/demo/DC2405A
Specifications are at TA = 25°C
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Supply Range VCC – GND 4.75 5.25 V
Analog Signal Input Range (AIN) ±10.24 V
Clock Frequency (CLK IN) 10 100 MHz
DC590 Interface Voltage Supply 3.0 3.3 3.6 V
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DEMO MANUAL DC2405A
DC2405A CONNECTION DIAGRAM
DC2405A JUMPERS
Figure 1. DC2405A Setup
DEFINITIONS
JP1 – GND2, Isolated ground connection
JP2 – VCC, 5V Power supply input connection
JP3 – GND, Power supply return connection
JP4 – CFG, Default 0, when CFG = 1 a secondary image
in U10 is selected, currently not implemented.
JP5 – OE, Output enable for U10, default ON. When OE is
ON, U10 drives the signals to U1 (for use with the DC890,
DC590, and DC2026). When OE is OFF the signals to U1
are high impedance from U10 and the interface signals
can be driven externally.
JP6 – JTAG, header for factory use only
JP7 – EEPROM, is for factory use only, default WP.
100MHz CLK IN
5V GND
DC890
ANALOG
INPUT
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DEMO MANUAL DC2405A
Figure 2. PScope Display Capturing 2kHz Input Tone
DC890 QUICK START PROCEDURE
Check to make sure that all switches and jumpers are
set to their default settings as described in the DC2405A
Jumpers section and Figure 1 of this manual. The demo
board is designed to use the onboard isolated power sup-
ply to generate all the required bias voltages. The analog
input is DC coupled.
1. Connect the DC2405A to a DC890 USB High Speed
Data Collection Board using the edge connector J4.
2. Connect the DC890 to a host PC with a standard USB
A/B cable.
3. Apply +5V and ground to the VCC and GND terminals.
4. Apply a low jitter signal source to J1. Observe the rec-
ommended input voltage range for the analog input.
5. Connect a low jitter 100MHz 2.5VP-P
sine wave or square
wave to connector J2. Note that J2 has a 50Ω termination
resistor to ground. Alternatively, a DC1216A 100MHz
fixed frequency clock source board can be used.
6. Run the PScope software (Pscope.exe version K83 or
later), which can be downloaded from www.linear.com/
designtools/software. The PScope software should rec-
ognize the DC2405A and configure itself automatically.
7. Click the Collect button (see Figure 2) to begin acquiring
data. The Collect button then changes to Pause, which
can be clicked to stop data acquisition.
Complete PScope software documentation is available
from the Help menu. Updates can be downloaded from
the Tools menu. Check for updates periodically as new
features may be added.
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DEMO MANUAL DC2405A
DC590/DC2026 QUICK START PROCEDURE
IMPORTANT! To avoid damage to the DC2405A, make
sure that VCCIO (JP6 of the DC590, JP3 of the DC2026)
of the DC590/DC2026 is set to 3.3V before connecting
the DC590/DC2026 to the DC2405A.
1. To use the DC590/DC2026 with the DC2405A, it is
necessary to apply 5V and ground to the VCC and GND
terminals of the DC2405A.
2. Connect the DC590/DC2026 to a host PC with a standard
USB A/B cable.
3. Connect the DC2405A to a DC590/DC2026 USB serial
controller using the supplied 14-conductor ribbon cable.
4. Apply a signal source to J1. A clock source on J2 is not
necessary.
5. Run the QuikEval software (QuikEval.exe version K107
or later), which is available from www.linear.com/
designtools/software. The correct control panel will be
loaded automatically.
6. Click the COLLECT button (Figure 3) to begin reading
the ADC.
Figure 3. QuikEval Screenshot Captured with a 50Ω Terminator on AIN
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DEMO MANUAL DC2405A
DC2405A SETUP
DC POWER
The DC2405A requires +5VDC and draws ~265mA. This
current is split between the isolated side and the logic side.
The isolated side current consumption is through the DC/
DC power converter supplying the LT1468, input buffer,
LTC2328-18 ADC, and the isolated side of the LTM2893.
The logic side current supplies the FPGA, clock input path,
and the LTM2893.
CLOCK SOURCE
You must provide a low jitter 2.5VP-P sine or square wave
to the clock input J2 for data collection with the DC890.
The clock input is AC-coupled so the DC level of the clock
signal is not important. A generator, such as the Rohde &
Schwarz SMB100A high speed clock source, is recom-
mended to drive the clock input. Drive J2 with a 100MHz
clock frequency. The ratio between the clock source and
the sampling frequency is 100:1. A 100MHz clock source
results in a 1Msps sampling rate.
DATA OUTPUT
If not connected to a DC890, parallel data output from this
board (0V to 2.5V by default), can be acquired by a logic
analyzer, and subsequently imported into a spreadsheet, or
mathematical package depending on what form of digital
signal processing is desired. Alternatively, the data can
be fed directly into an application circuit. Use pin 50 of
J4, edge connector, to latch the data. The data should be
latched using the negative edge of this signal.
ANALOG INPUTS
The DC2405A analog input AIN is a single-ended input
referenced to GND2. AIN has a high input impedance
buffer (LT1468) before the LTC2328-18 ADC. The default
setup for the DC2405A requires that AIN be driven with
a low noise, low distortion generator for SINAD, THD, or
SNR testing. Use an analog source such as the Stanford
Research DS360 or SR1. Synchronize the clock source
to the analog source through an external reference input
to generate SNR and SINAD results similar to Figure 2
without windowing.
LTM2893 DIGITAL INTERFACE
The demo board has an unpopulated header placeholder
in-between U10 and U1. All interface signals between the
FPGA (U10) and the logic interface of the LTM2893 (U1)
are exposed. An external interface may be connected to
this header location by setting the OE jumper JP5 off.
When JP5 is low, all signals to the LTM2893 will be high
impedance from the FPGA. The header placeholder pin
pitch is on 0.100-inch centers.
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DEMO MANUAL DC2405A
This demo board is tested in-house by attempting to
duplicate the FFT plot shown in Figure 2. This involves
a 100MHz clock source synchronized with a reference
clock to an SR1 sinusoidal generator. The SR1 sinusoidal
generator is set at a frequency of 2.01416kHz. The input
signal level is approximately –1dBFS. A typical FFT obtained
with DC2405A is shown in Figure 2. Note that to calculate
the real SNR, the signal level (F1 amplitude = –1.006dB)
has to be added back to the SNR that PScope displays.
With the example shown in Figure 2, this means that the
actual SNR would be 94.76dB instead of the 93.76dB that
PScope displays.
There are a number of scenarios that can produce mislead-
ing results when evaluating an ADC. One that is common
is feeding the converter with an input frequency that is
a sub-multiple of the sample rate and will only exercise
a small subset of the possible output codes. The proper
method is to pick an M/N frequency for the input sine
wave frequency. N is the number of samples in the FFT. M
is a prime number between one and N/2. Multiply M/N by
the sample rate to obtain the input sine wave frequency.
Another scenario that can yield poor results is if you do
not have a signal generator capable of ppm frequency ac-
curacy or if it cannot be locked to the clock frequency. You
can use an FFT with windowing to reduce the “leakage” or
spreading of the fundamental, to get a close approximation
of the ADC performance. If an amplifier or clock source
with poor phase noise is used, the windowing will not
improve the SNR.
DC2405A DATA COLLECTION
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DEMO MANUAL DC2405A
Due to the relatively low and somewhat unpredictable
sample rate of the DC590/DC2026, its usefulness is lim-
ited to noise measurement and data collection of slowly
moving signals.
To observe measurements from QuikEval, use a DC590 or
program a DC2026 with a DC590 sketch from an Arduino
IDE. Then launch QuikEval, a typical data capture and
histogram are shown in Figure 3.
DC590/DC2026 DATA COLLECTION
To observe measurements and see example code for read-
ing and configuring the LTM2893 from the DC2026, run an
Arduino IDE and select File > Sketchbook > Part Number
> 2000 > 2800 > 2893 >DC2405A. Upload the program to
the DC2026 and launch the Serial Monitor from the tools
menu. A brief menu will display on the serial monitor
output. Selecting 1 and sending to the DC2026 will result
in a single conversion and the result will be displayed in
the Serial Monitor window.
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DEMO MANUAL DC2405A
PARTS LIST
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
1 1 C1 CAPACITOR, CERAMIC, 3.3nF 5% 1206 250V NPO TDK/C3216C0G2E332J085AA
2 40 C2, C8, C15, C17, C18, C20,
C23-C28, C34, C45-46, C48-71, C73
CAPACITOR, CERAMIC, 100nF 10% 0402 50V X7R TDK/C1005X7R1H104K050BB
3 9 C3, C7, C10-13, C43, C47, C72 CAPACITOR, CERAMIC, 1μF 10% 0603 35V X7R TDK/C1608X7R1V105K080AC
4 4 C4-5, C29, C36 CAPACITOR, CERAMIC, 10μF 10% 1206 35V X7R TDK/C3216X7R1V106K160AC
5 0 C6, C9 OPTIONAL
6 1 C14 CAPACITOR, CERAMIC, 47μF 20% 1210 6.3V X7S TDK/C3225X7S0J476M250AC
7 1 C16 CAPACITOR, CERAMIC, 2.2μF 10% 0603 10V X7R TDK/C1608X7R1A225K080AC
8 4 C19, C38, C40, C44 CAPACITOR, CERAMIC, 10μF 10% 0805 16V X6S TDK/C2012X6S1C106K085AC
2 C21-22 CAPACITOR, CERAMIC, 150pF 10% 1808 250V X7R MURATA/GA342QR7GF151KW01L
9 7 C30-32, C35, C37, C39, C41 CAPACITOR, CERAMIC, 10nF 10% 0402 50V X7R TDK/C1005X7R1H103K050BB
10 1 C33 CAPACITOR, CERAMIC, 1μF 10% 1206 100V X7R TDK/C3216X7R2A105K160AA
11 1 C42 CAPACITOR, TANTALUM, 47μF 10% 2413 16V KEMET/T494C476K016AT
12 2 D1-2 DIODE, ARRAY, 75V 215mA SOT363 DIODES INC/BAV99DW-7-F
13 2 J1-2 CONNECTOR, BNC JACK, EDGE MOUNT TE CONNECTIVITY/1274727-1
14 1 J3 HEADER, 2 × 7 2mm SHROUDED MOLEX/87831-1420
15 3 JP1-3 HEADER, LOOP 1 × 2, 0.2mm AAVID/125700D00000G
16 3 JP4-5, JP7 HEADER, 1 × 3, 2mm WURTH/62000311121
17 3 JP4-5, JP7 SHUNT, 1 × 2, 2mm WURTH/60800213421
18 1 JP6 HEADER, 2 ×5, 0.1mm WURTH/61301021121
19 2 L1-2 INDUCTOR, COUPLED, 22μH 3 × 3mm 1.9Ω 0.44A COILCRAFT/LPD3015-223MRB
20 6 MH1-6 STANDOFF, NYLON 0.25" KEYSTONE, 8831 (SNAP ON)
21 2 R3-4 RESISTOR, 0Ω 1% 0603 VISHAY/CRCW06030000Z0EA
22 1 R2 OPTIONAL
23 3 R9-10, R35 RESISTOR, 1kΩ 1% 0603 VISHAY/CRCW06031K00FKEA
24 4 R7-8, R12, R25 RESISTOR, 33Ω 1% 0402 VISHAY/CRCW040233R0FKED
25 1 R11 RESISTOR, 49.9Ω 1% 1206 VISHAY/CRCW120649R9FKEA
26 1 R6 RESISTOR, 28kΩ 1% 0603 VISHAY/CRCW060328K0FKEA
27 1 R5 RESISTOR, 49.9kΩ 1% 0603 VISHAY/CRCW060349K9FKEA
28 7 R13, R16, R22, R36-38, R40 RESISTOR, 4.99kΩ 1% 0603 VISHAY/CRCW06034K99FKEA
29 14 R14-15, R17-21, R24, R26, R28,
R31-33, R34
RESISTOR, 10kΩ 1% 0402 VISHAY/CRCW040210K0FKED
30 2 R1, R23 RESISTOR, 100kΩ 1% 0603 VISHAY/CRCW0603100RFKEA
31 3 R27, R29-30 RESISTOR, 100kΩ 1% 0402 VISHAY/CRCW0402100KFKED
32 1 R39 RESISTOR, 2kΩ 1% 0603 VISHAY/CRCW06032K00FKEA
33 11 RA1-11 RESISTOR ARRAY, 33kΩ 4 RES 1206 PANASONIC/EXB-38V330JV
34 1 TR1 TRANSFORMER, 5kV 2:1 WURTH/750313626
35 1 U1 IC, 100MHz ADC-SPI ISOLATOR LINEAR TECH/LTM2893CY#PBF
36 1 U2 IC, OPAMP LINEAR TECH/LT1468CS8#PBF
37 1 U3 IC, ADC, 1MSPS, 18-BIT, BIPOLAR, ±10.24V LINEAR TECH/LTC2328CMS-18#PBF
38 1 U4 IC, PUSH-PULL DC/DC DRIVER, 1A, 1MHz LINEAR TECH/LT3999EMSE#PBF
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DEMO MANUAL DC2405A
PARTS LIST
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
39 1 U5 IC, BUS SWITCH, SPST, SC70-5 FAIRCHILD SEMI/NC7SZ66P5X
40 1 U6 IC, INVERTER, SC70-5 FAIRCHILD SEMI/NC7SZ04P5X
41 1 U7 IC, D-TYPE POS TRG, MSOP8 ON SEMI/NL17SZ74USG
42 2 U8-9 IC, UNBUFFERED INVERTER, SC70-5 FAIRCHILD SEMI/NC7SVU04P5X
43 1 U10 IC, FPGA/CPLD 130 I/O 169UBGA ALTERA/10M08SAU169C8GES
44 2 U11-12 IC, LDO, 15V, 100mA LINEAR TECH/LT3060ETS8-15#PBF
45 2 U13-14 IC, LDO, 5V, 100mA LINEAR TECH/LT1761ES5-5#PBF
46 1 U15 IC, LDO, 3.3V, 500mA LINEAR TECH/LT1763CDE-3.3#PBF
47 1 U16 IC, BUFFER, TRI-STATE, QUAD, 14TSSOP NXP/74LVT126PW,118
48 2 U17-18 IC, BUS TRANSCEIVER, TRI-STATE, SOT-563 TI/SN74LVC1T45DRLR
49 1 U19 IC, EEPROM, 2-KBIT, I2C, 8TSSOP MICROCHIP/24LC024-I/ST
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dc2405af
DEMO MANUAL DC2405A
SCHEMATIC DIAGRAM
R9
1k
3
2
6
51
74
U2
LT1468
R1
100
C1
3.3nF
NPO
HGFEDCBA
HGFEDCBA
4
5
6
7
8
9
10
4
5
6
7
8
9
10
LKJI
LKJI
1
2
3
1
2
3
R3
0
C6
OPT
15V
C7
1uF
-15V
C3
1uF
C9
OPT
R4
0
5VA
GND
2
OUT
5IN 1
SHDN 3
BYP
4
U13
LT1761-5
5VA
C38
10uF
C37
10nF
C15
100nF
5VD
C18
100nF
C17
100nF
C14
47uF
ON A1
SS A2
MOSI A3
SCK A4
BUSY A5
CNV A6
VL B1
MISOA B2
MISOB B3
CSC B4
GND B5
FAULT B6
VCC C1
GND C2
SA C4
GND C3
SB C5
SC C6
VCC2
N1
GND2
N2
GND2
N3
SA2
N4
SB2
N5
SC2
N6
VL2
P1
MISOA2
P2
MISOB2
P3
VL2
P4
GND2
P5
BUSYS
P6
ON2
R1
SS2
R2
SCK2
R4 MOSI2
R3
BUSY2
R5
CNV2
R6
U1
LTM2893CY
3V3
CHAIN 10
VDD 2
IN+
4
IN-
5
REFBUF 7
REFIN 8
CNV 9
BUSY 11
RDL/SDI 12
SCK 13
SDO 14
OVDD 15
GND
3
GND
6
VDDLBYP
1GND
16
U3
LTC2328-18
5VD
C16
2.2uF
C8
100nF
C2
100nF
R2
OPT
GND
2
OUT
5IN 1
SHDN 3
BYP
4
U14
LT1761-5
5VD
C40
10uF
C39
10nF
C19
10uF
RDC
6OVLO/DC 5
UVLO 4
SWB
10
SYNC
8ILIM/SS
9
VIN 3
RBIAS 2
SWA 1
RT
7
GND 11
U4
LT3999
R6
28k
R5
49.9k
3
16
4
2
5
TR1
C13
1uF
C12
1uF
C42
47uF
2413
C5
10uF
35V
ADJ
7
SHDN 1
OUT
6IN
5
GND 2
REF/BYP
8
GND 3
GND 4
U12
LT3060-15
C32
10nF
C36
10uF
35V
C35
10nF
ADJ
7
SHDN 1
OUT
6IN
5
GND 2
REF/BYP
8
GND 3
GND 4
U11
LT3060-15
C31
10nF
C29
10uF
35V
C30
10nF
C4
10uF
35V
C11
1uF
C10
1uF
15V
-15V
C34
100nF
ISOLATION BARRIER
C33
1uF
L1
22uH
L2
22uH
24
U6
NC7SZ04P5X R11
49.9
R10
1k
C24
100nF
J2 CLK
100MHz MAX
3.3VPP
J1
AIN
+/- 10.24V
3V3
24
U8
NC7SVU04P5X
R25
33
D2
Q
5
CP 1
CLR
6PR 7
Q
3
U7
NL17SZ74
R8
33
3V3
24
U9
NC7SVU04P5X
R12
33
R7
33
CNVST_33
1
2
4
U5
NC7SZ66P5X
CLK
CNV
SDOA
SCK
BUSY
CSC
FAULT
3V3
C44
10uF
C41
10nF
JP2
VCC
4.75V to 5.25V
JP3
GND
CLK
IN
10/11 OUT 2/3
GND
7GND
13
SHDN
8SEN 5
BYP 6
U15
LT1763-3.3
CS
SDI
SDOB
SA
SB
SC
CNV
BSY
SCK
SDI
CS
FLT
CSC
SOB
SOA
CNV33
ETADDEVORPPAVEROCE DESCRIPTION
SC
SB
SA
C43
1uF
Q_DETECT
R16
4.99k
R13
4.99k
3V3
C26
100nF
C28
100nF
C23
100nF
3V3
C25
100nF
C27
100nF
KWB
KWB
215102 ,ht4 rebmevoN ,yadsendeW
2
- 2 2ND PROTOTYPE KWB 11-4-15
LTM2893CY
DEMO CIRCUIT 2405A
SCHEMATIC
ISOLATED 100MHz ADC - SPI INTERFACE
NOTE: UNLESS OTHERWISE SPECIFIED
1. INSTALL SHUNTS AS SHOWN.
15V
5VA5VD
-15V
JP1
GND2
C20
100nF
-VI +VI
CNV2
BSY2
SCK2
SDO2
CUSTOMER NOTICE
THIS CIRCUIT IS PROPRIETARY TO
LINEAR TECHNOLOGY AND SUPPLIED FOR
USE WITH LINEAR TECHNOLOGY PARTS.
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT
TO DESIGN A CIRCUIT THAT MEETS CUSTOMER -
SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS
THE CUSTOMERS RESPONSIBILITY TO VERIFY
PROPER AND RELIABLE OPERATION IN THE ACTUAL
APPLICATION. COMPONENT SUBSTITUTION AND
PRINTED CIRCUIT LAYOUT MAY SIGNIFICANTLY
AFFECT CIRCUIT PERFORMANCE OR RELIABILITY.
CONTACT LINEAR TECHNOLOGY APPLICATIONS
ENGINEERING FOR ASSISTANCE.
3V3
D2:A
BAV99DW
D2:B
D1:A
BAV99DW
D1:B
GND
GND2
C21
150pF
C22
150pF
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dc2405af
DEMO MANUAL DC2405A
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
SCHEMATIC DIAGRAM
SDA
SCL
TMS
TCK
TDO
TDI
2
4
6
8
10
12
14
1
3
5
7
9
11
13
J3
QEVAL
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
12
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
J4
A B C DE FG H
A BC DE F G H
4
5
6
7
8
9
10
4
5
6
7
8
9
10
I J KL
I J KL
1
2
3
1
2
3
R38
4.99k
3V3
R39
2k
SCL 6
SDA 5
WP 7
A0
1
A1
2
A2
3
VCC 8
VSS
4
U19
24LC024-I/ST
R40
4.99k
R36
4.99k
R37
4.99k
C73
100nF JP7
EEPROM
WP
PG
Q_EN
Q_SDO
Q_SDI
Q_CS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
CLKOUT
BANK 1A, 1B
IOE5 E5
IOD1
D1
IOG1 G1
IOH1 H1
IOG2 G2
IOC2
C2
IOE3
E3
IOE4
E4
IOF5 F5
IOF4 F4
IOH2 H2
IOG4 G4
IOF6 F6
IOH3 H3
IOF1
F1
IOB1
B1
IOC1
C1
IOE1
E1
U10:A
10M08SAU169C8GES
BANK2
ION2 N2
IOG5
G5
IOL1 L1
ION3 N3
IOL2 L2
IOJ1
J1
IOH6
H6
IOJ2
J2
IOM3 M3
IOL3 L3
IOK2 K2
IOK1 K1
IOH4
H4
IOM1
M1
IOH5
H5
IOM2
M2
U10:B
10M08SAU169C8GES
BANK3
IOM9 M9
IOL5
L5
IOJ7 J7
ION11 N11
IOK7 K7
IOM4
M4
IOL4
L4
IOM5
M5
ION12 N12
ION10 N10
IOM12 M12
IOM13 M13
IOJ5
J5
ION4
N4
IOK5
K5
ION5
N5
ION6
N6
ION7
N7
IOM7
M7
IOM8
M8
IOJ6
J6
ION8
N8
IOK6
K6
ION9 N9
IOM11 M11
IOL11 L11
IOJ8 J8
IOM10 M10
IOL10 L10
IOK8 K8
U10:C
10M08SAU169C8GES
BANK5
IOJ9 J9
IOK10
K10
IOJ13 J13
IOH10 H10
IOH13 H13
IOK11
K11
IOJ10
J10
IOL12
L12
IOH9 H9
IOH8 H8
IOG12 G12
IOG13 G13
IOJ12
J12
IOL13
L13
IOK12
K12
IOK13
K13
U10:D
10M08SAU169C8GES
BANK6
IOB12 B12
IOG9
G9
IOE9 E9
IOB11 B11
IOC12 C12
IOG10
G10
IOF13
F13
IOE13
E13
IOB13 B13
IOA12 A12
IOE10 E10
IOC11 C11
IOF9
F9
IOE12
E12
IOF12
F12
IOD13
D13
IOF10
F10
IOC13
C13
IOF8
F8
IOD9 D9
IOD12 D12
IOD11 D11
U10:E
10M08SAU169C8GES
BANK8
IOA6 A6
IOC10
C10
IOB6 B6
IOA4 A4
IOB5 B5
IOA8
A8
IOC9
C9
IOA9
A9
IOA3 A3
IOB3 B3
IOD6 D6
IOE6 E6
IOB9
B9
IOA10
A10
IOB10
B10
IOA11
A11
IOD8
D8
IOE8
E8
IOB7
B7
IOE7
E7
IOA7
A7
IOD7
D7
IOB4 B4
IOC4 C4
IOA5 A5
IOC5 C5
IOB2 B2
IOA2 A2
U10:F
10M08SAU169C8GES
PWR/GND
ADC_VREF
D3
GND A1
VCC_ONE
F7
GND A13
GND B8
VCCIO1A
F2
GND C3
VCC_ONE
G6
VCC_ONE
G8
VCC_ONE
H7
VCCIO3
L6
GND D5
VCCIO2
K3 GND N13
GND N1
VCCIO1B
G3
GND F3
VCCIO2
J3
GND H12
GND G7
REFGND E2
GND E11
GND J4
GND L9
GND M6
ANAIN1 D2
VCCA3
D4 VCCA2
D10 VCCA1
K4
VCCA4
K9
VCCIO3
L7
VCCIO3
L8
VCCIO5
H11
VCCIO5
J11
VCCIO6
F11
VCCIO6
G11
VCCIO8
C6
VCCIO8
C7
VCCIO8
C8
U10:G
10M08SAU169C8GES
C67
100nF
C63
100nF
C55
100nF
C70
100nF
C59
100nF
C62
100nF
C69
100nF
C66
100nF
C60
100nF
C61
100nF
C57
100nF
C56
100nF
C54
100nF
C53
100nF
C65
100nF
C50
100nF
C51
100nF
C49
100nF
C48
100nF
C46
100nF
C68
100nF
C58
100nF
3V3
Q_EN
1 2
3 4
5 6
7 8
910
JP6
R31
10k
3V3
R28
10k
JTAGEN
R35
1k
3V3
CNVST_33
CLK
D1
D0
D5
D2
D4
D6
C72
1uF
D3
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
CLKOUT
SA
SB
SC
SCK
CS
SDI
CSC
CNV
SDOA
SDOB
FAULT
BUSY
Q_SDI
Q_SCK
Q_CS
Q_SDO
Q_SCK
R24 10k
R14 10k
R18 10k
R21 10k
R19 10k
R17 10k
R15 10k
3V3
3V3
CFGD
CRC
3V3
CLR
CFG
3V3
3V3
3V3
STAT
3V3
SCL
SDA
QSDO
QSDI
QSCK
QCS
QSPR
ECO REV APPROVED DATEDESCRIPTION
CLK2
CLK2
QEN
Q_DETECT
JP4
CONFIG
10
JP5
OE
ON
OFF
Q_SPARE
2 3
1
5 6
4
9 8
10
12 11
13
U16
74LVT126
R20
10k
3V3
Q_SPARE
Q_SPARE_DIR
3 4
1
6
5
2
U17
LVC1T45
34
1
6
5
2
U18
LVC1T45
Q_SPARE_DIR
3V3
R33
10k
R22
4.99k
C45
100nF
R34 10k
3V3 3V3
C52
100nF
C64
100nF
C71
100nF
3V3
- 2 2ND PROTOTYPE KWB 11-4-15
KWB
KWB
Wednesday, November 4th, 2015 2 2
2
LTM2893IY
DEMO CIRCUIT 2405A
SCHEMATIC
ISOLATED 100MHz ADC - SPI INTERFACE
CUSTOMER NOTICE
THIS CIRCUIT IS PROPRIETARY TO
LINEAR TECHNOLOGY AND SUPPLIED FOR
USE WITH LINEAR TECHNOLOGY PARTS.
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT
TO DESIGN A CIRCUIT THAT MEETS CUSTOMER -
SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS
THE CUSTOMERS RESPONSIBILITY TO VERIFY
PROPER AND RELIABLE OPERATION IN THE ACTUAL
APPLICATION. COMPONENT SUBSTITUTION AND
PRINTED CIRCUIT LAYOUT MAY SIGNIFICANTLY
AFFECT CIRCUIT PERFORMANCE OR RELIABILITY.
CONTACT LINEAR TECHNOLOGY APPLICATIONS
ENGINEERING FOR ASSISTANCE.
R23
100
C47
1uF
R32 10k
QDIR
RA5:B 33
RA5:A 33
RA5:C 33
RA5:D 33
RA11:A
33
RA11:B
33
RA11:C
33
RA11:D
33
RA10:A 33
RA10:B 33
RA10:C 33
RA10:D
33
RA9:A
33
RA9:B 33
RA9:C
33
RA9:D 33
RA8:A
33
RA8:B
33
RA8:C 33
RA8:D 33
RA7:A 33
RA7:B 33
RA7:C 33
RA7:D 33
RA6:B
33
RA6:A
33
RA6:C
33
RA6:D
33
RA4:D
33
RA4:B
33
RA4:A
33
RA4:C
33
RA1:B 33
RA1:A 33
RA1:D
33
RA1:C
33
RA2:A 33
RA2:B
33
RA2:C 33
RA2:D
33
RA3:A
33
RA3:B
33
RA3:C 33
RA3:D 33
R27
100k
R30
100k
R29
100k
R26
10k
3V3
12
dc2405af
DEMO MANUAL DC2405A
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2016
LT 0516 • PRINTED IN USA
DEMONSTRATION BOARD IMPORTANT NOTICE
Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:
This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT
OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety
measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union
directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.
If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date
of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU
OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS
FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR
ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or
agency certified (FCC, UL, CE, etc.).
No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance,
customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.
Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and
observe good laboratory practice standards. Common sense is encouraged.
This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application
engineer.
Mailing Address:
Linear Technology
1630 McCarthy Blvd.
Milpitas, CA 95035
Copyright © 2004, Linear Technology Corporation
