TP3067V - Texas Instruments High-Performance Analog

TP3064, TP3067

Enhanced Serial Interface CMOS CODEC/Filter COMBO

Literature Number: SNAS570

TL/H/5070

TP3064, TP3067 ‘‘Enhanced’’ Serial Interface CMOS CODEC/Filter COMBO

October 1991

TP3064, TP3067

‘‘Enhanced’’ Serial Interface

CMOS CODEC/Filter COMBOÉ

General Description

The TP3064 (m-law) and TP3067 (A-law) are monolithic

PCM CODEC/Filters utilizing the A/D and D/A conversion

architecture shown in

Figure 1

, and a serial PCM interface.

The devices are fabricated using National’s advanced dou-

ble-poly CMOS process (microCMOS).

Similar to the TP305X family, these devices feature an addi-

tional Receive Power Amplifier to provide push-pull bal-

anced output drive capability. The receive gain can be ad-

justed by means of two external resistors for an output level

of up to g6.6V across a balanced 600Xload.

Also included is an Analog Loopback switch and a TSXout-

put.

See also AN-370, ‘‘Techniques for Designing with CODEC/

Filter COMBO Circuits.’’

COMBOÉand TRI-STATEÉare registered trademarks of National Semiconductor Corpora-

tion.

Features

YComplete CODEC and filtering system including:

Ð Transmit high-pass and low-pass filtering

Ð Receive low-pass filter with sin x/x correction

Ð Active RC noise filters

Ðm-law or A-law compatible COder and DECoder

Ð Internal precision voltage reference

Ð Serial I/O interface

Ð Internal auto-zero circuitry

Ð Receive push-pull power amplifiers

Ym-lawÐTP3064

YA-lawÐTP3067

YDesigned for D3/D4 and CCITT applications

Yg5V operation

YLow operating powerÐtypically 70 mW

YPower-down standby modeÐtypically 3 mW

YAutomatic power-down

YTTL or CMOS compatible digital interfaces

YMaximizes line interface card circuit density

Block Diagram

TL/H/5070–1

FIGURE 1

C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Connection Diagrams

Dual-In-Line Package

TL/H/5070–2

Top View

Plastic Chip Carrier

TL/H/5070–6

Top View

Order Number TP3064J or TP3067J

See NS Package J20A

Order Number TP3064WM or TP3067WM

See NS Package M20B

Order Number TP3064N or TP3067N

See NS Package N20A

Order Number TP3064V or TP3067V

See NS Package V20A

Pin Description

Symbol Function

VPOaThe non-inverted output of the receive power

amplifier.

GNDA Analog ground. All signals are referenced to

this pin.

VPObThe inverted output of the receive power

amplifier.

VPI Inverting input to the receive power amplifier.

VFRO Analog output of the receive filter.

VCC Positive power supply pin. VCCea5Vg5%.

FSRReceive frame sync pulse which enables

BCLKRto shift PCM data into DR.FS

Ris an

8 kHz pulse train. See

Figures 2

and

for

timing details.

DRReceive data input. PCM data is shifted into

DRfollowing the FSRleading edge.

BCLKR/ The bit clock which shifts data into DRafter

the FSRleading edge. May vary from 64 kHz

CLKSEL

to 2.048 MHz. Alternatively, may be a logic

input which selects either

1.536 MHz/1.544 MHz or 2.048 MHz for

master clock in synchronous mode and

BCLKXis used for both transmit and receive

directions (see Table I).

MCLKR/ Receive master clock. Must be 1.536 MHz,

1.544 MHz or 2.048 MHz. May be

PDN

asynchronous with MCLKX, but should be

synchronous with MCLKXfor best

performance. When MCLKRis connected

continuously low, MCLKXis selected for all

internal timing. When MCLKRis connected

continuously high, the device is powered

down.

Symbol Function

MCLKXTransmit master clock. Must be 1.536 MHz,

1.544 MHz or 2.048 MHz. May be

asynchronous with MCLKR. Best

performance is realized from synchronous

operation.

BCLKXThe bit clock which shifts out the PCM data

on DX. May vary from 64 kHz to 2.048 MHz,

but must be synchronous with MCLKX.

DXThe TRI-STATEÉPCM data output which is

enabled by FSX.

FSXTransmit frame sync pulse input which

enables BCLKXto shift out the PCM data on

DX.FS

Xis an 8 kHz pulse train, see

Figures 2

and

for timing details.

TSXOpen drain output which pulses low during

the encoder time slot.

ANLB Analog Loopback control input. Must be set

to logic ‘0’ for normal operation. When pulled

to logic ‘1’, the transmit filter input is

disconnected from the output of the transmit

preamplifier and connected to the VPOa

output of the receive power amplifier.

GSXAnalog output of the transmit input amplifier.

Used to externally set gain.

VFXIbInverting input of the transmit input amplifier.

VFXIaNon-inverting input of the transmit input

amplifier.

VBB Negative power supply pin. VBBeb5Vg5%.

Functional Description

POWER-UP

When power is first applied, power-on reset circuitry initializ-

es the COMBOTM and places it into a power-down state. All

non-essential circuits are deactivated and the DX,VF

VPOband VPOaoutputs are put in high impedance states.

To power-up the device, a logical low level or clock must be

applied to the MCLKR/PDN pin

and

FSXand/or FSRpulses

must be present. Thus, 2 power-down control modes are

available. The first is to pull the MCLKR/PDN pin high; the

alternative is to hold both FSXand FSRinputs continuously

lowÐthe device will power-down approximately 2 ms after

the last FSXor FSRpulse. Power-up will occur on the first

FSXor FSRpulse. The TRI-STATE PCM data output, DX,

will remain in the high impedance state until the second FSX

pulse.

SYNCHRONOUS OPERATION

For synchronous operation, the same master clock and bit

clock should be used for both the transmit and receive di-

rections. In this mode, a clock must be applied to MCLKX

and the MCLKR/PDN pin can be used as a power-down

control. A low level on MCLKR/PDN powers up the device

and a high level powers down the device. In either case,

MCLKXwill be selected as the master clock for both the

transmit and receive circuits. A bit clock must also be ap-

plied to BCLKXand the BCLKR/CLKSEL can be used to

select the proper internal divider for a master clock of 1.536

MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation,

the device automatically compensates for the 193rd clock

pulse each frame.

With a fixed level on the BCLKR/CLKSEL pin, BLCKXwill be

selected as the bit clock for both the transmit and receive

directions. Table I indicates the frequencies of operation

which can be selected, depending on the state of BCLKR/

CLKSEL. In this synchronous mode, the bit clock, BCLKX,

may be from 64 kHz to 2.048 MHz, but must be synchro-

nous with MCLKX.

Each FSXpulse begins the encoding cycle and the PCM

data from the previous encode cycle is shifted out of the

enabled DXoutput on the positive edge of BCLKX. After 8

bit clock periods, the TRI-STATE DXoutput is returned to a

high impedance state. With an FSRpulse, PCM data is

latched via the DRinput on the negative edge of BCLKX(or

BCLKRif running). FSXand FSRmust be synchronous with

MCLKX/R.

TABLE I. Selection of Master Clock Frequencies

Master Clock

BCLKR/CLKSEL Frequency Selected

TP3067 TP3064

Clocked 2.048 MHz 1.536 MHz or

1.544 MHz

0 1.536 MHz or 2.048 MHz

1.544 MHz

1 2.048 MHz 1.536 MHz or

1.544 MHz

ASYNCHRONOUS OPERATION

For asynchronous operation, separate transmit and receive

clocks may be applied. MCLKXand MCLKRmust be 2.048

MHz for the TP3067, or 1.536 MHZ, 1.544 MHz for the

TP3064, and need not be synchronous. For best transmis-

sion performance, however, MCLKRshould be synchronous

with MCLKX, which is easily achieved by applying only static

logic levels to the MCLKR/PDN pin. This will automatically

connect MCLKXto all internal MCLKRfunctions (see Pin

Description). For 1.544 MHz operation, the device automati-

cally compensates for the 193rd clock pulse each frame.

FSXstarts each encoding cycle and must be synchronous

with MCLKXand BCLKX.FS

Rstarts each decoding cycle

and must be synchronous with BCLKR. BCLKRmust be a

clock, the logic levels shown in Table I are not valid in asyn-

chronous mode. BCLKXand BCLKRmay operate from 64

kHz to 2.048 MHz.

SHORT FRAME SYNC OPERATION

The COMBO can utilize either a short frame sync pulse (the

same as the TP3020/21 CODECs) or a long frame sync

pulse. Upon power initialization, the device assumes a short

frame mode. In this mode, both frame sync pulses, FSXand

FSR, must be one bit clock period long, with timing relation-

ships specified in

Figure 2

. With FSXhigh during a falling

edge of BCLKX, the next rising edge of BCLKXenables the

DXTRI-STATE output buffer, which will output the sign bit.

The following seven rising edges clock out the remaining

seven bits, and the next falling edge disables the DXoutput.

With FSRhigh during a falling edge of BCLKR(BCLKXin

synchronous mode), the next falling edge of BCLKRlatches

in the sign bit. The following seven falling edges latch in the

seven remaining bits. All devices may utilize the short frame

sync pulse in synchronous or asynchronous operating

mode.

LONG FRAME SYNC OPERATION

To use the long (TP5116A/56 CODECs) frame mode, both

the frame sync pulses, FSXand FSR, must be three or more

bit clock periods long, with timing relationships specified in

Figure 3

. Based on the transmit frame sync, FSX, the COM-

BO will sense whether short or long frame sync pulses are

being used. For 64 kHz operation, the frame sync pulse

must be kept low for a minimum of 160 ns. The DXTRI-

STATE output buffer is enabled with the rising edge of FSX

or the rising edge of BCLKX, whichever comes later, and the

first bit clocked out is the sign bit. The following seven

BCLKXrising edges clock out the remaining seven bits. The

DXoutput is disabled by the falling BCLKXedge following

the eighth rising edge, or by FSXgoing low, whichever

comes later. A rising edge on the receive frame sync pulse,

FSR, will cause the PCM data at DRto be latched in on the

next eight falling edges of BCLKR(BCLKXin synchronous

mode). All devices may utilize the long frame sync pulse in

synchronous or asynchronous mode.

TRANSMIT SECTION

The transmit section input is an operational amplifier with

provision for gain adjustment using two external resistors,

see

Figure 4

. The low noise and wide bandwidth allow gains

in excess of 20 dB across the audio passband to be real-

ized. The op amp drives a unity-gain filter consisting of RC

active pre-filter, followed by an eighth order switched-ca-

pacitor bandpass filter clocked at 256 kHz. The output of

this filter directly drives the encoder sample-and-hold circuit.

The A/D is of companding type according to m-law

(TP3064) or A-law (TP3067) coding conventions. A preci-

sion voltage reference is trimmed in manufacturing to pro-

vide an input overload (tMAX) of nominally 2.5V peak (see

Functional Description (Continued)

table of Transmission Characteristics). The FSXframe sync

pulse controls the sampling of the filter output, and then the

successive-approximation encoding cycle begins. The 8-bit

code is then loaded into a buffer and shifted out through DX

at the next FSXpulse. The total encoding delay will be ap-

proximately 165 ms (due to the transmit filter) plus 125 ms

(due to encoding delay), which totals 290 ms. Any offset

voltage due to the filters or comparator is cancelled by sign

bit integration.

RECEIVE SECTION

The receive section consists of an expanding DAC which

drives a fifth order switched-capacitor low pass filter

clocked at 256 kHz. The decoder is A-law (TP3067) or

m-law (TP3064) and the 5th order low pass filter corrects for

the sin x/x attenuation due to the 8 kHz sample/hold. The

filter is then followed by a 2nd order RC active post-filter

with its output at VFRO. The receive section is unity-gain,

but gain can be added by using the power amplifiers. Upon

the occurrence of FSR, the data at the DRinput is clocked in

on the falling edge of the next eight BCLKR(BCLKX) peri-

ods. At the end of the decoder time slot, the decoding cycle

begins, and 10 ms later the decoder DAC output is updated.

The total decoder delay is E10 ms (decoder update) plus

110 ms (filter delay) plus 62.5 ms((/2 frame), which gives

approximately 180 ms.

RECEIVE POWER AMPLIFIERS

Two inverting mode power amplifiers are provided for direct-

ly driving a matched line interface transformer. The gain of

the first power amplifier can be adjusted to boost the g2.5V

peak output signal from the receive filter up to g3.3V peak

into an unbalanced 300Xload, or g4.0V into an unbal-

anced 15 kXload. The second power amplifier is internally

connected in unity-gain inverting mode to give 6 dB of signal

gain for balanced loads.

Maximum power transfer to a 600Xsubscriber line termina-

tion is obtained by differentially driving a balanced trans-

former with a

2:1 turns ratio, as shown in

Figure 4

. A total

peak power of 15.6 dBm can be delivered to the load plus

termination.

ENCODING FORMAT AT DXOUTPUT

TP3064 TP3067

m-Law A-Law

(Includes Even Bit Inversion)

VIN ea

Full-Scale 1 000000010101010

IN e0V 1 111111111010101

Ð0 111111101010101

IN eb

Full-Scale 0 000000000101010

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

VCC to GNDA 7V

VBB to GNDA b7V

Voltage at any Analog Input

or Output VCCa0.3V to VBBb0.3V

Voltage at any Digital Input

or Output VCCa0.3V to GNDAb0.3V

Operating Temperature Range b25§Ctoa

125§C

Storage Temperature Range b65§Ctoa

150§C

Lead Temp. (Soldering, 10 sec.) 300§C

ESD (Human Body Model) J 1000V

ESD (Human Body Model) N 1500V

Latch-Up Immunity 100 mA on Any Pin

Electrical Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e

a5.0V g5%, VBB eb

5.0V g5%; TAe0§Cto70

C by correlation with 100% electrical testing at TAe25§C. All other limits

are assured by correlation with other production tests and/or product design and characterization. All signals referenced to

GNDA. Typicals specified at VCC ea

5.0V, VBB eb

5.0V, TAe25§C.

Symbol Parameter Conditions Min Typ Max Units

POWER DISSIPATION (ALL DEVICES)

ICC0 Power-Down Current (Note) 0.5 1.5 mA

IBB0 Power-Down Current (Note) 0.05 0.3 mA

ICC1 Active Current VPIe0V; VFRO, VPOaand VPObunloaded 7.0 10.0 mA

IBB1 Active Current VPIe0V; VFRO, VPOaand VPObunloaded 7.0 10.0 mA

DIGITAL INTERFACE

VIL Input Low Voltage 0.6 V

VIH Input High Voltage 2.2 V

VOL Output Low Voltage DX,I

3.2 mA 0.4 V

TSX,I

3.2 mA, Open Drain 0.4 V

VOH Output High Voltage DX,I

eb3.2 mA 2.4 V

IIL Input Low Current GNDAsVINsVIL, All Digital Inputs b10 10 mA

IIH Input High Current VIHsVINsVCC b10 10 mA

IOZ Output Current in High Impedance DX, GNDAsVOsVCC b10 10 mA

State (TRI-STATE)

Note: ICC0 and IBB0 are measured after first achieving a power-up state.

Electrical Characteristics (Continued)

Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC ea

5.0Vg5%, VBB eb

5.0Vg5%; TAe

0§Cto70

C by correlation with 100% electrical testing at TAe25§C. All other limits are assured by correlation with other

production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC e

a5.0V, VBB eb

5.0V, TAe25§C.

Symbol Parameter Conditions Min Typ Max Units

ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)

IIXA Input Leakage Current b2.5VsVsa2.5V, VFXIaor VFXIbb200 200 nA

RIXA Input Resistance b2.5VsVsa2.5V, VFXIaor VFXIb10 MX

ROXA Output Resistance Closed Loop, Unity Gain 1 3 X

RLXA Load Resistance GSX10 kX

CLXA Load Capacitance GSX50 pF

VOXA Output Dynamic Range GSX,R

10 kXb2.8 a2.8 V

AVXA Voltage Gain VFXIato GSX5000 V/V

FUXA Unity-Gain Bandwidth 1 2 MHz

VOSXA Offset Voltage b20 20 mV

VCMXA Common-Mode Voltage CMRRXA l60 dB b2.5 2.5 V

CMRRXA Common-Mode Rejection Ratio DC Test 60 dB

PSRRXA Power Supply Rejection Ratio DC Test 60 dB

ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)

RORF Output Resistance Pin VFRO13X

RF Load Resistance VFROeg2.5V 10 kX

CLRF Load Capacitance Connect from VFRO to GNDA 25 pF

VOSRO Output DC Offset Voltage Measure from VFRO to GNDA b200 200 mV

ANALOG INTERFACE WITH POWER AMPLIFIERS (ALL DEVICES)

IPI Input Leakage Current b1.0VsVPIs1.0V b100 100 nA

RIPI Input Resistance b1.0VsVPIs1.0V 10 MX

VIOS Input Offset Voltage b25 25 mV

ROP Output Resistance Inverting Unity-Gain at 1 X

VPOaor VPOb

FCUnity-Gain Bandwidth Open Loop (VPOb) 400 kHz

CLP Load Capacitance 100 pF

GAPaGain from VPObto VPOaRLe600XVPOato VPObb1 V/V

Level at VPObe1.77 Vrms

PSRRPPower Supply Rejection of VPObConnected to VPI

VCC or VBB 0 kHzb4 kHz 60 dB

4 kHzb50 kHz 36 dB

RLP Load Resistance Connect from VPOato VPOb600 X

Timing Specifications

Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC ea

5.0V g5%, VBB eb

5.0V g5%, TAe

0§Cto70

C by correlation with 100% electrical testing at TAe25§C. All other limits are assured by correlation with other

production tests and/or product design and characterization. All signals are referenced to GNDA. Typicals specified at VCC e

a5.0V, VBB eb

5.0V, TAe25§C. All timing parameters are measured at VOH e2.0V and VOL e0.7V.

See Definitions and Timing Conventions section for test methods information.

Symbol Parameter Conditions Min Typ Max Units

1/tPM Frequency of Master Clock 1.536 MHz

1.544 MHz

MCLKXand MCLKR2.048 MHz

tRM Rise Time of Master Clock MCLKXand MCLKR50 ns

tFM Fall Time of Master Clock MCLKXand MCLKR50 ns

tPB Period Bit of Clock 485 488 15725 ns

tRB Rise Time of Bit Clock BCLKXand BCLKR50 ns

tFB Fall Time of Bit Clock BCLKXand BCLKR50 ns

tWMH Width of Master Clock High MCLKXand MCLKR160 ns

tWML Width of Master Clock Low MCLKXand MCLKR160 ns

tSBFM Set-Up Time from BCLKXHigh 100 ns

to MCLKXFalling Edge

tSFFM Set-Up Time from FSXHigh Long Frame Only 100 ns

to MCLKXFalling Edge

tWBH Width of Bit Clock High 160 ns

tWBL Width of Bit Clock Low 160 ns

tHBFL Holding Time from Bit Clock Long Frame Only 0ns

Low to Frame Sync

tHBFS Holding Time from Bit Clock Short Frame Only 0ns

High to Frame Sync

tSFB Set-Up Time for Frame Sync Long Frame Only 80 ns

to Bit Clock Low

tDBD Delay Time from BCLKXHigh Loade150 pF plus 2 LSTTL Loads 0 180 ns

to Data Valid

tDBTS Delay Time to TSXLow Loade150 pF plus 2 LSTTL Loads 140 ns

tDZC Delay Time from BCLKXLow to 50 165 ns

Data Output Disabled

tDZF Delay Time to Valid Data from CLe0 pF to 150 pF 20 165 ns

FSXor BCLKX, Whichever

Comes Later

tSDB Set-Up Time from DRValid to 50 ns

BCLKR/X Low

tHBD Hold Time from BCLKR/X Low to 50 ns

DRInvalid

tSF Set-Up Time from FSX/R to Short Frame Sync Pulse (1 Bit Clock 50 ns

BCLKX/R Low Period Long)

tHF Hold Time from BCLKX/R Low Short Frame Sync Pulse (1 Bit Clock 100 ns

to FSX/R Low Period Long)

tHBFI Hold Time from 3rd Period of Long Frame Sync Pulse (from 3 to 8 Bit 100 ns

Bit Clock Low to Frame Sync Clock Periods Long)

(FSXor FSR)

tWFL Minimum Width of the Frame 64k Bit/s Operating Mode 160 ns

Sync Pulse (Low Level)

Timing Diagrams

TL/H/5070–3

FIGURE 2. Short Frame Sync Timing

Timing Diagrams (Continued)

TL/H/5070–4

FIGURE 3. Long Frame Sync Timing

Transmission Characteristics

Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC ea

5.0V g5%, VBB eb

5.0V g5%; TAe

0§Cto70

C by correlation with 100% electrical testing at TAe25§C. All other limits are assured by correlation with other

production tests and/or product design and characterization. GNDA e0V, f e1.02 kHz, VIN e0 dbm0, transmit input amplifier

connected for unity gain non-inverting. Typicals specified at VCC ea

5.0V, VBB eb

5.0V, TAe25§C.

Symbol Parameter Conditions Min Typ Max Units

AMPLITUDE RESPONSE

Absolute Levels Nominal 0 dBm0 Level is 4 dBm

(Definition of (600X)

nominal gain) 0 dBm0 1.2276 Vrms

tMAX Virtual Decision Value Defined Max Transmit Overload Level

per CCITT Rec. G711 TP3064 (3.17 dBm0) 2.501 VPK

TP3067 (3.14 dBm0) 2.492 VPK

GXA Transmit Gain, Absolute TAe25§C, VCCe5V, VBBeb5V b0.15 0.15 dB

GXR Transmit Gain, Relative to GXA fe16 Hz b40 dB

fe50 Hz b30 dB

fe60 Hz b26 dB

fe200 Hz b1.8 b0.1 dB

fe300 Hz-3000 Hz b0.15 0.15 dB

fe3300 Hz b0.35 0.05 dB

fe3400 Hz b0.7 0 dB

fe4000 Hz b14 dB

fe4600 Hz and Up, Measure b32 dB

Response from 0 Hz to 4000 Hz

GXAT Absolute Transmit Gain Variation Relative to GXA b0.1 0.1 dB

with Temperature

GXAV Absolute Transmit Gain Variation Relative to GXA b0.05 0.05 dB

with Supply Voltage

GXRL Transmit Gain Variations with Sinusoidal Test Method

Level Reference Leveleb10 dBm0

VFXIaeb40 dBm0 to a3 dBm0 b0.2 0.2 dB

VFXIaeb50 dBm0 to b40 dBm0 b0.4 0.4 dB

VFXIaeb55 dBm0 to b50 dBm0 b1.2 1.2 dB

GRA Receive Gain, Absolute TAe25§C, VCCe5V, VBBeb5V b0.15 0.15 dB

InputeDigital Code Sequence

for 0 dBm0 Signal

GRR Receive Gain, Relative to GRA fe0 Hz to 3000 Hz b0.15 0.15 dB

fe3300 Hz b0.35 0.05 dB

fe3400 Hz b0.7 0 dB

fe4000 Hz b14 dB

GRAT Absolute Receive Gain Variation Relative to GRA b0.1 0.1 dB

with Temperature

GRAV Absolute Receive Gain Variation Relative to GRA b0.05 0.05 dB

with Supply Voltage

GRRL Receive Gain Variations with Sinusoidal Test Method; Reference

Level Input PCM Code Corresponds to an

Ideally Encoded b10 dBm0 Signal

PCM Leveleb40 dBm0 to a3 dBm0 b0.2 0.2 dB

PCM Leveleb50 dBm0 to b40 dBm0 b0.4 0.4 dB

PCM Leveleb55 dBm0 to b50 dBm0 b1.2 1.2 dB

VRO Receive Filter Output at VFRORL

10 kXb2.5 2.5 V

Transmission Characteristics (Continued)

Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC ea

5.0V g5%, VBB eb

5.0V g5%; TAe

0§Cto70

C by correlation with 100% electrical testing at TAe25§C. All other limits are assured by correlation with other

production tests and/or product design and characterization. GNDA e0V, f e1.02 kHz, VIN e0 dbm0, transmit input amplifier

connected for unity gain non-inverting. Typicals specified at VCC ea

5.0V, VBB eb

5.0V, TAe25§C.

Symbol Parameter Conditions Min Typ Max Units

ENVELOPE DELAY DISTORTION WITH FREQUENCY

DXA Transmit Delay, Absolute fe1600 Hz 290 315 ms

DXR Transmit Delay, Relative to DXA fe500 Hzb600 Hz 195 220 ms

fe600 Hzb800 Hz 120 145 ms

fe800 Hzb1000 Hz 50 75 ms

fe1000 Hzb1600 Hz 20 40 ms

fe1600 Hzb2600 Hz 55 75 ms

fe2600 Hzb2800 Hz 80 105 ms

fe2800 Hzb3000 Hz 130 155 ms

DRA Receive Delay, Absolute fe1600 Hz 180 200 ms

DRR Receive Delay, Relative to DRA fe500 Hzb1000 Hz b40 b25 ms

fe1000 Hzb1600 Hz b30 b20 ms

fe1600 Hzb2600 Hz 70 90 ms

fe2600 Hzb2800 Hz 100 125 ms

fe2800 Hzb3000 Hz 145 175 ms

NOISE

NXC Transmit Noise, C Message TP3064 (Note 1) 12 15 dBrnC0

Weighted

NXP Transmit Noise, Psophometric TP3067 (Note 1) b74 b67 dBm0p

Weighted

NRC Receive Noise, C Message PCM Code Equals Alternating

Weighted Positive and Negative Zero

TP3064 8 11 dBrnCO

NRP Receive Noise, Psophometric PCM Code Equals Positive

Weighted Zero

TP3067 b82 b79 dBm0p

NRS Noise, Single Frequency fe0 kHz to 100 kHz, Loop Around b53 dBm0

Measurement, VFXIae0 Vrms

PPSRXPositive Power Supply Rejection, VCCe5.0 VDCa100 mVrms

Transmit fe0 kHzb50 kHz (Note 2) 40 dBC

NPSRXNegative Power Supply Rejection, VBBeb5.0 VDCa100 mVrms

Transmit fe0 kHzb50 kHz (Note 2) 40 dBC

PPSRRPositive Power Supply Rejection, PCM Code Equals Positive Zero

Receive VCCe5.0 VDCa100 mVrms

Measure VFRO

fe0Hz

4000 Hz 38 dBC

fe4 kHzb50 kHz 25 dB

NPSRRNegative Power Supply Rejection, PCM Code Equals Positive Zero

Receive VBBeb5.0 VDCa100 mVrms

Measure VFRO

fe0Hz

4000 Hz 40 dBC

fe4 kHzb25 kHz 40 dB

fe25 kHzb50 kHz 36 dB

SOS Spurious Out-of-Band Signals 0 dBm0, 300 Hzb3400 Hz Input

at the Channel Output PCM Code Applied at DR

Measure Individual Image Signals at

VFRO

4600 Hz– 7600 Hz b32 dB

7600 Hz– 8400 Hz b40 dB

8400 Hz– 100,000 Hz b32 dB

Transmission Characteristics (Continued)

Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC ea

5.0V g5%, VBB eb

5.0V g5%; TAe

0§Cto70

C by correlation with 100% electrical testing at TAe25§C. All other limits are assured by correlation with other

production tests and/or product design and characterization. GNDA e0V, f e1.02 kHz, VIN e0 dbm0, transmit input amplifier

connected for unity gain non-inverting. Typicals specified at VCC ea

5.0V, VBB eb

5.0V, TAe25§C.

Symbol Parameter Conditions Min Typ Max Units

DISTORTION

STDX, Signal to Total Distortion Sinusoidal Test Method (Note 3)

STDRTransmit or Receive Levele3.0 dBm0 33 dBC

Half-Channel e0 dBm0 to b30 dBm0 36 dBC

eb40 dBm0 XMT 29 dBC

RCV 30 dBC

eb55 dBm0 XMT 14 dBC

RCV 15 dBC

SFDXSingle Frequency Distortion, b46 dB

Transmit

SFDRSingle Frequency Distortion, b46 dB

Receive

IMD Intermodulation Distortion Loop Around Measurement, b41 dB

VFXIaeb4 dBm0 to b21 dBm0, Two

Frequencies in the Range

300 Hzb3400 Hz

CROSSTALK

CTX-R Transmit to Receive Crosstalk fe300 Hzb3000 Hz

DReQuiet PCM Code b90 b75 dB

CTR-X Receive to Transmit Crosstalk fe300 Hzb3000 Hz, VFXIe0V b90 b70 dB

(Note 2)

POWER AMPLIFIERS

VOPA Maximum 0 dBm0 Level Balanced Load, RLConnected Between

(Better than g0.1 dB Linearity over VPOaand VPOb.

the Range b10 dBm0 to a3 dBm0) RLe600X3.3 Vrms

RLe1200X3.5 Vrms

S/DPSignal/Distortion RLe600X50 dB

Note 1: Measured by extrapolation from the distortion test result at b50 dBm0.

Note 2: PPSRX, NPSRX, and CTRbXare measured with a b50 dBm0 activation signal applied to VFXIa.

Note 3: TP3064 is measured using C message weighted filter. TP3067 is measured using psophometric weighted filter.

Applications Information

POWER SUPPLIES

While the pins of the TP3060 family are well protected

against electrical misuse, it is recommended that the stan-

dard CMOS practice be followed, ensuring that ground is

connected to the device before any other connections are

made. In applications where the printed circuit board may be

plugged into a ‘‘hot’’ socket with power and clocks already

present, an extra long ground pin in the connector should

be used.

All ground connections to each device should meet at a

common point as close as possible to the GNDA pin. This

minimizes the interaction of ground return currents flowing

through a common bus impedance. 0.1 mF supply decou-

pling capacitors should be connected from this common

ground point to VCC and VBB, as close to the device as

possible.

For best performance, the ground point of each CODEC/

FILTER on a card should be connected to a common card

ground in ‘‘STAR’’ formation, rather than via a ground bus.

This common ground point should be decoupled to VCC and

VBB with 10 mF capacitors.

Note: See Application Note 370 for further details

Typical Asynchronous Application

TL/H/5070–5

Note 1: Transmit gain e20 clog #R1 aR2

R2 J,(R1 aR2) t10 kX

Note 2: Receive gain e20 clog #2cR3

R4 J,R4 t10 kX

FIGURE 4

Definitions and Timing Conventions

DEFINITIONS

VIH VIH is the d.c. input level above which

an input level is guaranteed to appear

as a logical one. This parameter is to

be measured by performing a

functional test at reduced clock

speeds and nominal timing, (i.e. not

minimum setup and hold times or

output strobes), with the high level of

all driving signals set to VIH and

maximum supply voltages applied to

the device

VIL VIL is the d.c. input level below which

an input level is guaranteed to appear

as a logical zero to the device. This

parameter is measured in the same

manner as VIH but with all driving

signal low levels set to VIL and

minimum supply voltages applied to

the device.

VOH VOH is the minimum d.c. output level

to which an output placed in a logical

one state will converge when loaded

at the maximum specified load current.

VOL VOL is the maximum d.c. output level

to which an output placed in a logical

zero state will converge when loaded

at the maximum specified load current.

Threshold Region The threshold region is the range of

input voltages between VIL and VIH.

Valid Signal A signal is Valid if it is in one of the

valid logic states, (i.e. above VIH or

below VIL). In timing specifiations, a

signal is deemed valid at the instant it

enters a valid state.

Invalid Signal A signal is Invalid if it is not in a valid

logic state, i.e. when it is in in the

threshold region between VIL and VIH.

In timing specifications, a signal is

deemed Invalid at the instant it enters

the threshold region.

TIMING CONVENTIONS

For the purposes of this timing specification, the following

conventions apply:

Input Signals All input signals may be characterized

as: VLe0.4V, VHe2.4V, tRk10 ns,

tFk10 ns.

Period The period of clock signal is

designated as tPxx where xx

represents the mnemonic of the clock

signal being specified.

Rise Time Rise times are designated as tRyy,

where yy represents a mnemonic of

the signal whose rise time is being

specified. tRyy is measured from VIL to

VIH.

Fall Time Fall times are designated as tFyy,

where yy represents a mnemonic of

the signal whose fall time is being

specified. tFyy is measured from VIH to

VIL.

Pulse Width High The high pulse width is designated as

tWzzH, where zz represents the

mnemonic of the input or output signal

whose pulse width is being specified.

High pulse widths are measured from

VIH to VIH.

Pulse Width Low The low pulse width is designated as

tWzzL, where zz represents the

mnemonic of the input or output signal

whose pulse width is being specified.

Low pulse widths are measured from

VIL to VIL.

Setup Time Setup times are designated as tSwwxx,

where ww represents the mnemonic of

the input signal whose setup time is

being specified relative to a clock or

strobe input represented by mnemonic

xx. Setup times are measured from the

ww Valid to xx Invalid.

Hold Time Hold times are designated as tHxxww,

where ww represents the mnemonic of

the input signal whose hold time is

being specified relative to a clock or

strobe input represented by mnemonic

xx. Hold times are measured from xx

Valid to ww Invalid.

Delay Time Delay times are designated as tDxxyy

Hi to Low, where xx represents the

mnemonic of the input reference

signal and yy represents the

mnemonic of the output signal whose

timing is being specified relative to xx.

The mnemonic may optionally be

terminated by an H or L to specify the

high going or low going transition of

the output signal. Maximum delay

times are measured from xx Valid to yy

Valid. Minimum delay times are

measured from xx Valid to yy Invalid.

This parameter is tested under the

load conditions specified in the

Conditions column of the Timing

Specifications section of this data

sheet.

Physical Dimensions inches (millimeters)

Cavity Dual-In-Line Package (J)

Order Number TP3064J or TP3067J

NS Package Number J20A

Molded Small Outline Package (WM)

Order Number TP3064WM or TP3067WM

NS Package Number M20B

Physical Dimensions inches (millimeters) (Continued)

Molded Dual-In-Line Package (N)

Order Number TP3064N or TP3067N

NS Package Number N20A

TP3064, TP3067 ‘‘Enhanced’’ Serial Interface CMOS CODEC/Filter COMBO

Physical Dimensions inches (millimeters) (Continued) Lit. Ý113975

Plastic Chip Carrier (V)

Order Number TP3064V or TP3067V

NS Package Number V20A

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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life

systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

National Semiconductor National Semiconductor National Semiconductor National Semiconductor

Corporation Europe Hong Kong Ltd. Japan Ltd.

1111 West Bardin Road Fax: (

49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309

Arlington, TX 76017 Email: cnjwge

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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