CY28446LFXC - Cypress Semiconductor

Clock Generator for Intel® Calistoga Chipset

CY28446

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 001-00168 Rev *D Revised April 03, 2006

Features

• Compliant to Intel® CK410M

• Selectable CPU frequencies

• Low power differential CPU clock pairs

• 100-MHz low power differential SRC clocks

• 96-MHz low power differential DOT clock

• 48-MHz USB clock

• SRC clocks stoppable through OE#

• 33-MHz PCI clocks

• Buffered 14.318-MHz reference clock

• Low-voltage frequency select input

•I

2C support with readback capabilities

• Ideal Lexmark Spread Spectrum profile for maximum

electromagnetic interferen ce (EMI) reduction

• 3.3V p ower supply

• 64-pin QFN package

Table 1. Output Configur ation table

CPU SRC PCI REF DOT96 48M

x2 / x3 x9/10 x5 x1 x 1 x 1

Pin Configuration

OE1#

FS_B/TEST_MODE

DOTC_96

DOTT_96

VDD_48

VSS_PCI

USB_48/FS_A

FS_C/TEST_SEL

VTTPWRGD#/PD

VSS_PCI

VDD_PCI

PCIF0/ITP_EN

PCI0

PCI1

PCI2

PCI3

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

VSS_48 1 48 VDD_PCI

SRCT0 2 47 REF

SRCC0 3 46 VSS_REF

OE0# 4 45 XIN

SRCT1 5 44 XOUT

SRCC1 6 43 VDD_REF

OEA# 7 42 SDATA

SRCT2 8 41 SCLK

SRCC2 9 40 CPU_STOP#

VDD_SRC 10 39 CPUT0

VSS_SRC 11 38 CPUC0

OE3# 12 37 VSS_CPU

SRCT3 13 36 VDD_CPU

SRCC3 14 35 CPUT1

OE6# 15 34 CPUC1

PCI_STOP# 16 33 VSS_SRC

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

VDD_SRC

SRCT5

SRCC5

SRCC6

SRCT6

SRCT8

SRCC8

OEB#

SRCC9

SRCT9

SRCT10

SRCC10

VDD_SRC

VSS_SRC

CPUC2_ITP/SRCC7

CPUT2_ITP/SRCT7

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Table 2. Frequenc y Table

FS_C FS_B FS_A CPU SRC/SATA PCIF/PCI REF LCD DOT96 USB

MID 0 1 100 100 33 14.318 100 96 48

0 0 1 133 100 33 14.318 100 96 48

0 1 1 166 100 33 14.318 100 96 48

0 1 0 200 100 33 14.318 100 96 48

00 0

MID 0 0

MID 1 0

MID 1 1 Reserved 100 33 14.318 100 96 48

1 0 x Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

1 1 0 REF/2 REF/8 REF/24 REF REF/8 REF REF

1 1 1 REF/2 REF/8 REF/24 REF REF/8 REF REF

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Document #: 001-00168 Rev *D Page 3 of 21

Pin Description

Pin No. Name Type Description

1 VSS_48 GND Ground for outputs.

2, 3, 5, 6, 8,

9, 13, 14, 18,

19, 20, 21,

22, 23, 25,

26, 27, 28

SRC(0:3, 5:6, 8:10)

[T/C] O, DIF 100-MHz Differential serial reference clocks

4, 7, 12, 15,

24, 64 OE[0, 1, 3, 6, A, B]# I, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW)

10, 17, 29, VDD_SRC PWR 3.3V power supply for outputs.

11, 30, 33 VSS_SRC GND Ground for outputs.

16 PCI_STP# I, PU 3.3V LVTTL input for PCI_STP#

Stops SRC and PCI clocks not set to free running in the SMBUS registers.

31, 32 CPU2_ITPT/SRCT7,

CPU2_ITPC/ SRCC7 O, DIF Select able differential CPU clock/100-MHz Differen tial serial reference clock.

Selectable via Pin 53 PCIF0/ITP_EN

34, 35, 38, 39 CPUT/C[0:1] O, DIF Differential CPU clock outputs.

36 VDD_CPU PWR 3.3V power supply for outputs.

37 VSS_CPU GND Ground for outputs.

40 CPU_STP# I, PU 3.3V LVTTL input for CPU_STP# active LOW.

41 SCLK I SMBus-compatible SCLOCK.

42 SDATA I/O,

OD SMBus-compatible SDATA.

43 VDD_REF PWR 3.3V power supply for outputs.

44 XOUT O, SE 14.318-MHz crystal output.

45 XIN I 14.318-MHz crystal input.

46 VSS_REF GND Ground for outputs.

47 REF O,SE Fixed 14.318-MH z clo ck output.

48, 54 VDD_PCI PWR 3.3V power supply for outputs.

49, 50, 51, 52 PCI[0:3] O, SE 33-MHz clock output

53 PCIF0/ITP_EN I/O, PD 33-MHz clock output (not stoppable by PCI_STOP#) / 3.3V LVTTL input for

selecting pins 31/3 2 (CPU2_ IT P[T/C]/SRC7[T/C]) (sampled on the

VTT_PWRGD# assertion).

0 (default): SRC7 [T/C]

1: CPU2_ITP[T/C]

55, 59 VSS_PCI GND Ground for outputs.

56 VTT_PWRGD#/PD I, PD 3.3V L VTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,

FS_C, and all I/O configuration pins,. After VTT_PWRGD# (active LOW) assertion,

this pin becomes a real-time input for asserting power-down (active HIGH).

57 FS_C/TEST_SEL I, PD 3.3V-tolerant input for CPU frequency selection/Selects test mode if pulled to

VIMFS_C when VTT_PWRGD# is asserted LOW.

Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifica-

tions.

58 USB_48/FS_A I/O, PU Fixed 48-MHz clock output / 3.3V -tolerant input for CPU frequency selection.

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

60 VDD_48 PWR 3.3V power supply for outputs.

61,62 DOT_96[T /C] O, DIF Fixed 96-M Hz c loc k outp ut .

63 FS_B/TEST_MODE I, PU 3.3V-tolerant input for CPU frequency selection Selects Ref/N or Tri-state

when in test mode

0 = T ri-state, 1 = Ref/N

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

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Document #: 001-00168 Rev *D Page 4 of 21

Frequency Select Pins (FS_A, FS_B, and FS_C)

Host clock frequency selection is achieved by applying the

appropriate logic level s to FS_A, FS_B, FS_C inputs prior to

VTT_PWRGD# assertion (as seen by the clock synthesizer).

Upon VTT_PWRGD# being sampled LOW by the clock chip

(indicating processor VTT voltage is stable), the clock chip

samples the FS_A, FS_B, and FS_C input values. For all logic

levels of FS_A, FS_B, and F S_C, VTT_PWRGD# employs a

one-shot functionality in that once a valid LOW on

VTT_PWRGD# has been sampled, all further VTT_PWRGD#,

FS_A, FS_B, and FSC transitions will be ignored, except in

test mode.

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer ,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers, can be individually enabled or disabled.

The registers associated with the Serial Data Interface

initialize to their de fault setting upon power-up, and therefore

use of this interface is optional. Clock device register changes

are normally made upon system initialization, if any are

required. The interface cannot be used during system

operation for power management functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller . For

block write/read operation, the bytes must be accessed in

sequential order from l owest to highest byte (most signifi cant

bit first) with the ability to stop after any complete byte has

been transferred. For byte write and byte read operations, the

system controller can access individually indexed bytes. The

offset of the indexed byte is encoded in the command code,

as described in Table 3.

The block write and block read protocol is outli ned in Table 4

while Table 5 outlines the corresponding byte write and byte

read protocol. The slave receiver address is 11010010 (D2h).

Table 3. Comman d Code De fi nition

Bit Description

7 0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be

'0000000'

Table 4. Block Read and Block Write Protocol

Block Write Protocol Block Read Protocol

Bit Description Bit Description

1 Start 1 Start

8:2 Slave address – 7 bits 8:2 Slave address – 7 bits

9 Write 9 Write

10 Acknowledge from slave 10 Acknowledge from slave

18:11 Command Code – 8 bits 18:11 Command Code – 8 bits

19 Acknowledge from slave 19 Acknowledge from slave

27:20 Byte Count – 8 bits

(Skip this step if I2C_EN bit set) 20 Repeat start

28 Acknowledge from slave 27:21 Slave address – 7 bits

36:29 Data byte 1 – 8 bits 28 Read = 1

37 Acknowledge from slave 29 Acknowledge from slave

45:38 Data byte 2 – 8 bits 37:30 Byte Count from slave – 8 bits

46 Acknowledge from slave 38 Acknowledge

.... Data Byte /Slave Acknowledges 46:39 Data byte 1 from slave – 8 bits

.... Data Byte N – 8 bits 47 Acknowledge

.... Acknowledge from slave 55:48 Data byte 2 from slave – 8 bits

.... Stop 56 Acknowledge

.... Data bytes from slave / Acknowledge

.... Data Byte N from slave – 8 bits

.... NOT Acknowledge

.... Stop

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Table 5. Byte Read and Byte Write Protocol

Byte Write Protocol Byte Read Protocol

Bit Description Bit Description

1Start 1Start

8:2 Slave address – 7 bits 8:2 Slave address – 7 bits

9Write 9Write

10 Acknowledge from slave 10 Acknowledge from slave

18:11 Command Code – 8 bits 18:11 Command Code – 8 bits

19 Acknowledge from slave 19 Acknowledge from slave

27:20 Data byte – 8 bits 20 Repeated start

28 Acknowledge from slave 27:21 Slave address – 7 bits

29 Stop 28 Read

29 Acknowledge from slave

37:30 Data from slave – 8 bits

38 NOT Acknowledge

39 Stop

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Control Registers

Byte 0: Control Register 0

Bit @Pup Name Description

7 1 CPU2_ITP[T/C]/SRC7[T/C] CPU2_ITP[T/C]/SRC[T/C]7 Output Enable

0 = Disable (Tri-state), 1 = Enable

6 1 SRC[T/C]6 SRC[T/C]6 Output Enable

0 = Disable (Tri-state), 1 = Enable

5 1 SRC[T/C]5 SRC[T/C]5 Output Enable

0 = Disable (Tri-state), 1 = Enable

4 1 Reserved Reserved

3 1 SRC[T/C]3 SRC[T/C]3 Output Enable

0 = Disable (Tri-state), 1 = Enable

2 1 SRC[T/C]2 SRC[T/C]2 Output Enable

0 = Disable (Tri-state), 1 = Enable

1 1 SRC[T/C]1 SRC[T/C]1 Output Enable

0 = Disable (Tri-state), 1 = Enable

0 1 SRC[T/C]0 SRC[T/C]0 Output Enable

0 = Disable (Tri-state), 1 = Enable

Byte 1: Control Register 1

Bit @Pup Name Description

7 1 PCIF0 PCIF0 Output Enable

0 = Disable, 1 = Enable

6 1 DOT_96[T/C] DOT_96 MHz Output Enable

0 = Disable (Tri-state), 1 = Enable

5 1 USB_48 USB_48 Output Enable

0 = Disable, 1 = Enable

4 1 REF REF Output Enable

0 = Disable, 1 = Enable

3 1 Reserved Reserved

2 1 CPU[T/C]1 CPU[T/C]1 Output Enable

0 = Disable (Tri-state), 1 = Enable

1 1 CPU[T/C]0 CPU[T/C]0 Output Enable

0 = Disable (Tri-state), 1 = Enable

0 0 CPU PLL Spread Enable PLL1 (CPU PLL) Spread Spectrum Enable

0 = Spread off

1 = Spread on (–0.5% spread spectrum on CPU/SRC/PCI clocks)

Byte 2: Control Register 2

Bit @Pup Name Description

7 1 Reserved Reserved set to 1

6 1 Reserved Reserved set to 1

5 1 PCI3 PCI3 Output Enable

0 = Disable, 1 = Enable

4 1 PCI2 PCI2 Output Enable

0 = Disable, 1 = Enable

3 1 PCI1 PCI1Output Enable

0 = Disable, 1 = Enable

2 1 PCI0 PCI0 Output Enable

0 = Disable, 1 = Enable

1 1 Reserved Reserved set to 1

0 1 Reserved Reserved set to 1

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Byte 3: Control Register 3

Bit @Pup Name Description

7 0 SRC7 Allow control of SRC[T/C]7 with assertion of OEB#

0 = Free running, 1 = Stopped with OEB#

6 0 Reserved Reserved set to 0

5 0 SRC5 Allow control of SRC[T/C]5 with assertion of OEB#

0 = Free running, 1 = Stopped with OEB#

4 0 Reserved Reserved set to 0

3 0 Reserved Reserved set to 0

2 0 SRC2 Allow control of SRC[T/C]2 with assertion of OEB#

0 = Free running, 1 = Stopped with OEB#

1 0 Reserved Reserved set to 0

0 0 Reserved Reserved set to 0

Byte 4: Control Register 4

Bit @Pup Name Description

7 1 Reserved Reserved set to 1

6 0 DOT96[T/C ] DOT PWRDWN Drive Mode

0 = Driven in PWRDWN, 1 = Tri-state

5 0 Reserved Reserved set to 0

4 1 Reserved Reserved set to 1

3 0 PCIF0 Allow control of PCIF0 with assertio n of SW and HW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

2 1 CPU[T/C]2 Allow control of CPU[T/C]2 with assertion of CPU_STP#

0 = Free running, 1 = St opped with CPU_STP#

1 1 CPU[T/C]1 Allow control of CPU[T/C]1 with assertion of CPU_STP#

0 = Free running, 1 = St opped with CPU_STP#

0 1 CPU[T/C]0 Allow control of CPU[T/C]0 with assertion of CPU_STP#

0 = Free running, 1 = St opped with CPU_STP#

Byte 5: Control Register 5

Bit @Pup Name Description

7 0 Reserved Reserved set to 0

6 0 CPU[T/C]2 CPU[T/C]2 Stop Drive Mode

0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP#

asserted

5 0 CPU[T/C]1 CPU[T/C]1 Stop Drive Mode

0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP#

asserted

4 0 CPU[T/C]0 CPU[T/C]0 Stop Drive Mode

0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP#

asserted

3 0 SRC[T/C] SRC[T/C] PWRDWN Drive Mode

0 = Driven when PD asserted, 1 = Tri-state when PD asserted

2 0 CPU[T/C]2 CPU[T/C]2 PWRDWN Drive Mode

0 = Driven when PD asserted, 1 = Tri-state when PD asserted

1 0 CPU[T/C]1 CPU[T/C]1 PWRDWN Drive Mode

0 = Driven when PD asserted, 1 = Tri-state when PD asserted

0 0 CPU[T/C]0 CPU[T/C]0 PWRDWN Drive Mode

0 = Driven when PD asserted, 1 = Tri-state when PD asserted

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Byte 6: Control Register 6

Bit @Pup Name Description

7 0 REF/N or Tri-state Select REF/N or Tri-state Select

1 = REF/N, 0 = Tri-state

6 0 Test Mode Test Mode Control

1 = Ref/N or T ristate, 0 = Normal Operation

5 1 Reserved Reserved set to 1

4 0 REF REF Output Drive Strength

0 = Low, 1 = High

3 1 PCI and PCIF clock

outputs except those set

to free running

SW PCI_STP Function

0 = SW PCI_STP assert, 1 = SW PCI_STP deassert

When this bit is set to 0, all STOPPABLE PCI and PCIF outputs will be

stopped in a synchronous manner with no sho rt pul ses.

When this bit is set to 1, all STOPPED PCI and PCIF outputs will resum e

in a synchronous manner with no short pulses.

2 HW FS_C FSC Reflects the value of the FS_C pin sampled on power-up

0 = FSC was low during VTT_PWRGD# assertion

1 HW FS_B FSB Reflects the value of the FS_B pin sampled on power-up

0 = FSB was low during VTT_PWRGD# assertion

0 HW F S_A FSA Reflects the value of the FS_A pin sampled on power-up

0 = FSA was low during VTT_PWRGD# assertion

Byte 7: Vendor ID

Bit @Pup Name Description

7 0 Revision Code Bit 3 Revision Code Bit 3

6 0 Revision Code Bit 2 Revision Code Bit 2

5 1 Revision Code Bit 1 Revision Code Bit 1

4 1 Revision Code Bit 0 Revision Code Bit 0

3 1 Vendor ID Bit 3 Vendor ID Bit 3

2 0 Vendor ID Bit 2 Vendor ID Bit 2

1 0 Vendor ID Bit 1 Vendor ID Bit 1

0 0 Vendor ID Bit 0 Vendor ID Bit 0

Byte 8: Control Register 7

Bit @Pup Name Description

7 0 Reserved Reserved set to 0

6 1 SRC[T/C]10 SRC[T/C]10 Output Enable

0 = Disable (Tri-state), 1 = Enable

5 1 SRC[T/C]9 SRC[T/C]9 Output Enable

0 = Disable (Tri-state), 1 = Enable

4 1 SRC[T/C]8 SRC[T/C]8 Output Enable

0 = Disable (Tri-state), 1 = Enable

3 0 Reserved Reserved set to 0

2 0 SRC10 Allow control of SRC[T/C]10 with assertion of OEA#

0 = Free running, 1 = Stopped with OEA#

1 0 SRC9 Allow control of SRC[T/C]9 with assertion of OEB#

0 = Free running, 1 = Stopped with OEB#

0 0 SRC8 Allow control of SRC[T/C]8 with assertion of OEA#

0 = Free running, 1 = Stopped with OEA#

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Document #: 001-00168 Rev *D Page 9 of 21

The CY28446 requires a Paral lel Resonance Crystal. Substi-

tuting a series resonance crystal will cause the CY28446 to

operate at the wrong frequency and violate the ppm specifi-

cation. For most applications there is a 300-ppm frequency

shift between series and parallel crystals due to incorrect

Crystal Loading

Crystal loading plays a critical role in achieving low ppm perfor-

mance. To realize low ppm performance, the total capacit ance

the crystal will see must be considered to calculate the appro-

priate capacitive loading (CL).

Figure 1 shows a typical crystal configuration using the two

trim capacitors. An important clarification for the following

discussion is that the trim capacitors are in series with the

crystal not parallel. It’s a common misconception that load

capacitors are in parallel with the crystal and should be

approximately equal to the load capacitance of the crystal.

This is not true.

Calculating Load Capacitors

In addition to the standard external trim capacitors, trace

capacitance and pin capacitance must also be considered to

correctly calculate crystal loading. As mentioned previously,

the capacitance on each side of the crystal is in series with the

crystal. This means the total capacitance on each side of the

crystal must be twice the specified crystal load capacitance

(CL). While the capacitance on each side of the crystal is in

series with the crystal, trim capacitors (Ce1,Ce2) should be

calculated to provide equal capaciti ve loading on both sides.

As mentioned previously, the capacitance on each side of the

crystal is in series with the crystal. This mean the tot al cap ac-

itance on each side of the crystal must be twice the specified

load capacitance (CL). While the capacitance on each side of

the crystal is in series with the crystal, trim capacitors

(Ce1,Ce2) should be calcula ted to provide equal capacitance

loading on both sides.

Byte 9: Control Register 8

Bit @Pup Name Description

7 0 PCI3 33-MHz Output drive strength

0 = Low, 1 = High

6 0 PCI2 33-MHz Output drive strength

0 = Low, 1 = High

5 0 PCI1 33-MHz Output drive strength

0 = Low, 1 = High

4 0 PCI0 33-MHz Output drive strength

0 = Low, 1 = High

3 0 PCIF0 33-MHz Output drive strength

0 = Low, 1 = High

2 1 Reserved Reserved set to 1

1 1 Reserved Reserved set to 1

0 1 Reserved Reserved set to 1

Crystal Recommendations

Frequency

(Fund) Cut Loading Load Cap Drive

(max.) Shunt Cap

(max.) Motional

(max.) Tolerance

(max.) Stability

(max.) Aging

(max.)

14.31818 MHz AT Parallel 20 pF 0.1 mW 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm

Figure 1. Crystal Cap acitive Clarification

XTAL

Ce2

Ce1

Cs1 Cs2

X1 X2

Ci1 Ci2

Clock Chip

Trace

2.8 pF

Trim

33 pF

3 to 6p

Figure 2. Crystal Loading Example

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Document #: 001-00168 Rev *D Page 10 of 21

Use the following formulas to calculate the trim capacitor

values for Ce1 and Ce2.

CL ...................................................Crystal load capacitance

CLe .........................................Actual loading seen by crystal

using standard value trim capacitors

Ce .....................................................External trim capacitors

Cs..............................................Stray capacitance (terraced)

Ci ...........................................................Internal capacitance

(lead frame, bond wires etc.)

OE# Description

The OE# signals are active LOW inputs used for clean

enabling and disabling selected SRC outputs. The outputs

controlled by OE[A,B]# are determined by the settings in

respectively. The OE# signal i s a debounced signa l in that its

state must remain unchanged during two consecutive rising

edges of SRCC to be recognized as a valid assertion or

deassertion. (The assertion and deassertion of this signal is

absolutely asynchronous.)

OE# Assertion (OE# -> LOW)

All differential outputs that were stopped are to resume normal

operation in a glitch-fre e manner. The maximum latency from

the assertion to active outputs is between 2 and 6 SRC clock

periods (2 clocks are shown) with all SRC outputs resuming

simultaneously . All stopped SRC outputs must be driven HIGH

within 10 ns of OE# deassertion to a voltage greater than

200 mV.

OE# Deassertion (OE# -> HIGH)

The impact of deasserting the OE# pins is that all SRC outputs

that are set in the control registers to stoppable via deassertion

of OE# are to be stopped a fter their next transition. The final

state of all stopped SRC clocks is Low/Low.

PD (Power-down) Clarification

The VTT_PWRGD# /PD pin is a dual-function pin. During

initial power-up, the pin functions as VTT_PWRGD#. Once

VTT_PWRGD# has been sampled LOW by the clock chip, the

pin assumes PD functionality. The PD pin is an asynchronous

active HIGH input used to shut off all clocks cleanly prior to

shutting off power to the device. This signal is synchronized

internal to the device prior to powering down the clock synthe-

sizer. PD is also an asynchronous input for powering up the

system. When PD is asserted HIGH, all clocks need to be

driven to a low value and held prior to turning off the VCOs and

the crystal oscillator.

PD (Power-down) Asser tio n

When PD is sampled HIGH by two consecutive rising edges

of CPUC, all single-ended outputs will be held LOW on their

next HIGH-to-LOW transition and dif ferential clocks must held

HIGH or tri-stated (depending on the state of the control

transition within 4 clock periods. When the SMBus PD drive

mode bit corresponding to the differential (CPU, SRC, and

DOT) clock output of interest is progra mmed to ‘0’, the clock

output are held with “Diff clock” pin driven HIGH and “Diff

clock#” driven LOW. If th e control register PD drive mode bit

corresponding to the output of interest is progra mmed to “1”,

then both the “Diff clock” and the “Diff clock#” are LOW. Note

Figure 4 shows CPUT = 133 MHz and PD drive mode = ‘1’ for

all differential outputs. This diagram and description is appli-

cable to valid CPU frequenci es 100, 1 33, 166, and 200 MHz.

In the event that PD mode is desired as the initial power-on

state, PD must be asserted HIGH in less than 10 µs after

asserting Vtt_PwrGd#. It should be noted that 96_100_SSC

will follow the DOT wavefo rm is selected for 96 MHz and the

SRC waveform when in 100-MHz mode.

Load Capacitan ce (each side)

Total Capacitance (as seen by the crystal)

Ce = 2 * CL – (Cs + Ci)

Ce1 + Cs1 + Ci1

1+Ce2 + Cs2 + Ci2

()

CLe

Figure 3. OE# Deassertion/Assertion Waveform

SRCT(stoppable)

SRCC(free running)

SRCT(free running)

OE#

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Document #: 001-00168 Rev *D Page 11 of 21

PD Deassertion

The power-up latency is less than 1.8 ms. This is the time from

the deassertion of the PD pin or the ramping of the power

supply until the time that stable clocks are output from the

clock chip. All differential outputs stopped in a three-state

condition resulting from power-down will be driven HIGH in

less than 300 µs of PD deassertion to a voltage greater than

200 mV. After the clock chip’s internal PLL is powered up and

locked, all outputs will be enabled within a few clock cycles of

each other . Figure 5 is an example showing the relationship of

clocks coming up. It should be noted that 96_100_SSC will

follow the DOT waveform is selected for 96 MHz and the SRC

waveform when in 100-MHz mode.

Figure 4. Power-down Assertion Timing Waveform

USB, 48MHz

DOT96T

DOT96C

SR CT 100MHz

SRCC 100MHz

CPUT, 133MHz

PCI, 33 MHz

REF

CP UC , 133MHz

Figure 5. Power-down Deassertion Timing Waveform

DOT96C

CPUC, 133MHz

CPUT, 133MHz

SRCC 100MHz

USB, 48MH z

DOT96T

SRCT 100MH z

Tstable

<1.8 ms

PCI, 33MHz

REF Tdrive_PWRDN#

<300 µσ, >200 mV

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Document #: 001-00168 Rev *D Page 12 of 21

CPU_STP# Assertion

The CPU_STP# signal is an active LOW input used for

synchronous stopping and starting the CPU output clocks

while the rest of the clock generator continues to function.

When the CPU_STP# pin is asserted, all CPU outputs that are

set with the SMBus configurat ion to be stoppable via assertion

of CPU_STP# will be stopped within two to six CPU clock

periods after being sampled by two rising edges of the internal

CPUC clock. The final state of all stopped CPU clocks is

High/Low when driven, Low/Low when tri-stated

CPU_STP# Deassertion

The deassertion of the CPU_ STP# signal will cause all CPU

outputs that were stopped to resume normal operation in a

synchronous manner, synchronous manner meaning that no

short or stretched clock pulses will be produce when the clock

resumes. The maximum latency from the deassertion to active

outputs is no more than two CPU clock cycles.

CPU_STP#

CPUT

CPUC

CP U T Inte rnal

Tdrive_CPU_STP#,10 ns > 200 mV

CP U C Inte rna l

Figure 6. CPU_STP# Deassertion Waveform

DOT96C

DOT96T

CPUC(Stoppable)

CPUT(Stoppable)

CP UC (Free Running

CPUT(Free Running

1.8 m s

CPU_STOP#

Figure 7. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven

CPU_STP#

CPUT

CPUC

Figure 8. CPU_STP# Assertion Waveform

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PCI_STP# Assertion

The PCI_STP# signal is an active LOW input used for

synchronous stopping and starting the PCI outputs while the

rest of the clock generator continues to function. The set-up

time for capturing PCI_STP# goi ng LOW is 10 ns (tSU). (See

Figure 10.) The PCIF clocks will not be affected by this pin if

their corresponding control bit in the SMBus re gister is set to

allow them to be free running.

PCI_STP# Deassertion

The deassertion of the PCI_STP# signal will cause all PCI and

stoppable PCIF clocks to resume running in a synchronous

manner within two PCI clock periods after PCI_STP# transi-

tions to a high level.

DOT96C

DOT96T

CPUC(Stoppable)

CPUT(Stoppable)

CPUC(Free Running)

CPUT(Free Running)

1.8mS

CPU_STOP#

Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state

Tsu

PCI_STP#

PCI_F

PCI

SRC 100MHz

Figure 10. PCI_STP# Assertion Waveform

PCI_STP#

PCI_F

PCI

SRC 100MHz

Tsu Tdrive_SRC

Figure 11. PCI_STP# Deassertion Waveform

CY28446

Document #: 001-00168 Rev *D Page 14 of 21

FS_A, FS_B,FS_C

VTT_PWRGD#

PWRGD_VRM

VDD C lock Gen

Clock State

Clock Outputs

Clock VCO

0.2-0.3mS

Delay

State 0 State 2 State 3

Wait for

VTT_PWRGD# S ample Sels

Off

State 1

Device is not aff ect ed,

VT T_P WR G D # is ignored

Figure 12. VTT_PWRGD# Timing Diagram

VTT_PWRGD # = Low

Delay

>0.25mS

Power Off

VDD_A = 2.0V

Sample

Inputs straps

Normal

Operation

W a it fo r <1 .8 m s

Enable Outputs

VTT_PWRGD # = toggle

VDD_A = off

Figure 13. Clock Generator Power-up/Run State Diagram

CY28446

Document #: 001-00168 Rev *D Page 15 of 21

Absolute Maximum Conditions

Parameter Description Condition Min. Max. Unit

VDD Core Supply Voltage –0.5 4.6 V

VDD_A Analog Supply Voltage –0.5 4.6 V

VIN Input Voltage Relative to VSS –0.5 VDD + 0.5 VDC

TSTemperature, Storage Non-functional –65 150 °C

TATemperature, Operating Ambient Functional 0 85 °C

TJTemperature, Junction Functional – 150 °C

ØJC Dissipation, Junction to Case Mil-STD-883E Method 1012.1 – 20 °C/W

ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/W

ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V

UL-94 Flammabi lity Rating At 1/8 in. V–0

MSL Moisture Sensi ti vity Leve l 1

Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power -up. Power supply sequencing is NOT required.

DC Electrical Specifications

Parameter Description Condition Min. Max. Unit

All VDDs 3.3V Operating V oltage 3.3 ± 5% 3.135 3.465 V

VILI2C Input Low Voltage SDATA, SCLK – 1.0 V

VIHI2C Input High Voltage SDATA, SCLK 2.2 – V

VIL_FS FS_[A,B] Input Low Voltage VSS – 0.3 0.35 V

VIH_FS FS_[A,B] Input High Voltage 0.7 V DD + 0.5 V

VILFS_C FS_C Input Low Voltage VSS – 0.3 0.35 V

VIMFS_C FS_C Input Middle Vo ltage Typical 0.7 1.7 V

VIHFS_C FS_C Input High Voltage Typical 2.0 VDD + 0.5 V

VIL 3.3V Input Low Voltage VSS – 0.3 0.8 V

VIH 3.3V Input High Voltage 2.0 VDD + 0.3 V

IIL Input Low Leakage Current Except internal pull-up resistors, 0 < VIN

< VDD –5 5 µA

IIH Input High Leakage Current Except internal pull-down resistors, 0 <

VIN < VDD –5µA

VOL 3.3V Output Low Voltage IOL = 1 mA – 0.4 V

VOH 3.3V Output High Voltage IOH = –1 mA 2.4 – V

IOZ High-impedance Output Current –10 10 µA

CIN Input Pin Ca pacitance 3 5 pF

COUT Output Pin Capacitance 3 6 pF

LIN Pin Inductance – 7 nH

VXIH Xin High Voltage 0.7VDD VDD V

VXIL Xin Low Voltage 0 0.3VDD V

IDD3.3V Dynamic Supply Current At max. load and freq. per Figure 15 – 250 mA

IPD3.3V Power-down Supply Curre nt PD asserted, Outputs Driven – 70 mA

IPD3.3V Power-down Supply Current PD asserted, Outputs Tri-state – 5 mA

CY28446

Document #: 001-00168 Rev *D Page 16 of 21

AC Electrical Specifications

Parameter Description Condition Min. Max. Unit

Crystal

TDC XIN Duty Cycle The device will operate reliably with input

duty cycles up to 30/70 but the REF clock

duty cycle will not be within specification

47.5 52.5 %

TPERIOD XIN Period When XIN is driven from an external

clock source 69.841 71.0 ns

TR / TFXIN Rise and Fall Times Measured between 0.3VDD and 0.7VDD –10.0ns

TCCJ XIN Cycle to Cycle Jitter As an average over 1-µs duration – 500 ps

LACC Long-term Accuracy Measured at crossing point VOX –300ppm

CPU at 0.8V

TDC CPUT and CPUC Duty Cycle Measured at crossing point VOX 45 55 %

TPERIOD 100-MHz CPUT and CPUC Period Measured at crossing point VOX 9.997001 10.00300 ns

TPERIOD 133-MHz CPUT and CPUC Period Measured at crossing point VOX 7.497751 7.502251 ns

TPERIOD 166-MHz CPUT and CPUC Period Measured at crossing point VOX 5.998201 6.001801 ns

TPERIOD 200-MHz CPUT and CPUC Period Measured at crossing point VOX 4.998500 5.001500 ns

TPERIODSS 100-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 9.997001 10.05327 ns

TPERIODSS 133-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 7.497751 7.539950 ns

TPERIODSS 166-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 5.998201 6.031960 ns

TPERIODSS 200-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 4.998500 5.026634 ns

TPERIODAbs 100-MHz CPUT and CPUC Absolute

period Measured at crossing point VOX 9.912001 10.08800 ns

TPERIODAbs 133-MHz CPUT and CPUC Absolute

period Measured at crossing point VOX 7.412751 7.587251 ns

TPERIODAbs 166-MHz CPUT and CPUC Absolute

period Measured at crossing point VOX 5.913201 6.086801 ns

TPERIODAbs 200-MHz CPUT and CPUC Absolute

period Measured at crossing point VOX 4.913500 5.086500 ns

TPERIODSSAbs 100-MHz CPUT and CPUC Absolute

period, SSC Measured at crossing point VOX 9.912001 10.13827 ns

TPERIODSSAbs 133-MHz CPUT and CPUC Absolute

period, SSC Measured at crossing point VOX 7.412751 7.624950 ns

TPERIODSSAbs 166-MHz CPUT and CPUC Absolute

period, SSC Measured at crossing point VOX 5.913201 6.116960 ns

TPERIODSSAbs 200-MHz CPUT and CPUC Absolute

period, SSC Measured at crossing point VOX 4.913500 5.111634 ns

TCCJ CPUT/C Cycle to Cycle Jitter Measured at crossing point VOX –85

[1] ps

TCCJ2 CPU2_ITP Cycle to Cycle Jitter Measured at crossing point VOX –125ps

LACC Long-term Accuracy Measured at crossing point VOX –300ppm

TSKEW2 CPU2_ITP to CPU0 Clock Skew Measured at crossing point VOX –150ps

TR / TFCPUT and CPUC Rise and Fall Time Measur ed from VOL = 0.175 to

VOH = 0.525V 175[1] 700 ps

TRFM Rise/Fall Matching Determined as a fraction of

2*(TR – TF)/(TR + TF)–20%

∆TRRise Time Variation – 125 ps

∆TFFall Time Variation – 125 ps

VHIGH Voltage High Math averages Figure 15 660 850 mV

Note:

1. Measured at typical condition. VDD = 3.3V, Temp=25°C.

CY28446

Document #: 001-00168 Rev *D Page 17 of 21

VLOW Voltage Low Math averages Figure 15 –150 – mV

VOX Crossing Point Voltage at 0.7V Swing 250[1] 550 mV

VOVS Maximum Overshoot Voltage – VHIGH +

0.3 V

VUDS Minimum Undershoot Voltage –0.3 – V

VRB Ring Back Voltage See Figure 15. Measure SE – 0.2 V

SRC at 0.8V

TDC SRCT and SRCC Duty Cycle Measu r ed at crossing poi nt VOX 45 55 %

TPERIOD 100-MHz SRCT and SRCC Period Measured at crossing point VOX 9.997001 10.00300 ns

TPERIODSS 100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX 9.997001 10.05327 ns

TPERIODAbs 100-MHz SRCT and SRCC Absolute

Period Measured at crossing point VOX 9.872001 10.12800 ns

TPERIODSSAbs 100-MHz SRCT and SRCC Absolute

Period, SSC Measured at crossing point VOX 9.872001 10.17827 ns

TSKEW Any SRCT/C to SRCT/C Clock Skew Measured at crossing point VOX –100ps

TCCJ SRCT/C Cycle to Cycle Jitter Measured at crossing point VOX –125ps

LACC SRCT/C Long Term Accuracy Measured at crossing point VOX –300ppm

TR / TFSRCT and SRCC Rise and Fall Time Measured fro m VOL = 0.175 to

VOH = 0.525V 175[1] 700[1] ps

TRFM Rise/Fall Matching Determined as a fraction of

2*(TR – TF)/(TR + TF)–20%

∆TRRise TimeVariation – 125 ps

∆TFFall Time Variation – 125 ps

VHIGH Voltage High Math averages Figure 15 660 850 mV

VLOW Voltage Low Math averages Figure 15 –150 – mV

VOX Crossing Point Voltage at 0.7V Swing 250 550 mV

VOVS Maximum Overshoot Voltage – VHIGH +

0.3 V

VUDS Minimum Undershoot Voltage –0.3 – V

VRB Ring Back Voltage See Figure 15. Measure SE – 0.2 V

DOT96 at 0.7V

TDC DOT96T and DOT96C Duty Cycle Measured at crossing point VOX 45 55 %

TPERIOD DOT96T and DOT96C Period Measured at crossing point VOX 10.41354 10.41979 ns

TPERIODAbs DOT96T and DOT96C Absolute Period Measured at crossing point VOX 10.16354 10.66979 ns

TCCJ DOT96T/C Cycle to Cycle Jitter Measured at crossing point VOX –250ps

LACC DOT96T/C Long Term Accuracy Measured at crossing point VOX –300ppm

TR / TFDOT96T and DOT96C Rise and Fall

Time Measured from VOL = 0.175 to

VOH = 0.525V 175 [1] 700 ps

TRFM Rise/Fall Matching Determined as a fraction of

2*(TR – TF)/(TR + TF)–20%

∆TRRise Time Variation – 125 ps

∆TFFall Time Variation – 125 ps

VHIGH Voltage High Math averages Figure 15 660 850 mV

VLOW Voltage Low Math averages Figure 15 –150 – mV

VOX Crossing Point Voltage at 0.7V Swing 250 550 mV

AC Electrical Specifications (continued)

Parameter Description Condition Min. Max. Unit

CY28446

Document #: 001-00168 Rev *D Page 18 of 21

VOVS Maximum Overshoot Voltage – VHIGH +

0.3 V

VUDS Minimum Undershoot Voltage –0.3 – V

VRB Ring Back Voltage See Figure 15. Measure SE – 0.2 V

PCI/PCIF at 3.3V

TDC PCI Duty Cycle Measurement at 1.5V 45 55 %

TPERIOD Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.99100 30.00900 ns

TPERIODSS Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V 29.9910 30.15980 ns

TPERIODAbs Spread Disable d PCIF/PCI Period Measurement at 1.5V 29.49100 30.50900 ns

TPERIODSSAbs Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V 29.49100 30.65980 ns

THIGH PCIF and PCI high time Measurement at 2.4V 12.0 – ns

TLOW PCIF and PCI low time Measurement at 0.4V 12.0 – ns

TR / TFPCIF/PCI rising and falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns

TSKEW Any PCI clock to Any PCI clock Skew Measurement at 1.5V – 500 ps

TCCJ PCIF and PCI Cycle to Cycle Jitter Measurement at 1.5V – 500 ps

LACC PCIF/PCI Long Term Accuracy Measured at crossing point VOX –300ppm

48_M at 3.3V

TDC Duty Cycle Measurement at 1.5V 45 55 %

TPERIOD Period Measurement at 1.5V 20.83125 20.83542 ns

TPERIODAbs Absolute Period Measurement at 1.5V 20.48125 21.18542 ns

THIGH 48_M High time Measurement at 2.4V 8.09 11.3 ns

TLOW 48_M Low time Measurement at 0.4V 7.694 11.3 ns

TR / TFRising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns

TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 350 ps

LACC 48M Long Term Accuracy Measured at crossing point VOX –300ppm

REF at 3.3V

TDC REF Duty Cycle Measurement at 1.5V 45 55 %

TPERIOD REF Period Measurement at 1.5V 69.8203 69.8622 ns

TPERIODAbs REF Absolute Period Measurement at 1.5V 68.82033 70.86224 ns

TR / TFREF Rising and Falling Edge Rate Measured betwee n 0.8V and 2.0V 1.0 4.0 V/n s

TSKEW REF Clock to REF Clock Measurement at 1.5V – 500 ps

TCCJ REF Cycle to Cycle Jitter Measurement at 1.5V – 1000 ps

LACC Long Term Accuracy Measurement at 1.5V – 300 ppm

ENABLE/DISABLE and SET-UP

TSTABLE Clock Stabilization from Power-up – 1.8 ms

TSS Stopclock Set-up Time 10.0 – ns

TSH Stopclock Hold Time 0 – ns

AC Electrical Specifications (continued)

Parameter Description Condition Min. Max. Unit

CY28446

Document #: 001-00168 Rev *D Page 19 of 21

Test and Measurement Set-up

For PCI Single-ended Signals and Reference

The following diagram shows the test load configuration of

single-ended PCI, USB output signals.

The following diagram shows the test load configuration for the

differential CPU and SRC outputs.

Figure 14. Single-ended PCI, USB Load Con fi guration

33Ω

5 pF

Figure 15. 0.7V Differential Load Configuration

CPUT

SRCT

DOT96T

TPCB

CPUC

SRCC

DTO96C

33Ω

L1 L2

100 ohm Differential

2 pF

Measurem ent

point

Measurement

point

2.0V

0.8V

3.3V

TR TF

1.5V

3.3V sig nals

TDC

- -

Figure 16. Single-en de d Ou tpu t Sign als (for AC Parameters Measur ement)

Ordering Information

Part Number Package Type Product Flow

Lead-free

CY28446LFXC 64-pin QFN Commercial, 0° to 70°C

CY28446LFXCT 64-pin QFN—Tape and Reel Commercial, 0° to 70°C

CY28446

Document #: 001-00168 Rev *D Page 20 of 21

© Cypress Semi con duct or Cor po rati on , 20 06 . The information con tained herei n is su bject to change wit hou t n oti ce. C ypr ess S em icon duct or Corpo ration assu mes no resp onsib ility for th e us e

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cyp ress does not a uthorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Package Diagram

Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips

I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard S pecification

as defined by Philips.

Intel is a registered trademark of Inte l Corporation. All products and company names mentioned in this documen t may be the

trademarks of their respective holders.

PIN1 ID

0.80 DIA. 3

PLANE

SEATING

0.20[0.008] REF.

0.05[0.002] MAX.

0.80[0.031] MAX.

1.00[0.039] MAX.

C0.08[0.003]

0.20[0.008] R.

9.10[0.358]

8.90[0.350]

8.80[0.346]

8.70[0.342]

8.80[0.346]

8.70[0.342]

9.10[0.358]

8.90[0.350]

0°-12°

0.28[0.011]

0.18[0.007]

0.30[0.012]

0.50[0.020]

7.55[0.297]

7.45[0.293]

0.45[0.018]

0.60[0.024]

0.24[0.009] (4X)

BY DEVICE TYPE)

(PAD SIZE VARY

E-PAD

TOP VIEW

SIDE VIEW

BOTTOM VIEW

DIMENSIONS IN MM[INCHES] MIN.

MAX.

REFERENCE JEDEC MO-220

WEIGHT: 0.2 GRAMS

51-85215-**

64-Lead QFN 9 x 9 mm (Punch Version) LF64A

CY28446

Document #: 001-00168 Rev *D Page 21 of 21

Document History Page

Document Title: CY28446 Clock Generator for Intel® Calistoga Chipset

Document Number: 001-00168

REV. ECN NO. Issue Date Orig. of

Change Description of Change

** 366781 See ECN RGL New data sheet

*A 385257 See ECN RGL Modify Control register byte 4 and 6

Delete 96_100MHz LCD clock AC timing spec from AC Electrical specifications

table

Modify figure 15 for lower differential buffer

Change pin 33 from IREF to VSS_SRC

Update IDD, IPD number in DC Electrical Specifications table

Updated single-ended PCI, USB loading config. diagram

*B 391184 See ECN RGL Minor Change: corrected the letter suffix for QFN package

*C 402318 See ECN XLZ Modify Control register byte 6, 7, 9

Update DC and AC Electrical Specifications table

*D 436731 See ECN RGL Updated Control register bytes 0,1 and 7

Updated AC Electrical Specifications table

Removed preliminary status