FN7646 Rev 1.00 Page 1 of 29
November 17, 2011
FN7646
Rev 1.00
November 17, 2011
ISLA112P25M
Low Power 12-Bit, 250MSPS ADC
DATASHEET
The ISLA112P25MREP is a low-power 12-bit, 250MSPS
analog-to-digital converter. Designed with Intersil’ s
proprietary Fem toCharge™ technology on a standard
CMOS process.
A serial peripheral interface (SPI) port allows for
extensive configurabili ty, as well as fine control of
various parameters such as gain and offset.
Digital output data is presented in sel ectable LVDS or
CMOS formats. The ISLA112P25MREP is avail able in a
72 Ld QFN package with an exposed paddle. Operating
from a 1.8V supply, performance is specified over the
full military temperature r ange (-55°C to +125°C).
Applications
• Power Amplifier Linearization
• Radar and Satellite Antenna Array Processing
• Broadband Communications
• High-Pe rformance Data Acquisition
• Communications Test Equipment
Key Specifications
• SNR = 62.7dBFS for fIN = 105MHz (-1dBFS)
•SFDR = 67dBc for f
IN = 105MHz (-1dBFS)
• Total Power Consumption
- 310mW @ 250MSPS (SDR Mode)
- 234mW @ 250MSPS (DDR Mode)
Features
• Programmable Gain, Offset and Skew Control
• 1.3GHz Analog Input Bandwidth
• 60fs Clock Jitter
•Over-Range Indicator
• Selectable Clock Divider: 1, 2 or 4
• Clock Phase Selection
• Nap and Sleep Modes
• Two’s Complement, Gray Code or Binary Data
Format
• SDR/DDR LVDS-Compatible or LVCMOS Outputs
• Programmable Built-in Test Patterns
• Single-Supply 1.8V Operation
• Pb-Free (RoHS Compliant)
VID Features
• Specifications per DSCC VID V62/10609
• Full Military Temperature Electrical Performance
from -55°C to +125°C
• Controlled Baseline with One Wafer Fabrication Site
and One Assembly/Test Site
• Full Homogeneous Lot Processing in Wafer Fab
• No Combination of W afer Fabrication Lots in
Assembly
• Full Traceability Through Assembly and Test by
• Date/Trace Code Assignment
• Enhanced Process Change Notification
• Enhanced Obsolescence Management
• Eliminates Need for Up-Screening a CO TS
Component
Block Diagram
DIGITAL
ERROR
CORRECTION
LVDS/CMOS
DRIVERS
1.25V
CLOCK
GENERATION
SHA
VINP
VINN
12-BIT
250 MSPS
ADC
CLKP
CLKN
SPI
CONTROL
CSB
SCLK
SDIO
OVSS
AVSS AVDD
CLKOUTP
CLKOUTN
D[11:0]P
D[11:0]N
ORP
ORN
OUTFMT
OUTMODE
OVDD
SDO
NAPSLP
CLKDIV
+
–
VCM
ISLA112P25M
FN7646 Rev 1.00 Page 2 of 29
November 17, 2011
Pin Configuration
ISLA112P25MREP
(72 LD QFN)
TOP VIEW
Pin Descriptions
PIN
NUMBER LVDS [LVCMOS]
NAME LVDS [LVCMOS] FUNCTION
SDR MODE DDR MODE
COMMENTS
1, 6, 12, 19,
24, 71 AVDD 1.8V Analog Supply
2, 3, 4, 5, 13,
14, 17, 18, 28,
29, 30, 31
DNC Do Not Conn ect
7, 8, 11, 72 AVSS Analog Ground
9, 10 VINN, VINP Analog Input Negative, Positive
15 VCM Common Mode Output
16 CLKDIV Tri-Level Clock Divider Control
AVSS
AVDD
OUTFMT
SDIO
72 71 70 69 68 67 66 65 64 63 62 61
SCLK
CSB
SDO
OVSS
ORP
ORN
D11P
D11N
60 59
D10P
D10N
D8P
D8N
D7P
D7N
D6P
D6N
CLKOUTP
CLKOUTN
RLVDS
OVSS
D5P
D5N
D4P
D4N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
54
53
52
51
50
49
48
47
46
45
44
43
42
41
AVDD
DNC
DNC
DNC
DNC
AVDD
AVSS
AVSS
VINN
VINP
AVSS
AVDD
DNC
DNC
19 20 21 22 23 24 25 26 27 28 29 30 31 32
AVDD
CLKP
CLKN
OUTMODE
NAPSLP
AVDD
RESETN
OVSS
OVDD
DNC
DNC
DNC
DNC
D0N
15
16
17
18
VCM
CLKDIV
DNC
DNC
33 34 35 36
D0P
D1N
D1P
OVDD
D3P
D3N
D2P
D2N
40
39
38
37
58 57
D9P
D9N
56 55
OVDD
OVSS
Connect Thermal Pad to AVSS
ISLA112P25M
FN7646 Rev 1.00 Page 3 of 29
November 17, 2011
20, 21 CLKP, CLKN Clock Input True, Complement
22 OUTMODE Tri-Level Output Mode Control (LVDS, LVCMOS)
23 NAPSLP Tri-Level Power Control (N ap, Sleep modes)
25 RESETN Power On Reset (Active Low, see page 15)
26, 45, 55, 65 OVSS Output Ground
27, 36, 56 OVDD 1.8V Output Supply
32 D0N
[NC] LVDS Bit 0 (LSB) Output Compl ement
[NC in LVCMOS] DDR Logical Bits 1, 0 (LVDS)
33 D0P
[D0] LVDS Bit 0 (LSB) Output True
[LVCMOS Bit 0] DDR Logical Bits 1, 0 (LVDS or CMOS)
34 D1N
[NC] LVDS Bit 1 Output Complement
[NC in LVCMOS] NC in DDR
35 D1P
[D1] LVDS Bit 1 Output True
[LVCMOS Bit 1] NC in DDR
37 D2N
[NC] LVDS Bit 2 Output Complement
[NC in LVCMOS] DDR Logical Bits 3,2 (LVDS)
38 D2P
[D2] LVDS Bit 2 Output True
[LVCMOS Bit 2] DDR Logical Bits 3,2 (LVDS or CMOS)
39 D3N
[NC] LVDS Bit 3 Output Complement
[NC in LVCMOS] NC in DDR
40 D3P
[D3] LVDS Bit 3 Output True
[LVCMOS Bit 3] NC in DDR
41 D4N
[NC] LVDS Bit 4 Output Complement
[NC in LVCMOS] DDR Logical Bits 5,4 (LVDS)
42 D4P
[D4] LVDS Bit 4 Output True
[LVCMOS Bit 4] DDR Logical Bits 5,4 (LVDS or CMOS)
43 D5N
[NC] LVDS Bit 5 Output Complement
[NC in LVCMOS] NC in DDR
44 D5P
[D5] LVDS Bit 5 Output True
[LVCMOS Bit 5] NC in DDR
46 RLVDS LVDS Bias Resistor
(Connect to OVSS with a 10k, 1% resistor)
47 CLKOUTN
[NC] LVDS Clock Output Complement
[NC in LVCMOS]
48 CLKOUTP
[CLKOUT] LVDS Clock Output True
[LVCMO S CLKOUT ]
49 D6N
[NC] LVDS Bit 6 Output Complement
[NC in LVCMOS] DDR Logical Bits 7,6 (LVDS)
50 D6P
[D6] LVDS Bit 6 Output True
[LVCMOS Bit 6] DDR Logical Bits 7,6 (LVDS or CMOS)
51 D7N
[NC] LVDS Bit 7 Output Complement
[NC in LVCMOS] NC in DDR
52 D7P
[D7] LVDS Bit 7 Output True
[LVCMOS Bit 7] NC in DDR
53 D8N
[NC] LVDS Bit 8 Output Complement
[NC in LVCMOS] DDR Logical Bits 9,8 (LVDS)
Pin Descriptions (Continued)
PIN
NUMBER LVDS [LVCMOS]
NAME LVDS [LVCMOS] FUNCTION
SDR MODE DDR MODE
COMMENTS
ISLA112P25M
FN7646 Rev 1.00 Page 4 of 29
November 17, 2011
54 D8P
[D8] LVDS Bit 8 Output True
[LVCMOS Bit 8] DDR Logical Bits 9,8 (LVDS or CMOS)
57 D9N
[NC] LVDS Bit 9 Output Complement
[NC in LVCMOS] NC in DDR
58 D9P
[D9] LVDS Bit 9 Output True
[LVCMOS Bit 9] NC in DDR
59 D10N
[NC] LVDS Bit 1 0 Output Complement
[NC in LVCMOS] DDR Logical Bits 11,10 (LVDS)
60 D10P
[D10] LV DS Bit 10 Output Tr ue
[LVCMOS Bit 10] DDR Logical Bits 11,10 (LVDS or CMOS)
61 D11N
[NC] LVDS Bit 1 1 Output Complement
[NC in LVCMOS] NC in DDR
62 D11P
[D11] LV DS Bit 11 Output Tr ue
[LVCMOS Bit 11] NC in DDR
63 ORN
[NC] LVDS Over Range Complement
[NC in LVCMOS]
64 ORP
[OR] LVDS Over Range True
[LVCMOS Over Range]
66 SDO SPI Serial Data Output
(4.7k pull-up to OVDD is required)
67 CSB SPI Chip Select (active low)
68 SCLK SPI Clock
69 SDIO SPI Serial Data Input/Output
70 OUTFMT Tri-Level Output Data Format Control (Two’s
Comp., Gray Code, Offset Binary)
Exposed Paddle A VSS Analog Ground
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection). SDR is the default state at power-up for
the 72 Ld package.
Pin Descriptions (Continued)
PIN
NUMBER LVDS [LVCMOS]
NAME LVDS [LVCMOS] FUNCTION
SDR MODE DDR MODE
COMMENTS
Ordering Information
PART NUMBER PART MARKING SPEED
(MSPS) TEMP. RANGE
(°C) PACKAGE
(Pb-Free) PKG.
DWG. #
ISLA112P25MREP (Note 1) ISLA112P25 MREP 250 -55 to +125 72 Ld QFN L72.10x10D
NOTE:
1. These I ntersil Pb-free pl astic packaged products emplo y spec ial Pb-free material sets; moldi ng compounds/di e attach
materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and com p atible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
ISLA112P25M
FN7646 Rev 1.00 Page 5 of 29
November 17, 2011
Table of Contents
Block Diagram ..................................................................................................................................... 1
Pin Configuration................................................................................................... .............................. 2
Pin Descriptions ............................................................. ............. ............. ........................................... 2
Ordering Information .......................................................................................................................... 4
Absolute Maximum Ratings ................................................................................................................. 6
Thermal Information ............................ ................................................................. ............. ................. 6
Operating Conditions........................................................................................................................... 6
Electrical Specifications....................................................................................................................... 6
Digital Specifications........................................................................................................................... 8
Timing Diagrams ................................................................................................................................. 9
Switching Specifications...................................................................................................................... 9
Typical Performance Curves .............................................................................................................. 11
Theory of Operation........................................................................................................................... 14
Functional Description....................................................................................................................... 14
Power-On Calibration.................. ... .. ............ ............. ............. ............ ....................... ........................ 14
User-Initiated Reset ......................................................................................................................... 15
Analog Input ................................................................................................................................... 15
Clock Input ........................................................... .. .. ...................................................................... 16
Jitter .............................................................................................................................................. 17
Voltage Reference............ .. ............. ............................................................................ ..................... 17
Digital Outputs ................................................................................................................................ 17
Over Range Indicator.................. ... ............ ............. ............ ............. ....................... .......................... 17
Power Dissipation............................................................................................................................. 17
Nap/Sleep....................................................................................................................................... 17
Data Format.................................................................................................................................... 18
Serial Peripheral Interface ................................................................................................................ 20
SPI Physical Interface........................ ....................... ............. ............ ............. ............. ..................... 20
SPI Configuration................. .. .. ............. ....................... ............. ............ ............. ............. ................. 21
Device Information........................................................................................................................... 21
Indexed Devi ce Co nfiguration/Control....................... .. ....................... ............. ............ ............. ........... 21
Global Device Configurati o n/Con t rol............. .. .. ... .. .............................................................................. 22
SPI Memory Map... .. ................................ .. .. ................................................................ .. .. ................. 25
Equivalent Circuits............................................................................................................................. 26
ADC Evaluation Platform ................................................................................................................... 27
Layout Considerations....................................................................................................................... 27
Split Ground an d Pow e r Pl ane s................ ....................... ....................... ........................ ..................... 27
Clock Input Consi de rations .................................. ....................... ....................... ................................ 27
Exposed Paddle................................................................................................................................ 27
Bypass and Filtering ................. .. ... ............ ............. ............ ........................ ............ .......................... 27
LVDS Outputs.............. .. ............................................ ...................................................................... 27
LVCMOS Outputs.............................................................................................................................. 28
Unused Inpu ts............. .. ..................... .. .. ..................... .. .. ..................... ... .. ..................... ................. 28
Definitions......................................................................................................................................... 28
Revision History ................................................................................................................................ 28
Products............................................................................................................................................ 28
Package Outline Drawing ............................................................ ...................................................... 29
ISLA112P25M
FN7646 Rev 1.00 Page 6 of 29
November 17, 2011
Absolute Maximum Ratings Thermal Information
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
OVDD to OVSS. . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OV SS . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Thermal Resistance (Typical) JA (°C/W) JC (°C/W)
72 Ld QFN Package (Note 2, 3) . . . 24 0.8
Storage Tempe rature. . . . . . . . . . . . . . . . -65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . -55°C to +125°C
Maximum Operating Junction Temperature. . . . . . . . +135°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
2. JA is measured wi th th e co mponent mounte d on a hi gh effecti v e thermal conductivity test board in free air. See Tech Brief
TB379 for details.
3. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA= -55°C to +125°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE =Maximum Conversion Rate (per
speed grade).
PARAMETER SYMBOL CONDITIONS MIN
(Note 4) TYP MAX
(Note 4) UNITS
DC SPEC IF ICATIONS (Note 5)
Analog Input
Full-Scale Analog Input Range VFS Differential 1.47 VP-P
Input Resistance RIN Differential 1000
Input Capacitance CIN Differential 1.8 pF
Full Scale Range Temp. Drift AVTC Full Temp 90 ppm/°C
Input Offset Voltage VOS ±2 mV
Gain Error EG±0.6 %
Common-Mode Output Voltage VCM 535 mV
Clock Inputs
Inputs Common Mode Voltage 0.9 V
CLKP, CLKN Input Swing 1.8 V
Power Requirements
1.8V Analog Supply Voltage AVDD 1.8 V
1.8V Digital Supply Voltage OVDD 1.8 V
1.8V Analog Supply Current IAVDD 90 mA
1.8V Digital Supply Current (SDR) (Note 6) IOVDD 3mA LV DS 58 mA
1.8V Digital Supply Current (DDR) (Note 6) IOVDD 3mA LV DS 39 mA
Power Supply Rejection Ratio PSRR 30MHz, 200mVP-P signal on A VDD -36 dB
Total Po wer Dissipa ti on
Normal Mode (SDR) PD3mA LVDS 267 mW
Normal Mode (DDR) PD3mA LVDS 234 mW
Nap Mode PD84 mW
Sleep Mode PDCSB at logic high 2 mW
Nap Mode Wakeup Time (Note 7) Sample Clock Running 1 µs
Sleep Mode Wakeup Time (Note 7) Sample Clock Running 1 ms
ISLA112P25M
FN7646 Rev 1.00 Page 7 of 29
November 17, 2011
AC SPECIFICATIONS (Note 9)
Differential Nonlinearity DNL ±0.3 LSB
Integral Nonlinearity INL ±0.8 LSB
Minimum Conversion Rate (Note 8) fS MIN 40 MSPS
Maximum Conversion Rate fS MAX 250 MSPS
Signal-to-Noise Ratio (Note 5) SNR fIN = 10MHz 66.1 dBFS
fIN = 105MHz 66.1 dBFS
fIN = 190MHz 65.9 dBFS
fIN = 364MHz 65.4 dBFS
fIN = 695MHz 63.8 dBFS
fIN = 995MHz 62.6 dBFS
Signal-to-Noise and Distortion SINAD fIN = 10MHz 65.3 dBFS
fIN = 105MHz 65.3 dBFS
fIN = 190MHz 64.6 dBFS
fIN = 364MHz 63.9 dBFS
fIN = 695MHz 56.9 dBFS
fIN = 995MHz 49.6 dBFS
Effective Number of Bits ENOB fIN = 10MHz 10.6 Bits
fIN = 105MHz 10.6 Bits
fIN = 190MHz 10.4 Bits
fIN = 364MHz 10.3 Bits
fIN = 695MHz 9.2 Bits
fIN = 995MHz 7.9 Bits
Spurious-Free Dynamic Range SFDR fIN = 10MHz 83.0 dBc
fIN = 105MHz 87 dBc
fIN = 190MHz 79.4 dBc
fIN = 364MHz 76.1 dBc
fIN = 695MHz 60.6 dBc
fIN = 995MHz 50.7 dBc
Intermodulation Distortion IMD fIN = 70MHz -85.7 dBFS
fIN = 170MHz -97.1 dBFS
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA= -55°C to +125°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE =Maximum Conversion Rate (per
speed grade). (Continued)
PARAMETER SYMBOL CONDITIONS MIN
(Note 4) TYP MAX
(Note 4) UNITS
ISLA112P25M
FN7646 Rev 1.00 Page 8 of 29
November 17, 2011
Word Error Rate WER 10-12
Full Power Bandwidth FPBW 1.3 GHz
NOTES:
4. For min and max parameter limits, refer to DSCC drawing number V62/10609.
5. To ens ure device accuracy the measurement temperature is to be within 60°C of the calibration temperature.
6. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load
on each digital output.
7. See Nap /Sleep Mode description on page 17 for more details.
8. The DLL R ange setting must be changed for low speed operation. See “Serial Peripheral Interface” on page 20 for more detail.
9. AC Specifications apply after internal calibration of the ADC is invoked at the given sample rate and temperature. Refer to
“Power-On Calibration” on page 14 and “User-Initiated Reset” on page 15 for more details.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA= -55°C to +125°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE =Maximum Conversion Rate (per
speed grade). (Continued)
PARAMETER SYMBOL CONDITIONS MIN
(Note 4) TYP MAX
(Note 4) UNITS
Digital Specifications
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
INPUTS
Input Current High (SDIO, RESETN) IIH VIN = 1.8V 1 µA
Input Current Low (SDIO, RESETN) IIL VIN = 0V -12 µA
Input Vo ltage High (SDIO, RESETN) VIH 1.8 V
Input Voltage Low (SDIO, RESETN) VIL 0V
Input Current High (OUTMODE, NAPSLP, CLKDIV,
OUTFMT) (Note 10) IIH 25 µA
Input Current Low (OUTMODE, NAPSLP, CLKDIV,
OUTFMT) IIL 25 µA
Input Capacitance CDI 3pF
LVDS OUTPUTS
Differential Output Voltage VT3mA Mode 620 mVP-P
Output Offset Voltage VOS 3mA Mode 965 mV
Output Rise Time tR500 ps
Output Fall Time tF500 ps
CMOS OUTPUTS
Voltage Output High VOH IOH = -500µA OVDD - 0.1 V
Voltage Output Low VOL IOL = 1mA 0.1 V
Output Rise Time tR1.8 ns
Output Fall Time tF1.4 ns
ISLA112P25M
FN7646 Rev 1.00 Page 9 of 29
November 17, 2011
Timing Diagrams
FIGURE 1A. DDR FIGURE 1B. SDR
FIGURE 1. LVDS TIMING DIAGRAMS (See “Digital Outputs” on page 17)
FIGURE 2A. DDRx FIGURE 2B. SDR
FIGURE 2. CMOS TIMING DIAGRAM (See “Digital Outputs” on page 17)
LATENCY = L CYCLES
tDC
tPD
tA
SAMPLE N
tCPD
INP
INN
CLKN
CLKP
CLKOUTN
CLKOUTP
ODD BITS
N-L N-L ODD BITS ODD BITS EVEN BITS
N-L + 1 N-L + 1 N-L + 2 N-L + 2
EVEN BITSEVEN BITSEVEN BITS
D[10/8/6/4/2/0]P
D[10/8/6/4/2/0]N N
LATENCY = L CYCLES
tDC
tPD
tA
SAMPLE N
tCPD
INP
INN
CLKN
CLKP
CLKOUTN
CLKOUTP
DATA DATA
N-L + 1
D[11/0]P
D[11/0]N N
DATA
N-L
SAMPLE N
tDC
tPD
tA
INP
INN
CLKN
CLKOUT
CLKP
D[10/8/6/4/2/0]
LATENCY = L CYCLES
ODD BITS
N-L N-L ODD BITS ODD BITS EVEN BITS
N-L + 1 N-L + 1 N-L + 2 N-L + 2
EVEN BITSEVEN BITSEVEN BITS N
tCPD
SAMPLE N
INP
INN
CLKN
CLKOUT
CLKP
tCPD
tA
D[11/0]
tDC
tPD
DATA
N-L
DATA DATA
N-L + 1 N
LATENCY = L CYCLES
Switching Specifications
PARAMETER CONDITION SYMBOL MIN TYP MAX UNITS
ADC OUTPUT
Aperture Delay tA375 ps
RMS Aperture Jitter jA60 fs
Output Clock to D a ta Propagation
Delay, LVDS Mode
(Note 11)
DDR Rising Edge tDC -50 ps
DDR Falling Edge tDC 10 ps
SDR Falling Edge tDC -40 ps
Output Clock to D a ta Propagation
Delay, CMOS Mode
(Note 11)
DDR Rising Edge tDC -10 ps
DDR Falling Edge tDC -90 ps
SDR Falling Edge tDC -50 ps
ISLA112P25M
FN7646 Rev 1.00 Page 10 of 29
November 17, 2011
Latency (Pipeline Delay) L 7.5 cycles
Over Voltage Recovery tOVR 1cycles
SPI INTERFACE (Notes 12, 13)
SCLK P e ri od Write Operation tCLK Note 15 cycles
(Note 12)
Read Operation tCLK Note 15 cycles
SCLK Duty Cycle (tHI/tCLK or
tLO/tCLK) Read or Write Note 15 50 Note 15 %
CSBto SCLK Setup Time Read or Write tSNote 15 cycles
CSBafter SCLK Hold Time Read or Write tHNote 15 cycles
Data Valid to SCLK Setup Time Write tDSW Note 15 cycles
Data Valid after SCLK Hold Time Write tDHW Note 15 cycles
Data Valid after SCLK Time Read tDVR Note 15 cycles
Data Invalid after SCLK Time Read tDHR Note 15 cycles
Sleep Mode CSBto SCLK Setup
Time (Note 14) Read or W rite in Sleep Mode tSNote 15 µs
NOTES:
10. The Tri-Level Inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advise d to float the in puts, ti e to
ground or AVDD depending on desired function.
11. The i nput cl ock to out put cl ock de lay is a function of sample rate, using the output clock to latch the data simplifies data
capture for most applications. Contact factory for more info if needed..
12. SPI Interface timing is directly proportional to the ADC sample period (4ns at 250MSPS).
13. The SPI may operate asynchronousl y with respect to the AD C sample clock.
14. The CSB setu p time increases in sleep mo de due to the reduced power state, CSB setup time in Nap mode is equal to normal
mode CSB setup time (4ns min).
15. Refer to DSCC drawing number V62/10609 for min/max parameters.
Switching Specifications (Continued)
PARAMETER CONDITION SYMBOL MIN TYP MAX UNITS
ISLA112P25M
FN7646 Rev 1.00 Page 11 of 29
November 17, 2011
Typical Performance Curves All Typical Performance Characteristics apply under the following
conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum
Conversion Rate (per speed grade).
FIGURE 3. SNR AND SFDR vs fIN FIGURE 4. HD2 AND HD3 vs fIN
FIGURE 5. SNR AND SFDR vs AIN FIGURE 6. HD2 AND HD3 vs AIN
FIGURE 7. SNR AND SFDR vs fSAMPLE FIGURE 8. HD2 AND HD3 vs fSAMPLE
50
55
60
65
70
75
80
85
90
0 200M 400M 600M 800M 1G
INPUT FREQUENCY (Hz)
SNR (dBFS) AND SFDR (dBc)
SNR @ 250MSPS
SFDR @ 250MSPS
SFDR @ 125MSPS
SNR @ 125MSP S
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
0 200M 400M 600M 800M 1G
INPUT FREQUENCY (Hz)
HD2 AND HD3 MAGNITUDE (dBc)
HD2 @ 250MSPS
HD3 @ 125MSPS
HD3 @ 250MSPS
HD2 @ 125MSPS
0
10
20
30
40
50
60
70
80
90
100
-60 -50 -40 -30 -20 -10 0
INPUT AMPLITUDE (dBFS)
SNR AND SFDR
SNR (dBc)
SFDR (dBc )
SNRFS (dBFS)
SFDRFS (d BFS )
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-60-50-40-30-20-10 0
INPUT AMPLITUDE (dBFS)
HD2 & HD3 MAGNITUDE
HD2 (dBc)
HD3 (dBc)
HD3 (dBFS)
HD2 (dBFS)
60
65
70
75
80
85
90
95
40 70 100 130 160 190 220 250
SAMPLE RATE (MSPS)
SNR (dBFS) AND SFDR (dBc)
SFDR
SNR
-120
-110
-100
-90
-80
-70
-60
40 70 100 130 160 190 220 250
SAMPLE RATE (MSPS)
HD2 AND HD3 MAGNITUDE (dBc)
HD2
HD3
ISLA112P25M
FN7646 Rev 1.00 Page 12 of 29
November 17, 2011
FIGURE 9. POWER vs fSAMPLE IN 3mA LVDS MODE FIGURE 10. DIFFEREN TIAL NONLINEARITY
FIGURE 11. INTEGRAL NONLINEARITY FIGURE 12. SNR AND SFDR vs VCM
FIGURE 13. NOISE HISTOGRAM FIGURE 14. SINGLE-TONE SPECTRUM @ 10MHz
Typical Performance Curves All Typical Performance Characteristics apply under the following
conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum
Conversion Rate (per speed grade). (Continued)
0
50
100
150
200
250
300
40 70 100 130 160 190 220 250
SAMPLE RATE (MSPS)
TOTAL POWER (mW)
DDR
SDR
0512 1024 1536 2048 2560 3072 3584 4096
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
CODE
DNL (LSBs)
0 512 1024 1536 2048 2560 3072 3584 4096
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
CODE
INL (LSBs)
50
55
60
65
70
75
80
85
90
300 400 500 600 700 800
INPUT COMMON MODE (mV)
SNR (dBFS) & SF DR (dB c)
SNR
SFDR
2050 2051 2052 2053 2054 2055 2056 2057 2058
0
30000
60000
90000
120000
150000
180000
210000
240000
270000
CODE
NUMBER OF HITS
020 40 60 80 100 120
-120
-100
-80
-60
-40
-20
0
FREQUENCY (MHz)
AIN = -1.0dBFS
SNR = 66.0dBFS
SFDR = 82.5dBc
SINAD = 65.9dBFS
AMPLITUDE (dBFS)
ISLA112P25M
FN7646 Rev 1.00 Page 13 of 29
November 17, 2011
FIGURE 15. SINGLE-TONE SPECTRUM @ 105MHz FIGURE 16. SINGLE-TONE SPECTRUM @ 190MHz
FIGURE 17. SINGLE-TONE SPECTRUM @ 495MHz FIGURE 18. SINGLE-TONE SPECTRUM @ 995MHz
FIGURE 19. TWO-TONE SPECTRUM @ 70MHz FIGURE 20. TWO-TONE SPECTRUM @ 170MHz
Typical Performance Curves All Typical Performance Characteristics apply under the following
conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum
Conversion Rate (per speed grade). (Continued)
020 40 60 80 100 120
-120
-100
-80
-60
-40
-20
0
FREQUENCY (MHz)
AMPLITUDE (dBFS)
AIN = -1.0dBFS
SNR = 66 .0dBF S
SFDR = 86.5dBc
SINAD = 65. 9dBFS
020 40 60 80 100 120
-120
-100
-80
-60
-40
-20
0AIN = -1.0dBFS
SNR = 65.7dBFS
SFDR = 79.2dBc
SINAD = 65.4dBFS
FREQUENCY (MHz)
AMPLITUDE (dBFS)
020 40 60 80 100 120
-120
-100
-80
-60
-40
-20
0
AMPLITUDE (dBFS)
FREQUENCY (MHz)
AIN = -1.0dBFS
SNR = 64.4dBFS
SFDR = 68.8dBc
SINAD = 62.6dBFS
020 40 60 80 100 120
-120
-100
-80
-60
-40
-20
0
FREQUENCY (MHz)
AMPLITUDE (dBFS)
AIN = -1.0dBFS
SNR = 61.6dBFS
SFDR = 49.8dBc
SINAD = 49.8dBFS
020 40 60 80 100 120
-120
-100
-80
-60
-40
-20
0
IMD = -85.7dBFS
FREQUEN CY ( MHz )
AMPLITUDE (dBFS)
020 40 60 80 100 120
-120
-100
-80
-60
-40
-20
0
IMD = -97.1dBFS
AMPLITUDE (dBFS)
FREQUENCY (MHz)
ISLA112P25M
FN7646 Rev 1.00 Page 14 of 29
November 17, 2011
Theory of Operation
Functional Description
The ISLA112P25MREP is based upon a 12-bit, 250MSPS
A/D converter core that utilizes a pipelined successive
approximation architecture (Figure 21). The input
voltage is captured by a Sample-Hold Amplifier (SHA)
and converted to a unit of charge. Proprietary
charge-domain techniques are used to successively
compare the input to a series of reference charges.
Decisions made du rin g the succ essi v e appro xi mati on
operations determine the digital code for each input
va lue. The co n ver ter pi peli ne requi res si x sampl es to
produce a r esult. Di gital er ror correc tion is also ap plied,
resulting in a total latency of seven and one half clock
cycles. This is evident to the user as a time lag between
the start of a conversion and the data being available on
the digital outputs.
Power-On Calibration
The ADC performs a self-cali bration at start -up. An
internal power-on-reset (POR) circuit detects th e supply
voltage ramps and initi ates the calibration when the
analog and digital supply voltages are above a threshold.
The following conditions must be adhered to for the
power-on calibr ation to execute successfully:
• A frequency-stable conv ersion clock must be applied
to the CLKP/CLKN pins
• DNC pins (especially 3, 4 and 18) must not be pulled
up or down
• SDO (pin 66) must be high
• RESETN (pin 25) must begin low
• SPI communications must not be attempted
A user-initiated reset can subsequently be in voked in the
event that the previously mentioned con ditions cannot
be met at power-up.
The SDO pin requires an external 4.7k pull-up to OVDD.
If the SDO pin is pulled low externally during power-up ,
calibration will not be executed properly.
After the power supply has stabilized, the internal POR
releases RESETN and an int ernal pull-up pulls it high,
which starts the calibration sequence. If a subsequent
user-initiated reset is required, the RESETN pin should
be connected to an open-drain driver with a drive
strength of le ss than 0.5mA.
The calibration sequence is initiated on the rising edge
of RESETN, as shown in Figure 22. The over-range
output (OR) is set hi gh once RESET N is pu lled low, and
remains in tha t state un til cali bration is complete. The
OR output returns to normal operation at that time, so it
is important th at th e anal og inpu t be wit hin the
converter’ s full -scale r ange to obs erv e the transition. If
the input is in an over-r ange condition, the OR pin will
stay high, and it will not be possible to detect the end of
the calibration cycle.
While RESETN is low , the output clock
(CLKOUTP/CLKOUTN) is set low . Normal operation of the
output clock resumes at the next input clock edge
(CLKP/CLKN) after RESETN is deasserted. At 250MSPS
the nominal calibration time is 200ms, while the
maximum calibr ation time is 550m s.
FIGURE 21. ADC CORE BLOCK DIAGRAM
DIGITAL
ERROR
CORRECTION
SHA
1.25V
INP
INN
CLOCK
GENERATION
2.5-BIT
FLASH
6-STAGE
1.5-BIT/STAGE
3-STAGE
1-BIT/STAGE
3-BIT
FLASH
LVDS/LVCMOS
OUTPUTS
+
–
ISLA112P25M
FN7646 Rev 1.00 Page 15 of 29
November 17, 2011
User-Initiated Reset
Recal ibratio n of the ADC can be initiated at an y time by
driving the RESETN pin low for a minimum of one clock
cycle. An open-dr ain driv er with a driv e strength of l ess
than 0.5mA is recommended, RESETN has an internal
high impedance pull-up to OVDD. As is the case during
power-on reset, the SDO, RESETN and DNC pins must be
in the proper state for the calibration to successfully
execute.
The performance of the ISLA112P25MREP changes with
variations in temper ature, supply voltage or sample rate.
The extent of these changes may necessitate
recalibration, depending on system performance
requirements. Best performance will be achieved by
recalibrating the ADC under the environmental conditions
at which it will oper ate. Note: To ensure device accuracy
the measurement temperature is to be within 60°C of the
calibration temper ature.
A supply voltage vari ation of less than 100mV will
generally result in an SNR change of less than 0.5dBFS
and SFDR change of less than 3dBc.
In situations where the sample rate is not constant, best
results will be obtained if the device i s calibr ated at the
highest sample r ate. R educing the sample r ate by less
than 75MSPS will typically r esult in an SNR change of
less than 0.5dBFS and an SFDR change of less than
3dBc.
Figures 23 and 24 show the effect of temperature on
SNR and SFDR performance without recalibration. In
each plot, the ADC is calibrated at +25°C and
temperature is v aried over the oper ating r ange without
recalibrating. The a ver age change in SNR/SFDR is
shown, relative to the +25°C v alue.
Analog Input
The ADC core contains a fully differenti al input
(VINP/VINN) to the sample and hold amplifier (SHA). The
ideal full-scale input voltage is 1.45V, centered at the
VCM voltage of 0.535V as shown in Figure 25.
Best performance is obtained when the analog inputs are
driven differentially. The common-mode output voltage,
VCM, should be used to properly bias the inputs as
shown in Figures 26 through 28. An RF tr ansformer wil l
give the best noise and distortion performance for
wideband and/or high intermedi ate frequency (IF)
inputs. Two different transformer input schemes are
shown in Figures 26 and 27.
FIGURE 22. CALIBRATION TIMING
CLKP
CLKN
CLKOUTP
RESETN
ORP
CALIBRATION BE GI NS
CALIBRATION COMPLETE
CALIBRATI O N TIME
FIGURE 23. SNR PERFORMANCE vs TEMPERATURE
(CAL DONE AT +25°C)
TEMPERATURE (°C)
60
61
62
63
64
65
66
67
68
69
70
-55 -35 -15 5 25 45 65 85 105 125
1.7V
1.9V
1.8V
SNR (d B)
FIGURE 24. SFDR PERFORMANCE vs TEMPERATURE
(CAL DONE AT +25°C)
TEMPERATURE (°C)
-55 -35 -15 5 25 45 65 85 105 125
60
65
70
75
80
85
90
1.9V
1.8V
1.7V
SFDR (dB)
ISLA112P25M
FN7646 Rev 1.00 Page 16 of 29
November 17, 2011
This dual transformer scheme i s used to improve
common-mode rejection, which keeps the common-
mode level of the input matched to VCM. The value of the
shunt resistor should be determined based on the
desired load impedance. The differential input resistance
of the ISLA112P25MREP is 1000.
The SHA design uses a switched capacitor input stage
(see Figure 41), which creates current spikes when the
sampling capacitance is reconnected to the input voltage.
This causes a disturbance at the input which must settle
before the next sampling point. Lower source impedance
will result in faster settling and improved performance.
Therefore a 1:1 transformer and low shunt resistance are
recommended for optimal performance.
A differential amplifier, as shown in Figure 28, can be
used in applications that require DC -coupling. In thi s
configuration, the amplifier will typically dominate the
achievable SNR and distortion perfo rmance.
Clock Input
The clock input circuit is a differential pair (see
Figure 42). Driving these inputs wi th a high lev el (up to
1.8VPP on each input) sine or square wav e will pro vide
the lowest jitter performance. A transformer with 4:1
impedance ratio will pro vide increased drive lev els.
The recommended drive circuit is shown in Figure 29. A
duty range of 40% to 60% is acceptable. The clock can
be driven single-ended, but this will reduce the edge r ate
and may impact SNR performance. The clock inputs are
internally self -biased to AVDD/2 to facilitate AC coupling.
A selectable 2x frequency divider is provided in series
with the clock input. The divider can be used in the 2x
mode with a sample clock equal to twice th e desired
sample rate. This allows the use of the Phase Slip
feature, which enables synchronization of multiple ADCs.
The clock divider can also be controlled through the SPI
port, which ov errides the CLKDIV pin setting. Details on
this are contained in “Serial Peripheral Interface” on
page 20.
FIGURE 25. ANALOG INPUT RANGE
1.0
1.8
0.6
0.2
1.4
INP
INN
VCM
0.535V
0.725V
FIGURE 26. TRANSFORMER INPUT FOR GENERAL
PURPOSE APPLICATIONS
FIGURE 27. TRANSMISSION-LINE TRANSFORMER
INPUT FOR HIGH IF APPLICATIONS
ADTL1-12
0.1µF
KAD5512P
VCM
ADTL1-12
1000pF
1000pF
TABLE 1. CLKDIV PIN SETTINGS
CLKDIV PIN DIVIDE RATIO
AVSS 2
Float 1
AVDD 4
KAD5512P
VCM
0.1µF
0.22µF
69.849.9
100
100
348
348
CM 217
25
25
69.8
FIGURE 28. DIFFERENTIAL AMPLIFIER INPUT
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
FIGURE 29. RECOMMENDED CLOCK DRIVE
TC4-1W
200pF 200O
200pF
200pF
CLKP
CLKN
1000pF
Ω
ISLA112P25M
FN7646 Rev 1.00 Page 17 of 29
November 17, 2011
A delay-lock ed loop (DLL) gener ates internal clock
signals for v arious stages within the charge pipeline. If
the frequency of the input clock changes, the DLL may
take up to 52µs to regain lock at 250MSPS. The lock time
is inversely proportional to the sample rate.
Jitter
In a sampled data system, clock jitter directly i mpacts
the achievable SNR performance. The theoretical
relationship between clock jitter (tJ) and SNR is shown in
Equation 1 and is illustrated in Figure 30.
This relationship shows the SNR that would be achieved
if clock jitter were the only non-ideal factor. In reality,
achievabl e SNR is limited by internal factors such as
linearity, aperture jitter and thermal noise. Internal
aperture jitter is the uncertainty in the sampling in stant
shown in Figure 1. The internal aperture jitter combines
with the input clock jitter in a root -sum-square fashion,
since they are not statistically correlated, and thi s
determines the total jitter in the system. The total jitter,
combined with other noise sources, then determines the
achiev able SNR.
Voltage Reference
A temperature compensated voltage reference provides
the reference charges used in the successive
approximation oper ations. The full-scale r ange of each
A/D is proportional to the reference v oltage. The v oltage
reference is internally bypassed and is not accessible to
the user.
Digital Outputs
Output data is av ailable as a par allel bus i n
LVDS-compatible or CMOS modes. A dditi onally, the data
can be presented in either double data rate (DDR) or
single data rate (SDR) formats. The even numbered data
output pins are active in DDR mode. When CLKOUT i s
low the MSB and all odd logical bits are output, while on
the high phase the LSB and all even logical bits are
presented. Figures 1 and 2 show the timing relationships
for LVDS/CMOS and DDR/SDR modes.
Additionally, the drive current for L VDS mode can be set
to a nominal 3mA or a power-sa ving 2mA. The lower
current setting can be used in designs where the receiver
is in close physical proximity to the ADC. The applicability
of this setting is dependent upon the PCB lay out,
therefore the user should experiment to determine if
performance degradation is observed.
The output mode and L VDS drive current are selected via
the OUTMODE pin as shown in Table 2.
The output mode can also be controlled through the SPI
port, which ov errides the OUTMODE pin setting. Details
on this are contained in “Serial Peripheral Interface” on
page 20.
An external resistor creates the bias for the LVDS drivers.
A 10k, 1% resistor must be connected from the RL VDS
pin to OVSS.
Over Range Indica tor
The over r a nge (OR) bit is as serted when the output
code reaches posi tiv e full- scale (e.g. 0xFFF in offset
binary mode). The output code does not wrap around
during an over-range condition. The OR bit is updated at
the sample rate.
Power Dissipation
The power dissipated by the ISLA112P25MREP is
primarily dependent on the sample r ate and the output
modes: LVDS vs CMOS and DDR vs SDR. There is a static
bias in the analog supply, while the remaining power
dissipation is linearly related to the sample r ate. The
output supply dissipation is approximately constant i n
L VDS mode, but linearly related to the clock frequency in
CMOS mode. Figures 34 and 35 illustrate these
relationships.
Nap/Sleep
Portions of the device may be shut down to save power
during times when operati on of the ADC is not required.
Two power saving modes are av ailable: Nap, and Sleep.
Nap mode reduces power dissipation to less than 95mW
and recovers to normal operation in approximately 1µs.
Sleep mode reduces power dissipation to less than 6mW
but requires approximately 1m s to recover from a sleep
command.
Wake-up time from sleep m ode is de pendent on the
state of CSB; in a typical application CSB would be held
high during sleep , requir ing a user to w ait 150µ s max
after CSB is asserted (brought low) prior to writing
‘001x’ to SPI R egister 25. The device would be fully
powered up, in normal mode 1ms after th is command is
written.
SNR 20 log10
1
2fINtJ
--------------------


=(EQ. 1)
FIGURE 30. SNR vs CLOCK JITTER
tj = 100ps
tj = 10ps
tj = 1ps
tj = 0.1ps
10 BITS
12 BITS
14 BITS
50
55
60
65
70
75
80
85
90
95
100
1 10 100 1000
SNR (dB)
INPUT FREQUENCY (MHz)
TABLE 2. OUTMODE PIN SETTINGS
OUTMODE PIN MODE
AVSS LVCMOS
Float LVDS, 3mA
AVDD LVDS, 2mA
ISLA112P25M
FN7646 Rev 1.00 Page 18 of 29
November 17, 2011
Wake-up from Sleep Mode Sequence (CSB high)
•Pull CSB Low
• Wait 150µs
• Write ‘001x’ to Register 25
• Wa it 1 ms until ADC fully powered on
In an applicati on where CSB w as k ept lo w in sleep
mode, the 150µs CSB setup time is not re qui red as th e
SPI registers are powered on when CSB is low, the chip
power dissipation increases by ~ 15mW in this case.
The 1ms wake-up ti me after the write of a ‘001x’ to
register 25 still applies. It is generally recommended to
keep CSB high in sleep mode to av oid any unintentional
SPI activity on the ADC.
All digital outputs (Data, CLKOUT and OR) are placed in
a high impedance state during Nap or Sleep. The input
clock should remain running and at a fixed frequency
during Nap or Sleep, and CSB should be high. R ecovery
time from Nap mode will increase if the clock is stopped,
since the internal DLL can take up to 52µs to regain lock
at 250MSPS
By default after the device is powered on, the operational
state is controlled by the NAPSLP pin as shown in Table 3.
The power-down mode can also be controlled through
the SPI port, which overrides the NAPSLP pin setting.
Details on this are contained in “Serial P eripher al
Interface” on page 20. This is an indexed function when
controlled from the SPI, but a global function when
driven from the pin.
Data Format
Output data can be presented in three formats: two’s
complement, Gray code and of fset binary. The data
format is selected via the OUTFMT pin as shown in
Table 4.
The data format can also be controlled through the SPI
port, which overrides the OUTFMT pin setting. Detai ls on
this are contained in “Serial P eripher al Interface” on
page 20.
Offset binary coding maps the most negative input
voltage to code 0x000 (all zeros) and the most positive
input to 0xFFF (all ones). Two’s complement coding
simply complements the MSB of the offset binary
representation.
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current
bit position and the next most significant bit. Figure 31
shows this operation.
Converting back to offset binary from Gray code m ust be
done recursively, using the result of each bit for the next
lower bit as shown in Figure 32.
TABLE 3. NAPSLP PIN SETTINGS
NAPSLP PIN MODE
AVSS Normal
Float Sleep
AVDD Nap
TABLE 4. OUTFMT PIN SETTINGS
OUTFMT PIN MODE
AVSS Offset Binary
Float Two’s Complement
AVDD Gray Code
FIGURE 31. BINARY TO GRAY CODE CONVERSION
1011 9 01BINARY
1011 9 0GRAY CODE
• • • •
• • • •
• • • •
1
FIGURE 32. GRA Y CODE TO BINARY CO NVERSION
1011 9 01
BINARY 1011 9 0
GRAY CODE • • • •
• • • •
• • • •
1
• • • •
ISLA112P25M
FN7646 Rev 1.00 Page 19 of 29
November 17, 2011
Mapping of the input v oltage to the v ari ous data formats is shown i n Table 5.
TABLE 5. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT VOLTAGE OFFSET BINARY TWO’S COMPLEMENT GRAY CODE
–Full Scale 000 00 000 00 00 100 00 000 00 00 000 00 000 00 00
–Full Scale + 1LSB 000 00 000 00 01 100 00 000 00 01 000 00 000 00 01
Mid–Scale 100 00 000 00 00 000 00 000 00 00 110 00 000 00 00
+Full Scale – 1LSB 111 11 111 11 10 011 11 111 11 10 100 00 000 00 01
+Full Scale 111 11 111 11 11 011 11 111 111 1 100 00 000 00 00
FIGURE 33. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO R/W W1 W0 A12 A11 A1 A0 D7 D6 D5 D4 D3 D2 D1D 0A10
FIGURE 34. LSB-FIRST ADDRESSI NG
CSB
SCLK
SDIO R/WW1W0A12A11A1A0 D7D6D5D4D3D2D1
D0A2
FIGURE 35. SPI WRITE
tS
tHI tCLK
tLO
R/W W1W0A12A11A10A9A8A7 D5 D4 D3 D2 D1 D0
tH
tDHW
tDSW
SPI WRITE
CSB
SCLK
SDIO
ISLA112P25M
FN7646 Rev 1.00 Page 20 of 29
November 17, 2011
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to
facilitate confi guration of the device and to optimize
performance. The SPI bus consists of chip select (CSB),
serial clock (SCLK) serial data output (SDO), and serial
data input/ou tput (SDIO) . The maxi mum SCLK r at e is
equal to the ADC sample rate (fSAMPLE) divided by 16
for write operations and fSAMPLE divided by 66 for
reads. At fSAMPLE = 250MHz, maximum SCLK is
15.63MHz for writing and 3.79MHz for read oper atio ns.
There is no minimum SCLK rate.
The following sections describe vari ous regi ster s tha t
are used to configure the SPI or a dju st performanc e or
functional parameters. Many registers in the available
address space (0x00 to 0xFF) are not defined in this
document. Additionally, within a defined register there
may be certain bits or bit combinations that are
reserved. Undefined re giste rs and undefined values
within defined registers are reserv ed and should not be
selected. Setting an y reserv ed re gist er or value may
produce indeter min ate re sult s.
SPI Physical Interface
The serial clock pin (SCLK) pro vides synchroni zation for
the data transfer. By default, all data is presented on the
serial data input/output (SDIO) pin in three- wire mode.
The state of the SDIO pin is set automatical ly in the
communication protocol (described below). A dedicated
serial data output pin (SDO) can be activ ated by setting
0x00[7] high to allow operation in four-wire mode.
The SPI port operates in a half duplex master/slave
configuration, with the ISLA112P25MREP functioning as a
slave. Mul tiple slav e devices can interface to a single
master in three-wire mode only, since the SDO output of
an unaddressed device is asserted in four- wire mode.
The chip-select bar (CSB) pin determines when a slave
device is being addressed. Multiple slave devices can be
written to concurrently, but only one slave device can be
FIGURE 36. SPI REA D
(3 WIRE MODE)
(4 WIRE MODE)
R/W W1 W0 A12 A11 A10 A9 A2 A1 D7 D6 D3 D2 D1
D7 D3 D2 D1 D0
A0
WRITING A READ COMMAND READING DATA
D0
tH
tDHR
tDVR
SPI READ
tHI tCLK
tLO
tDHW
tDSW
tS
CSB
SCLK
SDIO
SDO
FIGURE 37. 2-BYTE TRANSFER
CSB
SCLK
SDIO INSTRUCTION/ADDRESS DATA WORD 1 DATA WORD 2
CSB STALLING
FIGURE 38. N-BYTE TRANSFER
CSB
SCLK
SDIO INSTRUCTION/ADDRESS DATA WORD 1 DATA WORD N
LAST LEGAL
CSB STALLING
ISLA112P25M
FN7646 Rev 1.00 Page 21 of 29
November 17, 2011
read from at a given time (again, on ly in three-w ire
mode). If multiple slav e devices are selected for reading
at the same time, the results will be indeterminate.
The communication protocol begins with an
instruction/address phase. The first rising SCLK edge
following a high to low tr ansition on CSB determi nes the
beginning of the two-byte instruction/address command;
SCLK must be static low before the CSB transition. Data
can be presented in MSB-first order or LSB-first order.
The default is MSB-first, but this can be changed by
setting 0x00[6] high. Figures 33 and 34 show the
appropriate bit orderi ng for the MSB-first and LSB-first
modes, respectively. In MSB-first mode the address is
incremented for multi-byte tr ansfers, while in LSB-first
mode it’s decremented.
In the default mode the MSB is R/W, which determines if
the data is to be read (active hi gh) or written. The next
two bits, W1 and W0, determine the number of data
bytes to be read or written (see Table 6). The lower 13
bits contain the first address for the data transfer. This
relationship is illustr ated in Fi gure 35, and timing v alues
are given in “S witching Specifications” on page 9.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read
from the ADC (based on the R/W bit status). The data
transfer will continue as long as CSB remains low and
SCLK is active. Stalling of the CSB pin is al lowed at any
byte boundary (instruction/address or data) if the
number of bytes being tr ansferred is three or less. F o r
transfers of four bytes or more, CSB is allowed stall in the
middle of the instruction/address bytes or before the first
data byte. If CSB transitions to a hi gh state after that
point the state machine will reset and terminate the data
transfer.
Figures 37 and 38 illustrate the timing relationships for
2-byte and N-byte transfers, respectiv ely. The operation
for a 3-byte transfer can be inferred from these
diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register.
Bit order can be selected as MSB to LSB (MSB first) or
LSB to MSB (LSB first) to accommodate various
microcontrollers.
Bit 7 SDO Active
Bit 6 LSB First
Setting this bit high configures the SPI to interpret serial data
as arriving in LSB to MSB order.
Bit 5 Soft Re set
Setting this bit high resets all SPI registers to default values.
Bit 4 Reserved
This bit should always be set high.
Bits 3:0 These bits should always mirror bits 4:7 to
avoid ambiguity in bit ordering.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst
mode can improve throughput by eliminating redundant
addressing. In 3-w ire SPI mod e the burst is e nded b y
pulling the CSB pin high. If the device is operated in
2-wire mode the CSB pin i s not a v ailable. In that case,
setting the burst_end address determines the end of the
transfer. During a write operation , the user must be
cautious to transmit the correct number of bytes based
on the starting and ending addresses.
Bits 7:0 Burst End Address
This register value determines the ending address of the
burst data.
Device Information
ADDRESS 0X08 : CHIP_ID
ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number,
respectively, can be read from these two registers.
Indexed Device Configuration/Control
ADDRESS 0X10 : DE VICE_INDEX_A
A common SPI map, which can accommodate
single-channel or multi-channel devi ces, is used for all
Intersil ADC products. Certain configuration commands
(identified as Indexed in the SPI map) can be executed
on a per-conv erter basis. This register determines which
converter is being addressed for an Indexed command. It
is important to note that only a si ngle conv erter can be
addressed at a time.
This register defaults to 00h, indicating that no ADC i s
addressed. Therefore Bit 0 must be set high in order to
execute any Indexed commands. Error code ‘AD’ is
returned if any indexed register is read from without
properly se tting dev ice_i ndex_A .
ADDRESS 0X20: OFFSET_COARSE AND
ADDRESS 0X21 : OF FSET_FINE
The input offset of the ADC core can be adj usted in fi ne
and coarse steps. Both adjustments are made via an
8-bit word as detailed in Table 7.
The default val ue of each register will be the result of the
self-calibr ation after initial power-up. If a register is to be
TABLE 6. BYTE TRANSFER SELECTION
[W1:W0] BYTES TRANSFERRED
00 1
01 2
10 3
11 4 or more
ISLA112P25M
FN7646 Rev 1.00 Page 22 of 29
November 17, 2011
incremented or decremented, the user should first read
the register value then write the incremented or
decremented value back to the same register.
ADDRESS 0X22: GAIN_COARSE
ADDRESS 0X23: GAIN_MEDIUM
ADDRESS 0X24 : GAIN_FINE
Gain of the ADC core can be adjusted in coarse, medium
and fine steps. Coarse gain is a 4-bit adjustment while
medium and fine are 8-bit. Multiple Coarse Gain Bits can
be set for a total adjustment range of +/- 4.2%. (‘0011’
=~ -4.2% and ‘1100’ =~ +4.2%) It is recommended to
use one of the coarse gain settings (-4.2%, -2.8%, -
1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain
using the registers at 23h and 24h.
The default v alue of each register will be the result of the
self-calibr ation after initial power-up. If a register is to be
incremented or decremented, the user should first read
the register value then write the incremented or
decremented value back to the same register.
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By
default, the tri-level NAPSLP pin can select normal
operation or sleep modes (refer to “Nap/Sleep” on
page 17). This functionality can be overridden and
controlled through the SPI. This is an i ndexe d function
when controlled from the SPI, but a global functi on when
driven from the pin. This register is not changed by a
Soft R eset.
Nap mode must be entered by executing the following
sequence:
R eturn to Normal oper ation as fol lows:
Global Device Configuration/Control
ADDRESS 0X71: PHASE_SLIP
When using the clock divide r, it’s n ot possible to
determine the synchronization of the incoming and
divided clock ph ases. T his is parti cularly important when
multiple ADCs are used in a time-interlea ved system.
The phase slip feature allows the rising edge of the
divided clock to be advanced by one input clock cycle
when in CLK/4 mode, as shown in Figure 39. Execution of
a phase_slip command is accomplished by first writing a
‘0’ to bit 0 at address 71h followed by writing a ‘1’ to bit 0
at address 71h (32 sclk cycles).
TABLE 7. O FFSET ADJUSTMENTS
PARAMETER 0x20[7:0]
COARSE OFFSET 0x21[7:0]
FINE OFFSET
Steps 255 255
–Full Scale (0x00) -133LSB (-47mV) -5LSB (-1.75mV)
Mid–Scale (0x80) 0.0LSB (0.0mV) 0.0LSB
+Full Scale (0 xFF) +133LSB (+47mV) +5LSB (+1.75mV)
Nominal Step Size 1.04LSB (0.37mV) 0.04LSB
(0.014mV)
TABLE 8. COARSE GAIN ADJUSTMENT
0x22[3:0] NOMINAL COARSE GAIN ADJUST
(%)
Bit3 +2.8
Bit2 +1.4
Bit1 -2.8
Bit0 -1.4
TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS
PARAMETER 0x23[7:0]
MEDIUM GAIN 0x24[7:0]
FINE GAIN
Steps 256 256
–Full Scale (0x00) -2% -0.20%
Mid–Scale (0x80) 0.00% 0.00%
+Full Scale (0xFF) +2% +0.2%
Nominal Step Size 0.016% 0.0016%
TABLE 10. POW ER-DO WN CONTROL
VALUE 0x25[2:0]
POWER-DOWN MODE
000 Pin Control
001 Normal Operation
010 Nap Mode
100 Sleep Mode
SEQUENCE REGISTER VALUE
1 0x10 0x01
2 0x25 0x02
3 0x10 0x02
4 0x25 0x02
SEQUENCE REGISTER VALUE
1 0x10 0x01
2 0x25 0x01
3 0x10 0x02
4 0x25 0x01
ISLA112P25M
FN7646 Rev 1.00 Page 23 of 29
November 17, 2011
ADDRESS 0X72: CLOCK_DIVIDE
The ISLA112P25MREP has a selectable clock divider that
can be set to divide by four, two or one (no division). B y
default, the tri-level CLKDIV pin selects the divisor (refer
to “Clock Input” on page 16). This functionality can be
overridden and controlled through the SPI, as shown in
Table 11. This register is not changed by a Soft Reset.
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
ISLA112P25MREP can present output data in two
physical formats: LVDS or L VCMOS . Additionall y, the
drive strength in LVDS mode can be set high (3mA) or
low (2mA). By default, the tri- level OUTMODE pin selects
the mode and drive level (refer to “Digital Outputs” on
page 17). This functionality can be overridden and
controlled through the SPI, as shown in Table 12.
Data can be coded in three possible formats: two’ s
complement, Gra y code or offset binary. By default, the
tri-level OUTFMT pin selects the data format (refer to
“Data Format” on page 18). This functionality can be
overridden and controlled through the SPI, as shown in
Table 13.
This register is not changed by a Soft R eset.
ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFI G_ STA TUS
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default) or slow.
Internal clock signals are generated by a delay-locked loop
(DLL), which has a finite operating range. Table 14 shows
the allowable sample rate ranges for the slow and fast
settings.
.
The output_mode_B and config_status registers are used
in conjunction to enable DDR mode and select the
frequency range of the DLL clock gener ator. The method
of setting these options is different from the other
registers.
The procedure for setting output_mode_B is shown in
Figure 40. Read the contents of output_mode_B and
config_status and XOR them. Then XOR this result with
the desired value for output_mode_B and write that XOR
result to the register.
Device Test
The ISLA112P25MREP can produce preset or user
defined patterns on the digi tal outputs to facilitate in-site
TABLE 11. CLOCK DIVIDER SELECTION
VALUE 0x72[2:0]
CLOCK DIVIDER
000 Pin Control
001 Divide by 1
010 Divide by 2
100 Divide by 4
FIGURE 39. PHASE SLIP: CLK4 MODE,
fCLOCK = 1000MHz
CLK
CLK÷4
CLK÷4
SLIP ONCE
CLK = CLKP – CLKN
CLK÷4
SLIP TWICE
1.00ns
4.00ns
TABLE 12. OUTPUT MOD E CON T ROL
VALUE 0x93[7:5]
000 Pin Control
001 LVDS 2mA
010 LVDS 3mA
100 LVCMOS
TABLE 13. OUTPUT FORMAT CONTROL
VALUE 0x93[2:0]
OUTPUT FORMAT
000 Pin Control
001 Two’s Complement
010 Gray Code
100 Offset Binary
TABLE 14. DLL RANGES
DLL RANGE MIN MAX UNIT
Slow 40 100 MSPS
Fast 80 fS MAX MSPS
FIGURE 40. S ETTING OUTPUT_MODE_B REGISTER
READ
CONFIG_STATUS
0x75
READ
OUTPUT_MODE_B
0x74
DESIRED
VALUE
WRITE TO
0x74
FN7646 Rev 1.00 Page 24 of 29
November 17, 2011
ISLA112P25M
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
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For additional products, see www.intersil.com/en/products.html
© Copyright Intersil Americas LLC 2011. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
testing. A static word can be placed on the output bus, or
two different words can altern ate. In the alternate mode,
the values defined as Word 1 and Word 2 (as shown in
Table 15) are set on the output bus on alternating clock
phases. The test mode is enabled asynchronously to the
sample clock, therefore sever al sample clock cycl es may
elapse before the data is present on the output bus.
ADDRESS 0XC0: TEST_IO
Bits 7:6 User Test Mode
These bits set the test mode to static (0x00) or alternate
(0x01) mode. Other values are reserved.
The four LSBs in this register (Outpu t Test Mode)
determine the test pattern in combination with registers
0xC2 through 0xC5. Refer to Table 16.
ADDRESS 0XC2: USER _PATT1_LSB AND
ADDRESS 0XC3: USER _PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
ADDRESS 0XC4: USER _PATT2_LSB AND
ADDRESS 0XC5: USER _PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
TABLE 15. OUTPUT TEST MODES
VALUE
0xC0[3:0]
OUTPUT TEST
MODE WORD 1 WORD 2
0000 Off
0001 Midscale 0x8000 N/A
0010 Positive Full-Scale 0xFFFF N/A
0011 Negativ e Full -Scale 0x0000 N/A
0100 Checkerboard 0xAAAA 0x5555
0101 Reserved N/A N/A
0110 Reserved N/A N/A
0111 One/Zero 0xFFFF 0x0000
1000 User Pattern user_patt1 user_patt2
ISLA112P25M
FN7646 Rev 1.00 Page 25 of 29
November 17, 2011
SPI Memory Map
TABLE 16. SPI MEMORY MAP
ADDR
(Hex) PARAMETER
NAME BIT 7
(MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 Bit 0
(LSB) DEF. VALUE
(Hex) INDEXED/
GLOBAL
SPI Config
00 port_config SDO
Active LSB First Soft
Reset Mirror
(bit5) Mirror
(bit6) Mirror
(bit7) 00h G
01 reserved Reserved
02 burst_end Burst end address [7:0] 00h G
03-07 reserved Reserved
Info
08 chip_id Chip ID # Read onl y G
09 chip_version Chip V ersion # Read only G
Indexed Device Config/Control
10 device_index_A Reserved ADC00 00h I
11-1F reserved Reserved
20 offset_coarse Coarse Offset cal. value I
21 offset_fine Fine Offset cal. value I
22 gain_coarse Reserv ed Coarse Gain cal. value I
23 gain_medium Medium Gain cal. value I
24 gain_fine Fine Gain cal. value I
25 modes Reserved Power-Down Mode [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
other codes = reserved
00h
NOT
affected by
Soft Reset
I
26-5F reserved Reserved
60-6F reserved Reserved
Global Device Config/Control
70 reserved Reserved
71 phase_slip Reserved Next
Clock
Edge
00h G
72 clock_divide Cloc k Divid e [2:0]
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
other codes = reserved
00h
NOT
affected by
Soft Reset
G
73 output_mode_A Output Mode [2:0 ]
000 = Pin Control
001 = LVDS 2mA
010 = LVDS 3mA
100 = LVCMOS
other codes = reserved
Output Format [2:0]
000 = Pin Control
001 = Twos Complement
010 = Gray Code
100 = Offset Binary
other codes = reserved
00h
NOT
affected by
Soft Reset
G
74 output_mode_B DLL Range
0 = fast
1 = slow
DDR
Enable
(Note 16)
00h
NOT
affected by
Soft Reset
G
75 config_status XOR
Result XOR
Result Read Only G
76-BF reserved Reserved
ISLA112P25M
FN7646 Rev 1.00 Page 26 of 29
November 17, 2011
Device Test
C0 test_io User Test Mode
[1:0]
00 = Single
01 = Alternate
10 = R eserv ed
11 = R eserv ed
Output Test Mod e [ 3:0] 00h G
0 = Off
1 = Midscale Short
2 = +FS Shor t
3 = -FS Shor t
4 = Checker Board
5 = R eserv ed
6 = R eserv ed
7 = One/Zer o W ord
Toggle
8 = User Input
9-15 = R eserv ed
C1 Reserved Reserved 00h G
C2 user_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h G
C3 user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 00h G
C4 user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h G
C5 user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 00h G
C6-FF Reserved Reserved
NOTE:
16. At power-up, the DDR Enable bit is at a logic ‘0’ for the 72 pin package and set to a logic ‘1’ inter nally for the 48 pin pa ckage by an i nternal pull- up.
TABLE 16. SPI MEMORY MAP (Cont inued)
ADDR
(Hex) PARAMETER
NAME BIT 7
(MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 Bit 0
(LSB) DEF. VALUE
(Hex) INDEXED/
GLOBAL
Equivalent Circuits
FIGURE 41. ANALOG INPUTS FIGURE 42. CLOCK INPUTS
FIGURE 43. TRI-LEVEL DIGITAL INPUTS FIGURE 44. DIGITAL INPUTS
AVDD
INP
INN
AVDD
F1
F1
F2 F3
F2 F3
CSAMP
1.6pF
CSAMP
1.6pF TO
CHARGE
PIPELINE
TO
CHARGE
PIPELINE
1000O
AVDD
CLKP
CLKN
AVDD
AVDD
TO
CLOCK-PHASE
GENERATION
11kO
11kO
AVDD
18kO
18kO
AVDD
INPUT
AVDD
AVDD AVDD
TO
SENSE
LOGIC
75kO
75kO
75kO75kO
280O
INPUT
OVDD
OVDD
280
TO
LOGIC
OVDD
(20k PULL-UP
ON RESETN
ONLY)
20k
ISLA112P25M
FN7646 Rev 1.00 Page 27 of 29
November 17, 2011
ADC Evaluation Platform
Intersil offers an ADC Ev alu ation platform which can be
used to evaluate the KADxxxxx ADC family. The platform
consists of a FPGA based data capture motherboard and
a family of ADC daughter cards. This USB based platform
allows a user to quickly ev aluate the functioning of the
ISLA112P25MREP at room temperature with the
KAD5512P-25Q72 based daughter card at a user’s
specific application frequency requirements. More
information is av ailable at:
http://www.intersil.com/converters/adc_eval_platform/
Layout Considerations
Split Ground and Power Planes
Data converters oper ating at high sampli ng frequen cies
require extra care in PC board la yout. Many complex
board designs benefit from isolating the analog and
digital sections. Analog supply and ground planes should
be laid out under signal and clock inpu ts. Locate the
digital planes under outputs and logic pins. Grounds
should be joined under the chip.
Clock Input Considerations
Use matched transmission lines to the transformer inputs
for the analog input and clock signals. Locate
transformers and terminations as close to th e chip as
possible.
Exposed Paddle
The exposed paddle must be electrically connected to
analog ground (A VSS) and shoul d be connected to a
large copper plane using numerous vias for optimal
thermal performance.
Bypass and Filtering
Bulk capacitors should hav e low equiv alent series
resistance. Tantalum is a good choice. F or best
performance, keep ceramic bypass capacitors v ery close
to device pins. Longer traces will increase inductance,
resulting in diminished dynamic perfo rmance and
accuracy. Make sure that connections to ground are
direct and low impedance. Avoid forming ground loops.
LVDS Outputs
Output traces and connections must be designed for 50
(100 differential) char acteristic impedance. Keep traces
FIGURE 45. LVDS OUTPUTS FIGURE 46. CMOS OUTPUTS
FIGURE 47. VCM_OUT OUTPUT
Equivalent Circuits (Continued)
D[11:0]P
OVDD
OVDD
2mA OR
3mA
2mA OR
3mA
DATA
DATA
DATA
DATA
D[11:0]N
OVDD
D[11:0]
OVDD
OVDD
DATA
VCM
AVDD
0.535V +
–
ISLA112P25M
FN7646 Rev 1.00 Page 28 of 29
November 17, 2011
direct and minimize bends where possible. Avoid crossing
ground and power-plane breaks with signal traces.
LVCMOS Outputs
Output traces and connections must be designed for 50
characteristic impedance.
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO)
which will not be oper ated do not require con nection to
ensure optimal ADC performance. These inputs can be
left floating if they are not used. Tri-level inputs (NAPSLP,
OUTMODE, OUTFMT, CLKDIV) accept a floating input as a
valid state, and therefore should be biased according to
the desired functionality.
Definitions
Analog Input Bandwidth is the analog input frequency
at which the spectral ou tput power at the fundamental
frequency (as determined by FFT analysis) is reduced by
3dB from its full-scale low-frequency v alue. This is also
referred to as Full P ower Bandwi dth.
Aperture Delay or Sampling Delay is the time
required after the rise of the clock input for th e sampling
switch to open, at which time the signal is held for
conversion.
Aperture Jitter is the RMS v ariation in aperture dela y
for a set of samples.
Clock Duty Cycle is the ratio of the time th e clock wave
is at logic high to the total time of one clock period.
Differential Non-Linearity (DNL) is the deviation of
any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB) is an alternate
method of specifying Sign al to No ise-and-Dist ortio n
Ratio (SINAD). In dB, it is calculated as:
ENOB = (SINAD - 1.76)/6.02
Gain Error is the ratio of the difference between the
voltages that cause the lowest and highest code
transitions to the full-scale v oltage less 2 LSB. It is
typically expressed in percent.
Integral Non-Linearity (INL) is the maximu m
deviation of the ADC’s transfer function from a best fit
line determined by a least squares curv e fit o f that
transfer function, measured in units of LSBs.
Least Significant Bit (LSB) is the bit that has the
smallest value or weight in a digital word. Its value in
terms of input voltage is VFS/(2N-1) where N is the
resolution in bits.
Missing Codes are output codes that are skipped and
will never appear at the ADC output. These codes cannot
be reached with any input value.
Most Significant Bit (MSB) is the bit that has the
largest value or weight.
Pipeline Delay is the number of clock cycles between
the initiation of a conversion and the appear ance at the
output pins of the data.
Power Supply Rejection Ratio (PSRR) is the ratio of
the observed magnitude of a spur in the ADC FFT, caused
by an AC signal superimposed on the power supply
voltage.
Signal to Noise-and-Distortion (SINAD) is the ratio
of the RMS signal amplitude to the RMS sum of all other
spectral components below one half the clock frequency,
including harmonics but excluding DC.
Signal-to-Noise Ratio (without Harmonics) is the ratio
of the RMS signal amplitude to the RMS sum of all other
spectr al co mponen ts belo w one-hal f the sampli ng
frequency, excluding harmoni cs and DC.
SNR and SINAD ar e either giv en in units of dB when the
power of the fundamental is u sed as the ref erence, or
dBFS (dB to full scale) when the conv erter’ s full-scale
input power is used as the reference.
Spurious-Free-Dynamic Range (SFDR) is the ratio of
the RMS signal amplitude to the RMS v alue of the largest
spurious spectral component. The largest spurious
spectral co mponent ma y or may no t be a harmoni c.
Products
Intersil Corporation is a leader in the design and manuf acture of high-performan ce analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
For a complete li sting of Applications, Related Documentation and Related P arts, please see the respective device
information page on intersil.com: ISLA112P25MREP
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE REVISION CHANGE
6/25/10 FN7646.0 Initial Re lease
ISLA112P25M
FN7646 Rev 1.00 Page 29 of 29
November 17, 2011
Package Outline Drawing
L72.10x10D
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 11/08
located within the zone indicated. The pin #1 identifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.30mm from the terminal tip.
Dimension b applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSEY14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.
1.
NOTES:
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
BOTTOM VIEW
C0 . 2 REF
0 . 05 MAX.
0 . 00 MIN.
5
B
6
PIN 1
INDEX AREA
18
1
36 19
0.10 AMC B
4
A
4X 8.50
72X 0.40 72X 0.24
68X 0.50
10.00
10.00
0.90 Max
72X 0.24
72X 0.60
68X 0.50
6.00 Sq
9.80 Sq
6
PIN 1
INDEX AREA
Exp. DAP
6.00 Sq.
SEE DETAIL "X"
SEATING PLANE
0.08
0.10
C
C
C
(4X) 0.15
37
54
7255
Mouser Electronics
Authorized Distributor
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