DATASHEET 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Description Features/Benefits The 9FGV0241 is a 2-output very low power frequency generator for PCIe Gen 1, 2, 3 and 4 applications with integrated output terminations providing Zo=100. The device has 2 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off. * Integrated terminations provide 100 differential Zo; Recommended Application * PCIe Gen1-4 clock generation for Riser Cards, Storage, Networking, JBOD, Communications, Access Points * Output Features * * * * * 2 - 0.7V low-power HCSL-compatible (LP-HCSL) DIF * * pairs w/Zo=100 1 - 1.8V LVCMOS REF output w/Wake-On-LAN (WOL) support * Key Specifications * * * * * DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <50ps DIF phase jitter is PCIe Gen1-2-3-4 compliant REF phase jitter is <1.5ps RMS * * reduced component count and board space 1.8V operation; reduced power consumption OE# pins; support DIF power management LP-HCSL differential clock outputs; reduced power and board space Programmable Slew rate for each output; allows tuning for various line lengths Programmable output amplitude; allows tuning for various application environments DIF outputs blocked until PLL is locked; clean system start-up Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI External 25MHz crystal; supports tight ppm with 0 ppm synthesis error Configuration can be accomplished with strapping pins; SMBus interface not required for device control 3.3V tolerant SMBus interface works with legacy controllers Space saving 24-pin 4x4 mm VFQFPN; minimal board space Block Diagram vOE(1:0)# 2 REF XIN/CLKIN_25 IDT 603-25-150JA4C or 603-25-150JA4I 25MHz X2 DIF1 SSC Capable PLL vSADR vSS_EN_tri ^CKPWRGD_PD# SDATA_3.3 DIF0 Control Logic SCLK_3.3 IDT(R) 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 1 9FGV0241 JUNE 22, 2017 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR vOE1# VDD1.8 GND ^CKPWRGD_PD# vSS_EN_tri GNDXTAL Pin Configuration 24 23 22 21 20 19 X1_25 1 16 VDDA1.8 15 GNDA 14 DIF0# 13 DIF0 vOE0# 9 10 11 12 VDD1.8 8 GND 7 SCLK_3.3 GNDREF 5 GNDDIG 6 connect epad to GND SDATA_3.3 vSADR/REF1.8 4 9FGV0241 VDDDIG1.8 X2 2 VDDXTAL1.8 3 18 DIF1# 17 DIF1 24-pin VFQFPN, 4x4 mm, 0.5mm pitch ^ prefix indicates internal 120KOhm pull up resistor v prefix indicates internal 120KOhm pull down resistor SMBus Address Selection Table State of SADR on first application of CKPWRGD_PD# SADR 0 1 Address 1101000 1101010 + Read/Write Bit x x Power Management Table SMBus DIFx REF True O/P Comp. O/P OE bit 0 X Low Low Hi-Z1 1 1 Running Running Running 1 0 Low Low Low 1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when CKPWRG_PD# is low, REF is Low. CKPWRGD_PD# Power Connections Pin Number VDD 3 7 11,20 16 GND 5,24 6 10,21 15 Description XTAL, REF Digital Power DIF outputs PLL Analog IDT(R) 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 2 9FGV0241 JUNE 22, 2017 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Pin Descriptions Pin# Pin Name 1 X1_25 2 3 X2 VDDXTAL1.8 4 vSADR/REF1.8 5 6 7 8 9 10 11 GNDREF GNDDIG VDDDIG1.8 SCLK_3.3 SDATA_3.3 GND VDD1.8 12 vOE0# 13 14 15 16 17 18 DIF0 DIF0# GNDA VDDA1.8 DIF1 DIF1# 19 vOE1# 20 21 VDD1.8 GND 22 ^CKPWRGD_PD# 23 vSS_EN_tri 24 GNDXTAL Type IN OUT PWR LATCHED I/O GND GND PWR IN I/O GND PWR Pin Description Crystal input, Nominally 25.00MHz. Crystal output. Power supply for XTAL, nominal 1.8V Latch to select SMBus Address/1.8V LVCMOS copy of X1 pin. Ground pin for the REF outputs. Ground pin for digital circuitry 1.8V digital power (dirty power) Clock pin of SMBus circuitry, 3.3V tolerant. Data pin for SMBus circuitry, 3.3V tolerant. Ground pin. Power supply, nominal 1.8V Active low input for enabling DIF pair 0. This pin has an internal pull-down. IN 1 =disable outputs, 0 = enable outputs OUT Differential true clock output OUT Differential Complementary clock output GND Ground pin for the PLL core. PWR 1.8V power for the PLL core. OUT Differential true clock output OUT Differential Complementary clock output Active low input for enabling DIF pair 1. This pin has an internal pull-down. IN 1 =disable outputs, 0 = enable outputs PWR Power supply, nominal 1.8V GND Ground pin. Input notifies device to sample latched inputs and start up on first high assertion. IN Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal pull-up resistor. Latched select input to select spread spectrum amount at initial power up : LATCHED IN 1 = -0.5% spread, M = -0.25%, 0 = Spread Off GND GND for XTAL IDT(R) 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 3 9FGV0241 JUNE 22, 2017 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Test Loads Low-Power HCSL Differential Output Test Load 5 inches Rs Zo=100ohm 2pF Rs 2pF Device REF Output Test Load Zo = 50 ohms 33 5pF REF Output Alternate Terminations 3.3V Driving LVDS Cc R7a R7b R8a R8b Rs Zo Cc Rs Device LVDS Clock input Driving LVDS inputs with the 9FGV0241 Value Receiver has Receiver does not Component termination have termination Note R7a, R7b 10K ohm 140 ohm R8a, R8b 5.6K ohm 75 ohm Cc 0.1 uF 0.1 uF Vcm 1.2 volts 1.2 volts IDT(R) 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 4 9FGV0241 JUNE 22, 2017 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9FGV0241. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER SYMBOL CONDITIONS 1.8V Supply Voltage Input Voltage Input High Voltage, SMBus Storage Temperature Junction Temperature Input ESD protection VDDxx VIN VIHSMB Ts Tj ESD prot Applies to All VDD pins MIN -0.5 -0.5 TYP SMBus clock and data pins -65 Human Body Model MAX 2.5 VDD+0.3V 3.6V 150 125 2000 UNITS NOTES V V V C C V 1,2 1, 3 1 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. 3 Not to exceed 2.5V. Electrical Characteristics-Current Consumption TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS IDDAOP VDDA, PLL Mode, All outputs active @100MHz 7 8 mA 1 IDDOP VDD, All outputs active @100MHz 15 18 mA 1 Suspend Supply Current I DDSUSP VDDxxx, PD# = 0, Wake-On-LAN enabled 6 8 mA 1 Powerdown Current I DDPD PD#=0 0.6 1 mA 1, 2 Operating Supply Current MIN TYP MAX UNITS NOTES 1 Guaranteed by design and characterization, not 100% tested in production. Assuming REF is not running in power down state 2 Electrical Characteristics-Output Duty Cycle, Jitter, and Skew Characteristics TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Duty Cycle Skew, Output to Output Jitter, Cycle to cycle tDC tsk3 Measured differentially, PLL Mode VT = 50% PLL mode 45 50 34 14 55 50 50 % ps ps 1 1 1,2 tjcyc-cyc 1 Guaranteed by design and characterization, not 100% tested in production. Measured from differential waveform 2 IDT(R) 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 5 9FGV0241 JUNE 22, 2017 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Electrical Characteristics-Input/Supply/Common Parameters-Normal Operating Conditions TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL 1.8V Supply Voltage VDD Ambient Operating Temperature Input High Voltage Input Mid Voltage Input Low Voltage Schmitt Trigger Positive Going Threshold Voltage Schmitt Trigger Negative Going Threshold Voltage Hysteresis Voltage Output High Voltage Output Low Voltage Input Current Input Frequency Pin Inductance Capacitance CONDITIONS MAX UNITS NOTES 1.7 1.8 1.9 V 1 TCOM TIND VIH VIM VIL 0 -40 0.75 VDD 0.4 VDD -0.3 25 25 70 85 VDD + 0.3 0.6 VDD 0.25 VDD C C V V V 1 1 1 1 1 VT+ Single-ended inputs, where indicated 0.4 VDD 0.7 VDD V 1 VT- Single-ended inputs, where indicated 0.1 VDD 0.4 VDD V 1 VH VIH VIL IIN VT+ - VTSingle-ended outputs, except SMBus. I OH = -2mA Single-ended outputs, except SMBus. IOL = -2mA Single-ended inputs, VIN = GND, VIN = VDD 0.1 VDD VDD-0.45 0.4 VDD 1 1 1 1 IINP -5 0.45 5 V V V uA Single-ended inputs VIN = 0 V; Inputs with internal pull-up resistors VIN = VDD; Inputs with internal pull-down resistors -200 200 uA 1 XTAL, or X1 input 23 25 Logic Inputs, except DIF_IN Output pin capacitance From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock Allowable Frequency (Triangular Modulation) DIF start after OE# assertion DIF stop after OE# deassertion DIF output enable after PD# de-assertion Fall time of single-ended control inputs Rise time of single-ended control inputs VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V @ IPULLUP @ VOL 1.5 27 7 5 6 MHz nH pF pF 1 1 1 1 0.4 1.8 ms 1,2 31 31.6 32 kHz 1 2 3 4 clocks 1,3 4 300 us 1,3 5 5 0.8 3.6 0.4 1,2 1,2 1,4 1,5 1 1 1 1 1 1 Fin Lpin CIN COUT TSTAB SS Modulation Frequency f MOD OE# Latency tLATOE# Tdrive_PD# tDRVPD Tfall Trise SMBus Input Low Voltage SMBus Input High Voltage SMBus Output Low Voltage SMBus Sink Current Nominal Bus Voltage SCLK/SDATA Rise Time SCLK/SDATA Fall Time SMBus Operating Frequency tF tR VILSMB VIHSMB VOLSMB I PULLUP VDDSMB tRSMB t FSMB f MAXSMB (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) 3.6 1000 300 ns ns V V V mA V ns ns Maximum SMBus operating frequency 400 kHz 1 Guaranteed by design and characterization, not 100% tested in production. 2 Control input must be monotonic from 20% to 80% of input swing. 3 Time from deassertion until outputs are >200 mV For VDDSMB < 3.3V, VILSMB <= 0.35VDDSMB 5 TYP Supply voltage for core, analog and single-ended LVCMOS outputs Commercial range Industrial range Single-ended inputs, except SMBus Single-ended tri-level inputs ('_tri' suffix, if present) Single-ended inputs, except SMBus Clk Stabilization 4 MIN 2.1 4 1.7 For VDDSMB < 3.3V, VIHSMB >= 0.65VDDSMB IDT(R) 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 6 9FGV0241 JUNE 22, 2017 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Electrical Characteristics-DIF 0.7V Low Power HCSL Outputs TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL Slew rate Trf Slew rate matching Trf Voltage High V HIGH CONDITIONS MIN TYP Scope averaging on 3.0V/ns setting Scope averaging on 2.0V/ns setting Slew rate matching, Scope averaging on 2 1.5 3.1 2.3 3 4.3 3.5 20 660 794 850 Voltage Low VLOW Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) Max Voltage Min Voltage Vswing Crossing Voltage (abs) Crossing Voltage (var) Vmax Vmin Vswing Vcross_abs -Vcross Measurement on single ended signal using absolute value. (Scope averaging off) Scope averaging off Scope averaging off Scope averaging off MAX UNITS NOTES V/ns V/ns % 1, 2, 3 1, 2, 3 1,2,4 1,7 mV -150 21 150 816 -15 1551 397 15 1150 -300 300 300 550 140 1 mV mV mV mV 1 1 1,2 1,5 1,6 1 Guaranteed by design and characterization, not 100% tested in production. Measured from differential waveform 2 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute. 7 At default SMBus settings. Electrical Characteristics-Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions SYMBOL PARAMETER CONDITIONS t jphPCIeG1-CC PCIe Gen 1 PCIe Gen 2 Low Band 10kHz < f < 1.5MHz (PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz) t jphPCIeG2-CC PCIe Gen 2 High Band Phase Jitter, 1.5MHz < f < Nyquist (50MHz) PLL Mode (PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz) PCIe Gen 3 t jphPCIeG3-CC (PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz) PCIe Gen 4 t jphPCIeG4-CC (PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz) Notes on PCIe Filtered Phase Jitter Tables 1 Applies to all differential outputs, guaranteed by design and characterization. 2 Calculated from Intel-supplied Clock Jitter Tool, with spread on and off. 3 Specification UNITS NOTES Limit 86 ps (p-p) 1, 2, 3 MIN TYP MAX 21 25 35 0.9 0.9 1.1 3 ps (rms) 1, 2 1.5 1.6 1.9 3.1 ps (rms) 1, 2 0.3 0.37 0.44 1 0.3 0.37 0.44 0.5 ps (rms) ps (rms) 1, 2 1, 2 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12. IDT(R) 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 7 9FGV0241 JUNE 22, 2017 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Electrical Characteristics-REF TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP 0 Long Accuracy ppm see Tperiod min-max values Clock period Tperiod 25 MHz output nominal 40 Rise/Fall Slew Rate t rf1 Byte 3 = 1F, VOH = VDD-0.45V, VOL = 0.45V 0.5 1 Rise/Fall Slew Rate t rf1 Byte 3 = 5F, VOH = VDD-0.45V, VOL = 0.45V 0.5 1.6 Byte 3 = 9F, VOH = VDD-0.45V, VOL = 0.45V 0.5 2 Rise/Fall Slew Rate t rf1 Rise/Fall Slew Rate t rf1 Byte 3 = DF, VOH = VDD-0.45V, VOL = 0.45V 0.5 2.1 Duty Cycle dt1 VT = VDD/2 V 45 53.1 Duty Cycle Distortion dtcd VT = VDD/2 V 0 2 Jitter, cycle to cycle tjcyc-cyc VT = VDD/2 V 19 Noise floor t jdBc1k 1kHz offset -130 Noise floor t jdBc10k 10kHz offset to Nyquist -140 Jitter, phase t jphREF 12kHz to 5MHz 0.63 MAX 2.5 2.5 2.5 2.5 55 4 250 -105 -120 1.5 UNITS ppm ns V/ns V/ns V/ns V/ns % % ps dBc dBc ps (rms) Notes 1,2 1,2 1,3 1,3 1,3 1,3 1,4 1,5 1,4 1,4 1,4 1,4 1 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz 3 Typical value occurs when REF slew rate is set to default value 4 When driven by a crystal. 5 When driven by an external oscillator via the X1 pin. X2 should be floating in this case. 2 Clock Periods-Differential Outputs with Spread Spectrum Disabled SSC OFF Center Freq. MHz DIF 100.00 Measurement Window 1us 0.1s 0.1s 0.1s - ppm -SSC + ppm -c2c jitter 0 ppm Short-Term Long-Term Long-Term Period AbsPer Average Average Average Nominal Min Min Min Max 9.94900 9.99900 10.00000 10.00100 1 Clock 1us +SSC Short-Term Average Max 1 Clock +c2c jitter Units Notes AbsPer Max 10.05100 ns 1,2 Clock Periods-Differential Outputs with -0.5% Spread Spectrum Enabled SSC ON Center Freq. MHz DIF 99.75 Measurement Window 1us 0.1s 0.1s 0.1s - ppm -SSC + ppm -c2c jitter 0 ppm Short-Term Long-Term Long-Term AbsPer Period Average Average Average Min Nominal Min Min Max 9.94906 9.99906 10.02406 10.02506 10.02607 1 Clock 1us +SSC Short-Term Average Max 10.05107 1 Clock +c2c jitter Units Notes AbsPer Max 10.10107 ns 1,2 1 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz 2 IDT(R) 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 8 9FGV0241 JUNE 22, 2017 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR General SMBus Serial Interface Information How to Write How to Read * * * * * * * * * * * * * * * * * * * * * Controller (host) sends a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 IDT clock will acknowledge each byte one at a time Controller (host) sends a Stop bit Index Block Write Operation Controller (Host) T Index Block Read Operation IDT (Slave/Receiver) Controller (Host) starT bit T Slave Address WR * * * Controller (host) will send a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N+X-1 IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit IDT (Slave/Receiver) starT bit Slave Address WRite ACK WR WRite ACK Beginning Byte = N ACK Beginning Byte = N ACK Data Byte Count = X ACK RT Slave Address Beginning Byte N ACK X Byte O O O Repeat starT RD ReaD ACK O Data Byte Count=X O O ACK ACK ACK Beginning Byte N Byte N + X - 1 stoP bit O Note: Read/Write address is determined by SADR latch. O X Byte P O O O O Byte N + X - 1 IDT(R) 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR N Not acknowledge P stoP bit 9 9FGV0241 JUNE 22, 2017 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR SMBus Table: Output Enable Register Byte 0 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 DIF OE1 Bit 2 DIF OE0 Bit 1 Bit 0 Control Function Reserved Reserved Reserved Reserved Reserved Output Enable Output Enable Reserved SMBus Table: SS Readback and Vhigh Control Register Byte 1 Name Control Function SSENRB1 SS Enable Readback Bit1 Bit 7 SSENRB1 SS Enable Readback Bit0 Bit 6 Bit 5 SSEN_SWCNTRL Enable SW control of SS SSENSW1 SS Enable Software Ctl Bit1 Bit 4 SSENSW0 SS Enable Software Ctl Bit0 Bit 3 Reserved Bit 2 AMPLITUDE 1 Bit 1 Controls Output Amplitude AMPLITUDE 0 Bit 0 1. B1[5] must be set to a 1 for these bits to have any effect on the part. SMBus Table: DIF Slew Rate Control Register Byte 2 Name Control Function Reserved Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 SLEWRATESEL DIF1 Adjust Slew Rate of DIF1 Bit 2 SLEWRATESEL DIF0 Adjust Slew Rate of DIF0 Bit 1 Reserved Bit 0 SMBus Table: REF Control Register Byte 3 Name Bit 7 REF Bit 6 Bit 5 REF Power Down Function Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REF OE Control Function Slew Rate Control Wake-on-Lan Enable for REF REF Output Enable Reserved Reserved Reserved Reserved Type 0 1 RW RW Low/Low Low/Low Enabled Enabled Type 0 1 00' for SS_EN_tri = 0, '01' for SS_EN_tri R = 'M', '11 for SS_EN_tri = '1' R RW SS control locked Values in B1[4:3] control SS amount. RW 1 RW 1 00' = SS Off, '01' = -0.25% SS, '10' = Reserved, '11'= -0.5% SS RW RW 00 = 0.6V 10= 0.8V 01 = 0.7V 11 = 0.9V Type 0 1 RW RW 2.0V/ns 2.0V/ns 3.0V/ns 3.0V/ns Type RW RW 0 1 00 = Slowest 01 = Slow 10 = Fast 11 = Faster REF does not run in REF runs in Power RW Power Down Down RW Low Enabled Default 1 1 1 1 1 1 1 1 Default Latch Latch 0 0 0 1 1 0 Default 1 1 1 1 1 1 1 1 Default 0 1 0 1 1 1 1 1 Byte 4 is reserved and reads back 'hFF'. IDT(R) 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 10 9FGV0241 JUNE 22, 2017 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR SMBus Table: Revision and Vendor ID Register Byte 5 Name Control Function RID3 Bit 7 RID2 Bit 6 Revision ID RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VENDOR ID VID1 Bit 1 VID0 Bit 0 Type R R R R R R R R SMBus Table: Device Type/Device ID Byte 6 Name Device Type1 Bit 7 Device Type0 Bit 6 Device ID5 Bit 5 Device ID4 Bit 4 Device ID3 Bit 3 Device ID2 Bit 2 Device ID1 Bit 1 Device ID0 Bit 0 Type R R R R R R R R SMBus Table: Byte Count Register Byte 7 Name Bit 7 Bit 6 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 Control Function Device Type Device ID Control Function Reserved Reserved Reserved Byte Count Programming 0 A rev = 0000 0001 = IDT 0 1 00 = FGV, 01 = DBV, 10 = DMV, 11= Reserved 00010 binary or 02 hex Type RW RW RW RW RW 1 0 1 Writing to this register will configure how many bytes will be read back, default is = 8 bytes. Default 0 0 0 0 0 0 0 1 Default 0 0 0 0 0 0 1 0 Default 0 0 0 0 1 0 0 0 Recommended Crystal Characteristics (3225 package) PARAMETER VALUE UNITS NOTES Frequency Resonance Mode Frequency Tolerance @ 25C Frequency Stability, ref @ 25C Over Operating Temperature Range Temperature Range (commercial) Temperature Range (industrial) Equivalent Series Resistance (ESR) Shunt Capacitance (CO) Load Capacitance (CL) Drive Level Aging per year Notes: 1. FOX 603-25-150. 2. For I-temp, FOX 603-25-261. 25 Fundamental 20 MHz PPM Max 1 1 1 20 PPM Max 1 0~70 -40~85 50 7 8 0.3 5 C C Max pF Max pF Max mW Max PPM Max 1 2 1 1 1 1 1 IDT(R) 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 11 9FGV0241 JUNE 22, 2017 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Thermal Characteristics PARAMETER SYMBOL CONDITIONS Thermal Resistance JC Jb JA0 JA1 JA3 JA5 Junction to Case Junction to Base Junction to Air, still air Junction to Air, 1 m/s air flow Junction to Air, 3 m/s air flow Junction to Air, 5 m/s air flow TYP UNITS NOTES VALUE 62 C/W 1 C/W 5.4 1 50 C/W 1 NLG20 NLG24 43 C/W 1 39 C/W 1 38 C/W 1 PKG 1 ePad soldered to board Marking Diagrams LOT 241AL YYWW LOT 241AIL YYWW Notes: 1. `LOT' is the lot number. 2. `YYWW' is the last two digits of the year and week that the part was assembled. 3. `L' denotes RoHS compliant package. 4. `I' denotes industrial temperature grade. IDT(R) 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 12 9FGV0241 JUNE 22, 2017 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Package Outline and Dimensions (NLG24) IDT(R) 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 13 9FGV0241 JUNE 22, 2017 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Package Outline and Dimensions (NLG24), cont. IDT(R) 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 14 9FGV0241 JUNE 22, 2017 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Ordering Information Part / Order Number Shipping Packaging 9FGV0241AKLF Tubes 9FGV0241AKLFT Tape and Reel 9FGV0241AKILF Tubes 9FGV0241AKILFT Tape and Reel Package 24-pin VFQFPN 24-pin VFQFPN 24-pin VFQFPN 24-pin VFQFPN Temperature 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. "A" is the device revision designator (will not correlate with the datasheet revision). Revision History Rev. E F G H J Issue Date Initiator Description Updated IDDAOP and IDDOP typ and max specs per latest 2/3/2015 RDW characterization review. 11/30/2015 RDW Updated block diagram 1/4/2016 RDW Corrected typo in ordering information; changed rev "B" to rev "A" 10/18/2016 RDW Removed IDT crystal part number Updated front page Gendes to reflect the PCIe Gen4 updates. 6/19/2017 RG Updated Electrical Characteristics - Filtered Phase Jitter Parameters PCIe Common Clocked (CC) Architectures and added PCIe Gen4 Data IDT(R) 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 15 9FGV0241 Page # 5 1 13 1,7 JUNE 22, 2017 9FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR SYNTHESIZERS Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 www.idt.com/go/sales www.idt.com/go/support Corporate Headquarters Integrated Device Technology, Inc. www.idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as "IDT") reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. 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