9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 7
9FGV0241 JUNE 22, 2017
Electrical Characteristics–DIF 0.7V Low Power HCSL Outputs
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common
Clocked (CC) Architectures
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Scope avera
in
on 3.0V/ns settin
23.14.3
1, 2, 3
Scope avera
in
on 2.0V/ns settin
1.5 2.3 3.5
1, 2, 3
Δ
Trf Slew rate matching, Scope averaging on 320 %1,2,4
Voltage High VHI GH 660 794 850 1,7
Voltage Low VLOW -150 21 150 1
Max Voltage Vmax 816 1150 1
Min Voltage Vmin -300 -15 1
Vswing Vswing Scope averaging off 300 1551 mV 1,2
Crossin
Volta
e (abs) Vcross_abs Scope avera
in
off 300
550 mV 1,5
Crossing Voltage (var) Δ-Vcross Scope averaging off 15 140 mV 1,6
2
Measured from differential waveform
7 At default SMBus settings.
Measurement on single ended signal using
absolute value. (Scope averaging off) mV
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
Slew rate Trf
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting ∆-Vcross to be smaller than Vcross absolute.
1Guaranteed by design and characterization, not 100% tested in production.
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
mV
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
SYMBOL PARAMETER CONDITIONS MIN TYP MAX Specification
Limit
UNITS NOTES
tjphPCIeG1-CC PCIe Gen 1 212535 86ps (p-p)1, 2, 3
PCIe Gen 2 Low Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
0.9 0.9 1.1 3 ps
(rms) 1, 2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
1.5 1.6 1.9 3.1 ps
(rms) 1, 2
tjphPCIeG3-CC
PCIe Gen 3
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
(rms)
1, 2
tjphPCIeG4-CC
PCIe Gen 4
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz) 0.3 0.37 0.44 0.5 ps
(rms) 1, 2
Notes on PCIe Filtered Phase Jitter Tables
1
Applies to all differential outputs,
uaranteed by desi
n and characterization.
Phase Jitter,
PLL Mode
tjphPCIeG2-CC
2 Calculated from Intel-supplied Clock Jitter Tool, with spread on and off.
Sample size of at least 100K cycles. This fi
ure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1
.