Altera Corporation Section II–1
Preliminary
Section II. HardCopy
APEX Device Family Data
Sheet
This section provides designers with the data sheet specifications for
HardCopy® APEXTM devices. These chapters contain feature definitions
of the internal architecture, configuration and JTAG boundary-scan
testing information, DC operating conditions, AC timing parameters, a
reference to power consumption, and ordering information for
HardCopy APEX devices.
This section contains the following:
■Chapter 7, Introduction to HardCopy APEX Devices
■Chapter 8, Description, Architecture, and Features
■Chapter 9, Boundary-Scan Support
■Chapter 10, Operating Conditions
Revision History Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the complete handbook.
Section II–2 Altera Corporation
Preliminary
Revision History HardCopy Series Handbook, Volume 1
Altera Corporation 7–1
September 2008
7. Introduction to
HardCopy APEX Devices
Introduction HardCopy® APEXTM devices enable high-density APEX 20KE device
technology to be used in high-volume applications where significant cost
reduction is desired. HardCopy APEX devices are physically and
functionally compatible with APEX 20KC and APEX 20KE devices. They
combine the time-to-market advantage, performance, and flexibility of
APEX 20KE devices with the ability to move to high-volume, low-cost
devices for production. The migration process from an APEX 20KE
device to a HardCopy APEX device is fully automated, with designer
involvement limited to providing a few Quartus®II software-generated
output files.
Features... HardCopy APEX devices are manufactured using an 0.18-μm CMOS
six-layer-metal process technology:
■Preserves functionality of a configured APEX 20KC or APEX 20KE
device
■Pin-compatible with APEX 20KC or APEX 20KE devices
■Meets or exceeds timing of configured APEX 20KE and APEX 20KC
devices
■Optional emulation of original programmable logic device (PLD)
programming sequence
■High-performance, low-power device
■MultiCore architecture integrating embedded memory and look-up
table (LUT) logic used for register-intensive functions
■Embedded system blocks (ESBs) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port RAM,
and content-addressable memory (CAM)
■Customization performed through metallization layers
H51006-2.3
7–2 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
High-density architecture:
■400,000 to 1.5 million typical gates (Table 7–1)
■Up to 51,840 logic elements (LEs)
■Up to 442,368 RAM bits that can be used without reducing available
logic
...and More
Features
Low-power operation:
■1.8-V supply voltage (Table 7–2)
■MultiVolt I/O support for 1.8-, 2.5-, and 3.3-V interfaces
■ESBs offering power-saving mode
Flexible clock management circuitry with up to four phase-locked loops
(PLLs):
■Built-in low-skew clock tree
■Up to eight global clock signals
■ClockLock feature reducing clock delay and skew
■ClockBoost feature providing clock multiplication and division
■ClockShift feature providing clock phase and delay shifting
Powerful I/O features:
■Compliant with peripheral component interconnect Special Interest
Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V
operation at 33 or 66 MHz and 32 or 64 bits
Table 7–1. HardCopy APEX Device Features Note (1)
Feature HC20K400 HC20K600 HC20K1000 HC20K1500
Maximum system gates 1,052,000 1,537,000 1,772,000 2,392,000
Typical gates 400,000 600,000 1,000,000 1,500,000
LEs 16,640 24,320 38,400 51,840
ESBs 104 152 160 216
Maximum RAM bits 212,992 311,296 327,680 442,368
Phase-locked loops (PLLs) 4 4 4 4
Maximum macrocells 1,664 2,432 2,560 3,456
Maximum user I/O pins 488 588 708 808
Note to Table 7–1:
(1) The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to
57,000 additional gates.
Altera Corporation 7–3
September 2008
...and More Features
■Support for high-speed external memories, including double-data
rate (DDR), synchronous dynamic RAM (SDRAM), and
zero-bus-turnaround (ZBT) static RAM (SRAM)
■16 input and 16 output LVDS channels
■Fast tCO and tSU times for complex logic
■MultiVolt I/O support for 1.8-V, 2.5-V, and 3.3-V interfaces
■Individual tri-state output enable control for each pin
■Output slew-rate control to reduce switching noise
■Support for advanced I/O standards, including LVDS, LVPECL,
PCI-X, AGP, CTT, SSTL-3 and SSTL-2, GTL+, and HSTL Class I
■Supports hot-socketing operation
HardCopy APEX device implementation features:
■Customized interconnect for each design
■HardCopy APEX devices preserve APEX 20K device MegaLAB
structure, LEs, ESBs, I/O element (IOE), PLLs, and LVDS circuitry
■Up to four metal layers customizable for customer designs
■Completely automated proprietary design migration flow
●Testability analysis and fix
●Automatic test pattern generation (ATPG)
●Automatic place and route
●Static timing analysis
●Static functional verification
●Physical verification
Table 7–2. HardCopy APEX Device Supply Voltages
Feature Voltage
Internal supply voltage (VCCINT)1.8 V
MultiVolt I/O interface voltage levels (VCCIO) 1.8 V, 2.5 V, 3.3 V, 5.0 V (1)
Note to Table 7–2:
(1) HardCopy APEX devices can be 5.0-V tolerant by using an external resistor.
7–4 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
Tables 7–3 through 7–6 show the HardCopy APEX device ball-grid array
(BGA) and FineLine BGA package options, I/O counts, and sizes.
Table 7–3. HardCopy APEX Device BGA Package Options and I/O Count
Note (1)
Device 652-Pin BGA
HC20K400 488
HC20K600 488
HC20K1000 488
HC20K1500 488
Table 7–4. HardCopy APEX Device FineLine BGA Package Options and I/O
Count Note (1)
Device 672-Pin 1,020-Pin
HC20K400 488 –
HC20K600 508 588
HC20K1000 508 708
HC20K1500 – 808
Note to Tables 7–3 and 7–4:
(1) I/O counts include dedicated input and clock pins.
Table 7–5. HardCopy APEX Device BGA Package Sizes
Feature 652-Pin BGA
Pitch (mm) 1.27
Area (mm2)2,025
Length × width (mm × mm) 45.0 × 45.0
Table 7–6. HardCopy APEX Device FineLine BGA Package Sizes
Feature 672-Pin 1,020-Pin
Pitch (mm) 1.00 1.00
Area (mm2)729 1,089
Length × width (mm × mm) 27 × 27 33 × 33
Altera Corporation 7–5
September 2008
Document Revision History
Document
Revision History
Table 7–7 shows the revision history for this chapter.
Table 7–7. Document Revision History
Date and Document
Version Changes Made Summary of Changes
September 2008,
v2.3
Updated chapter number and metadata. —
June 2007, v2.2 Minor text edits. —
December 2006
v2.1
Updated revision history. —
March 2006 Formerly chapter 9; no content change. —
January 2005
v2.0
Update device names and other minor textual changes —
June 2003
v1.0
Initial release of Chapter 9, Introduction to HardCopy APEX
Devices, in the HardCopy Device Handbook
—
7–6 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
Altera Corporation 8–1
September 2008
8. Description, Architecture,
and Features
Introduction HardCopy® APEXTM devices extend the flexibility of high-density FPGAs
to a cost-effective, high-volume production solution. The migration
process from an Altera® FPGA to a HardCopy APEX device offers
seamless migration of a high-density system-on-a-programmable-chip
(SOPC) design to a low-cost alternative device with minimal risk. Using
HardCopy APEX devices, Altera’s SOPC solutions can be leveraged from
prototype to production, while reducing costs and speeding
time-to-market.
A significant benefit of HardCopy devices is that customers do not need
to be involved in the device migration process. Unlike
application-specific integrated circuit (ASIC) development, the
HardCopy design flow does not require generation of test benches, test
vectors, or timing and functional simulation. The HardCopy migration
process only requires the Quartus®II software-generated output files
from a fully functional APEX 20KE or APEX 20KC device. Altera
performs the migration and delivers functional prototypes in as few as
seven weeks.
A risk-free alternative to ASICs, HardCopy APEX devices are
customizable, full-featured devices created by Altera’s proprietary
design migration methodology. They are based on Altera’s
industry-leading high-density device architecture and use an
area-efficient sea-of-logic-elements (SOLE) core.
HardCopy APEX devices retain all the same features as the APEX 20KE
and APEX 20KC devices, which combine the strength of LUT-based and
product-term-based devices in conjunction with the same embedded
memory structures. All routing resources that were programmable in the
APEX 20K device family are replaced by custom interconnect, resulting in
a considerable die size reduction and subsequent cost saving.
The SRAM configuration cells of the original FPGA are replaced in
HardCopy APEX devices by metal elements, which define the function of
each logic element (LE), embedded memory, and I/O cell in the device.
These resources are connected to each other using the same metallization
layers. Once a HardCopy APEX device has been manufactured, the
functionality of the device is fixed and no programming is possible.
Altera performs the migration of the original FPGA design to an
equivalent HardCopy APEX device using a proprietary design migration
flow.
H51007-2.3
8–2 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
The migration of a FPGA to a HardCopy APEX device begins with a user
design that has been implemented in an APEX 20KE or APEX 20KC
device. Table 8–1 shows the device equivalence for HardCopy and
APEX 20KE or APEX 20KC devices.
1To ensure HardCopy device performance and functionality, the
APEX 20K design must be completely debugged before
committing the design to HardCopy device migration.
HardCopy APEX device implementation begins with extracting the
Quartus II software-generated SRAM Object File (.sof) and converting its
connectivity information into a structural Verilog HDL netlist. This netlist
is then placed and routed in a similar fashion to a gate array. There are no
dedicated routing channels. The router can exploit all available metal
layers (up to four) and route over LE cells and other functional blocks.
Altera’s proprietary architecture and design methodology will guarantee
virtually 100% routing of any APEX 20KE or APEX 20KC design
compiled and fitted successfully using the Quartus II software. Place and
route is timing-driven and will comply with the timing constraints of the
original FPGA design as specified in the Quartus II software. Figure 8–1
shows a diagram of the HardCopy APEX device architecture.
Table 8–1. HardCopy and APEX 20KE or APEX 20C Device Equivalence
HardCopy APEX Device APEX 20KE Device APEX 20KC Device
HC20K1500 EP20K1500E EP20K1500C
HC20K1000 EP20K1000E EP20K1000C
HC20K600 EP20K600E EP20K600C
HC20K400 EP20K400E EP20K400C
Altera Corporation 8–3
September 2008
Introduction
Figure 8–1. HardCopy APEX Device Architecture
The strip of auxiliary gates (SOAG) is an Altera proprietary feature
designed into the HardCopy APEX device and is used during the
HardCopy device implementation process. The SOAG structures can be
configured into several different types of functions through the use of
metallization. For example, high fanout signals require adequate
buffering, so buffers are built out of SOAG cells for this purpose.
HardCopy APEX devices include the same advanced features as the
APEX 20KE and APEX 20KC devices, such as enhanced I/O standard
support, content-addressable memory (CAM), additional global clocks,
and enhanced ClockLock circuitry. Table 8–2 lists the features included in
HardCopy APEX devices.
I/O Elements
PLLs
ESB
Strip of auxiliary
gates (SOAG)
LE LAB
Table 8–2. HardCopy APEX Device Features (Part 1 of 2)
Feature HardCopy Devices
MultiCore system integration Full support
Hot-socketing support Full support
32-/64-bit, 33-MHz PCI Full compliance
32-/64-bit, 66-MHz PCI Full compliance
MultiVolt I/O operation 1.8-V, 2.5-V, or 3.3-V VCCIO
VCCIO
selected bank by bank
5.0-V tolerant with use of external resistor
8–4 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
All HardCopy APEX devices are tested using automatic test pattern
generation (ATPG) vectors prior to shipment. For fully synchronous
designs near 100%, fault coverage can be achieved through the built-in
full-scan architecture. ATPG vectors allow the designer to focus on
simulation and design verification.
Because the configuration of HardCopy APEX devices is built-in during
manufacture, they cannot be configured in-system. However, if the
APEX 20KE or APEC 20KC device configuration sequence must be
emulated, the HardCopy APEX device has this capability.
fAll of the device features of APEX 20KE and APEX 20KC devices are
available in HardCopy APEX devices. For a detailed description of these
device features, refer to the APEX 20K Programmable Logic Device Family
Data Sheet and the APEX 20KC Programmable Logic Device Family Data
Sheet.
ClockLock support Clock delay reduction
m/(n × v) clock multiplication
Drive ClockLock output off-chip
External clock feedback
ClockShift circuitry
LVDS support
Up to four PLLs
ClockShift, clock phase adjustment
Dedicated clock and input pins Eight
I/O standard support 1.8-V, 2.5-V, 3.3-V, 5.0-V I/O
3.3-V PCI and PCI-X
3.3-V AGP
CTT
GTL+
LV CM O S
LV TT L
True-LVDS and LVPECL data pins
LVDS and LVPECL clock pins
HSTL class I
PCI-X
SSTL-2 class I and II
SSTL-3 class I and II
Memory support CAM
Dual-port RAM
FIFO
RAM
ROM
Table 8–2. HardCopy APEX Device Features (Part 2 of 2)
Feature HardCopy Devices
Altera Corporation 8–5
September 2008
Differences Between HardCopy APEX and APEX 20K FPGAs
Differences
Between
HardCopy APEX
and APEX 20K
FPGAs
Several differences must be considered before a design is ready for
implementation in HardCopy technology:
■HardCopy APEX devices are only customizable at the time they are
manufactured. Make sure that the original APEX 20KE or
APEX 20KC device has undergone thorough testing in the
end-system before deciding to proceed with migration to a
HardCopy APEX device, because no changes can be made to the
HardCopy APEX device after it has been manufactured.
■ESBs that are configured as RAM or CAM will power-up
un-initialized in the HardCopy APEX device. In the FPGA it is
possible to configure, or “pre-load,” the ESB memory as part of the
configuration sequence, then overwrite it when the device is in
normal functional mode. This pre-loaded memory feature of the
FPGA is not available in HardCopy devices. If a design contains
RAM or CAM with assumed data values at power-up, then the
HardCopy APEX device will not operate as expected. If a design uses
this feature, it should be re-compiled without the memory pre-load.
ESBs configured as ROM are fully supported.
■The JTAG boundary scan order in the HardCopy APEX device is
different compared to the APEX 20K device. A HardCopy BSDL file
that describes the re-ordered boundary scan chain should be used.
1The BSDL files for HardCopy APEX devices are different
from the corresponding APEX 20KE or APEX 20KC
devices. Download the correct HardCopy BSDL file from
Altera’s website at www.altera.com.
■The advanced 0.18-μm aluminum metal process is used to support
both APEX 20KE and APEX 20KC devices. The performance
improvement achieved by the die size reduction and metal
interconnect optimization more than offsets the need for copper in
this case. Altera guarantees that a target HardCopy APEX device will
provide the same or better performance as in the corresponding
APEX 20KE or APEX 20KC device.
Power-up Mode
and
Configuration
Emulation
Unlike their FPGA counterparts, HardCopy APEX devices do not need to
be configured. However, to facilitate seamless migration, configuration
can be emulated in these devices. There are three modes in which a
8–6 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
HardCopy APEX device can be prepared for operation after power up:
instant on, instant on after 50 ms, and configuration emulation. Each
mode is described below.
■In instant on mode, the HardCopy APEX device is available for use
shortly after the device receives power. The on-chip power-on-reset
(POR) circuit will set or reset all registers. The CONF_DONE output
will be tri-stated once the power-on reset has elapsed. No
configuration device or configuration input signals are necessary.
■In instant on after 50 ms mode, the HardCopy APEX device performs
in a similar fashion to the Instant On mode, except that there is an
additional delay of 50 ms (nominal), during which time the device is
held in reset stage. The CONF_DONE output is pulled low during this
time and then tri-stated after the 50 ms have elapsed. No
configuration devices or configuration input signals are necessary
for this option.
■In configuration emulation mode, the HardCopy APEX device
undergoes an emulation of a full configuration sequence as if
configured by an external processor or an EPC device. In this mode,
the CONF_DONE signal is tri-stated after the correct number of clock
cycles. This mode may be useful where there is some dependency on
the configuration sequence (for example, multi-device configuration
or processor initialization). In this mode, the device expects to see all
configuration control and data input signals.
Speed Grades Because HardCopy APEX devices are customized, no speed grading is
performed. All HardCopy APEX devices will meet the timing
requirements of the original FPGA of the fastest speed grade. Generally,
HardCopy APEX devices will have a higher fMAX than the corresponding
FPGA, but the speed increase will vary on a design-by-design basis.
Quartus II-
Generated
Output Files
The HardCopy migration process requires several Quartus II
software-generated files. These key output files are listed and explained
below.
■The SRAM Object File (.sof) contains all of the necessary information
needed to configure a FPGA
■The Compiler Report File (.csf.rpt) is parsed to extract useful
information about the design
■The Verilog atom-based netlist file (.vo) is used to check the
HardCopy netlist
■The pin out information file (.pin) contains user signal names and
I/O configuration information
Altera Corporation 8–7
September 2008
Document Revision History
■The Delay Information File (.sdo) is used to check the original FPGA
timing
■A completed HardCopy timing requirements file describes all
necessary timing information on the design. A template of this text
file is available for download from the Altera website at
www.altera.com.
The migration process consists of several steps. First, a netlist is
constructed from the SOF. Then, the netlist is checked to ensure that the
built-in scan test structures will operate correctly. The netlist is then fed
into a place-and-route engine, and the design interconnect is generated.
Static timing analysis ensures that all timing constraints are met, and
static functional verification techniques are employed to ensure correct
device migration. After successfully completing these stages, physical
verification of the device takes place, and the metal mask layers are taped
out to fabricate HardCopy APEX devices.
Document
Revision History
Table 8–3 shows the revision history for this chapter.
Table 8–3. Document Revision History
Date and Document
Version Changes Made Summary of Changes
September 2008,
v2.3
Updated chapter number and metadata. —
June 2007, v2.2 Minor text edits. —
December 2006
v2.1
Updated revision history. —
March 2006 Formerly chapter 10; no content change. —
January 2005
v2.0
Update device names and other minor textual changes —
June 2003
v1.0
Initial release of Chapter 10, Description, Architecture and
Features, in the HardCopy Device Handbook
—
8–8 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
Altera Corporation 9–1
September 2008
9. Boundary-Scan Support
IEEE Std. 1149.1
(JTAG)
Boundary-Scan
Support
All HardCopy devices provide JTAG boundary-scan test (BST) circuitry
that complies with the IEEE Std. 1149.1-1990 specification. HardCopy®
APEX™ devices support the JTAG instructions shown in Table 9–1.
1The BSDL files for HardCopy devices are different from the
corresponding APEX 20KE or APEX 20KC parts. Download the
correct HardCopy BSDL file from Altera’s website at
www.altera.com.
HardCopy APEX devices instruction register length is 10 bits; the
USERCODE register length is 32 bits. Tables 9–2 and 9–3 show the
boundary-scan register length and device IDCODE information for
HardCopy devices.
Table 9–1. HardCopy APEX JTAG Instructions
JTAG Instruction Description
SAMPLE/PRELOAD SAMPLE/PRELOAD allows a snapshot of signals at the device pins to be
captured and examined during normal device operation and permits an initial
data pattern to be output at the device pins. It is also used by the SignalTap®
embedded logic analyzer.
EXTEST Allows the external circuitry and board-level interconnections to be tested by
forcing a test pattern at the output pins and capturing test results at the input pins.
BYPASS Places the 1-bit bypass register between the TDI and TDO pins, which allows the
BST data to pass synchronously through selected devices to adjacent devices
during normal device operation.
USERCODE Selects the 32-bit USERCODE register and places it between the TDI and TDO
pins, allowing the USERCODE to be serially shifted out of TDO.
IDCODE Selects the IDCODE register and places it between the TDI and TDO pins,
allowing the IDCODE to be serially shifted out of TDO.
H51009-2.3
9–2 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
Figure 9–1 shows the timing requirements for the JTAG signals.
Figure 9–1. HardCopy JTAG Waveforms
Table 9–2. HardCopy APEX Boundary-Scan Register Length
Device Boundary-Scan Register Length
HC20K400 1,506
HC20K600 1,806
HC20K1000 2,190
HC20K1500 2,502
Table 9–3. 32-Bit HardCopy APEX Device IDCODE
Device
IDCODE (32 Bits) Note (1)
Version
(4 Bits) Part Number (16 Bits) Manufacturer
Identity (11 Bits)
1 (1 Bit)
(2)
HC20K400 0000 1000 0100 0000 0000 000 0110 1110 1
HC20K600 0000 1000 0110 0000 0000 000 0110 1110 1
HC20K1000 0000 1001 0000 0000 0000 000 0110 1110 1
HC20K1500 0000 1001 0101 0000 0000 000 0110 1110 1
Notes to Tab l e 9 –3 :
(1) The most significant bit (MSB) is on the left.
(2) The IDCODE’s least significant bit (LSB) is always 1.
TDO
TCK
t
JPZX
t
JPCO
t
JPH
t
JPXZ
t
JCP
t
JPSU
t
JCL
t
JCH
TDI
TMS
Signal
to Be
Captured
Signal
to Be
Driven
t
JSZX
t
JSSU
t
JSH
t
JSCO
t
JSXZ
Altera Corporation 9–3
September 2008
Document Revision History
Table 9–4 shows the JTAG timing parameters and values for HardCopy
devices.
fFor more information about using JTAG BST circuitry in Altera devices,
refer to Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing
in Altera Devices.
Document
Revision History
Table 9–5 shows the revision history for this chapter.
Table 9–4. HardCopy APEX JTAG Timing Parameters and Values
Symbol Parameter Min Max Unit
tJCP TCK clock period 100 ns
tJCH TCK clock high time 50 ns
tJCL TCK clock low time 50 ns
tJPSU JTAG port setup time 20 ns
tJPH JTAG port hold time 45 ns
tJPCO JTAG port clock to output 25 ns
tJPZX JTAG port high impedance to valid output 25 ns
tJPXZ JTAG port valid output to high impedance 25 ns
tJSSU Capture register setup time 20 ns
tJSH Capture register hold time 45 ns
tJSCO Update register clock to output 35 ns
tJSZX Update register high impedance to valid output 35 ns
tJSXZ Update register valid output to high impedance 35 ns
Table 9–5. Document Revision History (Part 1 of 2)
Date and Document
Version Changes Made Summary of Changes
September 2008,
v2.3
Updated chapter number and metadata. —
June 2007, v2.2 Minor text edits. —
December 2006
v2.1
Updated revision history. Updated revision history.
March 2006 Formerly chapter 11; no content change.
9–4 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
January 2005
v2.0
Update device names and other minor textual changes. —
June 2003
v1.0
Initial release of Boundary-Scan Support in the HardCopy
Device Handbook.
—
Table 9–5. Document Revision History (Part 2 of 2)
Date and Document
Version Changes Made Summary of Changes
Altera Corporation 10–1
September 2008
10. Operating Conditions
Recommended
Operating
Conditions
Tables 10–1 through 10–4 provide information on absolute maximum
ratings, recommended operating conditions, DC operating conditions,
and capacitance for 1.8-V HardCopy® APEXTM devices.
Table 10–1. HardCopy APEX Device Absolute Maximum Ratings Note (1)
Symbol Parameter Conditions Min Max Unit
VCCINT Supply voltage With respect to ground (2) –0.5 2.5 V
VCCIO –0.5 4.6 V
VIDC input voltage –0.5 4.6 V
IOUT DC output current, per pin –25 25 mA
TSTG Storage temperature No bias –65 150 °C
TAMB Ambient temperature Under bias –65 135 °C
TJJunction temperature BGA packages, under bias 135 °C
Table 10–2. HardCopy APEX Device Recommended Operating Conditions
Symbol Parameter Conditions Min Max Unit
VCCINT Supply voltage for internal
logic and input buffers
(3), (4) 1.71
(1.71)
1.89
(1.89)
V
VCCIO Supply voltage for output
buffers, 3.3-V operation
(3), (4) 3.00
(3.00)
3.60
(3.60)
V
Supply voltage for output
buffers, 2.5-V operation
(3), (4) 2.375
(2.375)
2.625
(2.625)
V
VIInput voltage (2), (5) –0.5 4.1 V
VOOutput voltage 0 VCCIO V
TJJunction temperature For commercial use 0 85 ° C
For industrial use –40 100 ° C
tRInput rise time (10% to 90%) 40 ns
tFInput fall time (90% to 10%) 40 ns
H51010-2.3
10–2 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
Table 10–3. HardCopy APEX Device DC Operating Conditions (Part 1 of 2) Notes (6), (7), (8)
Symbol Parameter Conditions Min Typ Max Unit
VIH High-level LVTTL, CMOS, or
3.3-V PCI input voltage
1.7,
0.5 ×VCCIO (8)
4.1 V
VIL Low-level LVTTL, CMOS, or
3.3-V PCI input voltage
–0.5 0.8,
0.3 ×VCCIO (8)
V
VOH 3.3-V high-level LVTTL output
voltage
IOH
= –12 mA DC,
VCCIO = 3.00 V (9)
2.4 V
3.3-V high-level LVCMOS
output voltage
IOH
= –0.1 mA DC,
VCCIO = 3.00 V (9)
VCCIO –0.2 V
3.3-V high-level PCI output
voltage
IOH
= –0.5 mA DC,
VCCIO = 3.00 to 3.60 V
(9)
0.9 ×VCCIO V
2.5-V high-level output
voltage
IOH
= –0.1 mA DC,
VCCIO = 2.30 V (9)
2.1 V
IOH
= –1 mA DC,
VCCIO = 2.30 V (9)
2.0 V
IOH
= –2 mA DC,
VCCIO = 2.30 V (9)
1.7 V
VOL 3.3-V low-level LVTTL output
voltage
IOL = 12 mA DC,
VCCIO = 3.00 V (10)
0.4 V
3.3-V low-level LVCMOS
output voltage
IOL = 0.1 mA DC,
VCCIO = 3.00 V (10)
0.2 V
3.3-V low-level PCI output
voltage
IOL = 1.5 mA DC,
VCCIO = 3.00 to 3.60 V
(10)
0.1 ×VCCIO V
2.5-V low-level output voltage IOL = 0.1 mA DC,
VCCIO = 2.30 V (10)
0.2 V
IOL = 1 mA DC,
VCCIO = 2.30 V (10)
0.4 V
IOL = 2 mA DC,
VCCIO = 2.30 V (10)
0.7 V
IIInput pin leakage current (11) VI = 4.1 to –0.5 V –10 10 μA
IOZ Tri-stated I/O pin leakage
current (11)
VO = 4.1 to –0.5 V –10 10 μA
ICC0 VCC supply current (standby)
(All ESBs in power-down
mode)
VI = ground, no load,
no toggling inputs,
-7 speed grade
10 mA
VI = ground, no load,
no toggling inputs,
-8, -9 speed grades
5mA
Altera Corporation 10–3
September 2008
Recommended Operating Conditions
RCONF Value of I/O pin pull-up
resistor before and during
configuration emulation
VCCIO =3.0 V (12) 20 50 kΩ
VCCIO = 2.375 V (12) 30 80 kΩ
VCCIO = 1.71 V (12) 60 150 kΩ
Table 10–4. HardCopy APEX Device Capacitance Note (13)
Symbol Parameter Conditions Min Typ Max
CIN Input capacitance VIN = 0 V, f = 1.0 MHz 8 pF
CINCLK Input capacitance on
dedicated clock pin
VIN = 0 V, f = 1.0 MHz 12 pF
COUT Output capacitance VOUT = 0 V, f = 1.0 MHz 8 pF
Notes to Tab l e 1 0– 1 through 10–4:
(1) Refer to the Operating Requirements for Altera Devices Data Sheet.
(2) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –0.5 V or overshoot to 4.6 V for
input currents less than 100 mA and periods shorter than 20 ns.
(3) Numbers in parentheses are for industrial-temperature-range devices.
(4) Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
(5) All pins (including dedicated inputs, clock, I/O, and JTAG pins) may be driven before VCCINT and VCCIO
are
powered.
(6) Typical values are for TA = 25°C, VCCINT = 1.8 V, and VCCIO = 1.8 V, 2.5 V, or 3.3 V.
(7) These values are specified under the HardCopy device recommended operating conditions, as shown in Table 10–2
on page 10–1.
(8) Refer to AN 117: Using Selectable I/O Standards in Altera Devices for the VIH, VIL , VOH, VOL, and II parameters when
VCCIO = 1.8 V.
(9) The APEX 20KE input buffers are compatible with 1.8-V, 2.5-V and 3.3-V (LVTTL and LVCMOS) signals.
Additionally, the input buffers are 3.3-V PCI compliant. Input buffers also meet specifications for GTL+, CTT, AGP,
SSTL-2, SSTL-3, and HSTL.
(10) The IOH parameter refers to high-level TTL, PCI, or CMOS output current.
(11) This value is specified for normal device operation. The value may vary during power-up.
(12) Pin pull-up resistance values will be lower if an external source drives the pin higher than VCC IO .
(13) Capacitance is sample-tested only.
Table 10–3. HardCopy APEX Device DC Operating Conditions (Part 2 of 2) Notes (6), (7), (8)
Symbol Parameter Conditions Min Typ Max Unit
10–4 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
Tables 10–5 through 10–20 list the DC operating specifications for the
supported I/O standards. These tables list minimal specifications only;
HardCopy devices may exceed these specifications.
Table 10–5. LVTTL I/O Specifications
Symbol Parameter Conditions Minimum Maximum Units
VCCIO Output supply
voltage
3.0 3.6 V
VIH High-level input
voltage
2.0 VCCIO + 0.3 V
VIL Low-level input
voltage
–0.3 0.8 V
IIInput pin leakage
current
VIN = 0 V or 3.3 V –10 10 μA
VOH High-level output
voltage
IOH = –12 mA,
VCCIO = 3.0 V (1)
2.4 V
VOL Low-level output
voltage
IOL = 12 mA,
VCCIO = 3.0 V (2)
0.4 V
Table 10–6. LVCMOS I/O Specifications
Symbol Parameter Conditions Minimum Maximum Units
VCCIO Power supply
voltage range
3.0 3.6 V
VIH High-level input
voltage
2.0 VCCIO + 0.3 V
VIL Low-level input
voltage
–0.3 0.8 V
IIInput pin leakage
current
VIN = 0 V or 3.3 V –10 10 μA
VOH High-level output
voltage
VCCIO = 3.0 V
IOH = –0.1 mA (1)
VCCIO – 0.2 V
VOL Low-level output
voltage
VCCIO = 3.0 V
IOL = 0.1 mA (2)
0.2 V
Altera Corporation 10–5
September 2008
Recommended Operating Conditions
Table 10–7. 2.5-V I/O Specifications
Symbol Parameter Conditions Minimum Maximum Units
VCCIO Output supply
voltage
2.375 2.625 V
VIH High-level input
voltage
1.7 VCCIO + 0.3 V
VIL Low-level input
voltage
–0.3 0.7 V
IIInput pin leakage
current
VIN = 0 V or 3.3 V –10 10 μA
VOH High-level output
voltage
IOH = –0.1 mA (1) 2.1 V
IOH = –1 mA (1) 2.0 V
IOH = –2 mA (1) 1.7 V
VOL Low-level output
voltage
IOL = 0.1 mA (2) 0.2 V
IOL = 1 mA (2) 0.4 V
IOL = 2 mA (2) 0.7 V
Table 10–8. 1.8-V I/O Specifications
Symbol Parameter Conditions Minimum Maximum Units
VCCIO Output supply
voltage
1.7 1.9 V
VIH High-level input
voltage
0.65 × VCCIO VCCIO + 0.3 V
VIL Low-level input
voltage
0.35 × VCCIO V
IIInput pin leakage
current
VIN = 0 V or 3.3 V –10 10 μA
VOH High-level output
voltage
IOH = –2 mA (1) VCCIO – 0.45 V
VOL Low-level output
voltage
IOL = 2 mA (2) 0.45 V
Table 10–9. 3.3-V PCI Specifications (Part 1 of 2)
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supply voltage 3.0 3.3 3.6 V
VIH High-level input
voltage
0.5 × VCCIO VCCIO
+ 0.5 V
10–6 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
VIL Low-level input
voltage
–0.5 0.3 × VCCIO V
IIInput pin leakage
current
0 < VIN < VCCI O –10 10 μA
VOH High-level output
voltage
IOUT = –500 μA0.9 × VCCIO V
VOL Low-level output
voltage
IOUT = 1,500 μA0.1 × VCCIO V
Table 10–10. 3.3-V PCI-X Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO Output supply
voltage
3.0 3.3 3.6 V
VIH High-level input
voltage
0.5 × VCCIO VCCIO
+ 0.5 V
VIL Low-level input
voltage
–0.5 0.35 × VCCIO V
VIPU Input pull-up voltage 0.7 × VCCIO V
IIL Input pin leakage
current
0 < VIN < VCCI O –10.0 10.0 μΑ
VOH High-level output
voltage
IOUT = –500 µA 0.9 × VCCIO V
VOL Low-level output
voltage
IOUT = 1500 µA 0.1 × VCCIO V
LPIN Pin Inductance 15.0 nH
Table 10–11. 3.3-V LVDS I/O Specifications (Part 1 of 2)
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supply voltage 3.135 3.3 3.465 V
VOD Differential output
voltage
RL = 100 Ω250 450 mV
VOD Change in VOD
between high and
low
RL = 100 Ω50 mV
VOS Output offset voltage RL = 100 Ω1.125 1.25 1.375 V
Table 10–9. 3.3-V PCI Specifications (Part 2 of 2)
Symbol Parameter Conditions Minimum Typical Maximum Units
Altera Corporation 10–7
September 2008
Recommended Operating Conditions
VOS Change in VOS
between high and
low
RL = 100 Ω50 mV
VTH Differential input
threshold
VCM = 1.2 V –100 100 mV
VIN Receiver input
voltage range
0.0 2.4 V
RLReceiver differential
input resistor
(external to
APEX 20K devices)
90 100 110 Ω
Table 10–12. GTL+ I/O Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VTT Termination voltage 1.35 1.5 1.65 V
VREF Reference voltage 0.88 1.0 1.12 V
VIH High-level input
voltage
VREF + 0.1 V
VIL Low-level input
voltage
VREF
– 0.1 V
VOL Low-level output
voltage
IOL = 36 mA (2) 0.65 V
Table 10–13. SSTL-2 Class I Specifications (Part 1 of 2)
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supply voltage 2.375 2.5 2.625 V
VTT Termination voltage VREF – 0.04 VREF VREF + 0.04 V
VREF Reference voltage 1.15 1.25 1.35 V
VIH High-level input
voltage
VREF + 0.18 VCCIO
+ 0.3 V
VIL Low-level input
voltage
–0.3 VREF – 0.18 V
Table 10–11. 3.3-V LVDS I/O Specifications (Part 2 of 2)
Symbol Parameter Conditions Minimum Typical Maximum Units
10–8 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
VOH High-level output
voltage
IOH = –7.6 mA (1) VTT + 0.57 V
VOL Low-level output
voltage
IOL = 7.6 mA (2) VTT – 0.57 V
Table 10–14. SSTL-2 Class II Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supply voltage 2.375 2.5 2.625 V
VTT Termination voltage VREF – 0.04 VREF VREF + 0.04 V
VREF Reference voltage 1.15 1.25 1.35 V
VIH High-level input
voltage
VREF + 0.18 VCCIO
+ 0.3 V
VIL Low-level input
voltage
–0.3 VREF – 0.18 V
VOH High-level output
voltage
IOH = –15.2 mA (1) VTT + 0.76 V
VOL Low-level output
voltage
IOL = 15.2 mA (2) VTT – 0.76 V
Table 10–15. SSTL-3 Class I Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supply voltage 3.0 3.3 3.6 V
VTT Termination voltage VREF – 0.05 VREF VREF + 0.05 V
VREF Reference voltage 1.3 1.5 1.7 V
VIH High-level input
voltage
VREF + 0.2 VCCIO
+ 0.3 V
VIL Low-level input
voltage
–0.3 VREF
– 0.2 V
VOH High-level output
voltage
IOH = –8 mA (1) VTT + 0.6 V
VOL Low-level output
voltage
IOL = 8 mA (2) VTT – 0.6 V
Table 10–13. SSTL-2 Class I Specifications (Part 2 of 2)
Symbol Parameter Conditions Minimum Typical Maximum Units
Altera Corporation 10–9
September 2008
Recommended Operating Conditions
Table 10–16. SSTL-3 Class II Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supply voltage 3.0 3.3 3.6 V
VTT Termination voltage VREF – 0.05 VREF VREF + 0.05 V
VREF Reference voltage 1.3 1.5 1.7 V
VIH High-level input
voltage
VREF + 0.2 VCCIO
+ 0.3 V
VIL Low-level input
voltage
–0.3 VREF
– 0.2 V
VOH High-level output
voltage
IOH = –16 mA (1) VTT + 0.8 V
VOL Low-level output
voltage
IOL = 16 mA (2) VTT – 0.8 V
Table 10–17. HSTL Class I I/O Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supply voltage 1.71 1.8 1.89 V
VTT Termination voltage VREF – 0.05 VREF V
REF + 0.05 V
VREF Reference voltage 0.68 0.75 0.90 V
VIH High-level input
voltage
VREF + 0.1 VCCIO
+ 0.3 V
VIL Low-level input
voltage
–0.3 VREF
– 0.1 V
VOH High-level output
voltage
IOH = –8 mA (1) VCCIO
– 0.4 V
VOL Low-level output
voltage
IOL = 8 mA (2) 0.4 V
Table 10–18. LVPECL Specifications (Part 1 of 2)
Symbol Parameter Minimum Typical Maximum Units
VCCIO Output Supply
Voltage
3.135 3.3 3.465 V
VIH Low-level input
voltage
1,300 1,700 mV
VIL High-level input
voltage
2,100 2,600 mV
VOH Low-level output
voltage
1,450 1,650 mV
10–10 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
VOL High-level output
voltage
2,275 2,420 mV
VID Input voltage
differential
400 600 950 mV
VOD Output voltage
differential
625 800 950 mV
tr, tfRise and fall time
(20 to 80%)
85 325 ps
tDSKEW Differential skew 25 ps
tOOutput load 150 Ω
RLReceiver differential
input resistor
100 Ω
Table 10–19. 3.3-V AGP I/O Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supply voltage 3.15 3.3 3.45 V
VREF Reference voltage 0.39 × VCCIO 0.41 × VCCIO V
VIH High-level input
voltage
0.5 × VCCIO VCCIO
+ 0.5 V
VIL Low-level input
voltage
0.3 × VCCIO V
VOH High-level output
voltage
IOUT = –500 μA0.9 × VCCIO 3.6 V
VOL Low-level output
voltage
IOUT = 1500 μA0.1 × VCCIO V
IIInput pin leakage
current
0 < VIN
< VCCIO –10 10 μΑ
Table 10–20. CTT I/O Specifications (Part 1 of 2)
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supply voltage 3.0 3.3 3.6 V
VTT/VREF (3) Termination and
reference voltage
1.35 1.5 1.65 V
VIH High-level input
voltage
VREF + 0.2 V
Table 10–18. LVPECL Specifications (Part 2 of 2)
Symbol Parameter Minimum Typical Maximum Units
Altera Corporation 10–11
September 2008
Recommended Operating Conditions
VIL Low-level input
voltage
VREF
– 0.2 V
IIInput pin leakage
current
0 < VIN < VCCI O –10 10 μA
VOH High-level output
voltage
IOH = –8 mA (1) VREF + 0.4 V
VOL Low-level output
voltage
IOL = 8 mA (2) VREF
– 0.4 V
IOOutput leakage
current (when output
is high Z)
GND ≤ VOUT ≤ VCCIO –10 10 μA
Notes to Tables 10–5 through 10–20:
(1) The IOH parameter refers to high-level output current.
(2) The IOL parameter refers to low-level output current. This parameter applies to open-drain pins as well as output
pins.
(3) VREF specifies center point of switching range.
Table 10–20. CTT I/O Specifications (Part 2 of 2)
Symbol Parameter Conditions Minimum Typical Maximum Units
10–12 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
Figure 10–1 shows the output drive characteristics of HardCopy APEX
devices.
Figure 10–1. Output Drive Characteristics of HardCopy APEX Devices
Vo Output Voltage (V)
IOL
IOH
2
4
6
8
10
12
14
16
18
20
22
24
26
Vo Output Voltage (V)
IOL
IOH
5
10
15
20
45
0.5 1 1.5 22.5
3
25
30
35
40
50
55
60
Typical IO
Output
Current (mA)
10
20
30
40
50
60
70
80
90
0.5 1 1.5 22.5 3
Vo Output Voltage (V)
VCCINT = 1.8 V
VCCIO = 3.3 V
Room Temperature
IOH
IOL
Typical IO
Output
Current (mA)
100
110
120
0.5 1 1.5 2.0
VCCINT = 1.8 V
VCCIO = 2.5V
Room Temperature
VCCINT = 1.8V
VCCIO = 1.8V
Room Temperature
Typical IO
Output
Current (mA)
Altera Corporation 10–13
September 2008
Recommended Operating Conditions
Figure 10–2 shows the timing model for bidirectional I/O pin timing.
Figure 10–2. Synchronous Bidirectional Pin External Timing
Tables 10–21 and 10–22 describe HardCopy APEX device external timing
parameters.
PRN
CLRN
DQ
PRN
CLRN
DQ
IOE Register
Bidirectional Pin
Dedicated
Clock
PRN
CLRN
DQ
OE Register
Output IOE Register
Input Register
XZBIDIR
ZXBIDIR
t
t
INSUBIDIR
INHBIDIR
t
t
OUTCOBIDIR
t
Table 10–21. HardCopy APEX Device External Timing Parameters Note (1)
Symbol Clock Parameter Conditions
tINSU Setup time with global clock at IOE register
tINH Hold time with global clock at IOE register
tOUTCO Clock-to-output delay with global clock at IOE output register C1 = 35 pF
tINSUPLL Setup time with PLL clock at IOE input register
tINHPLL Hold time with PLL clock at IOE input register
tOUTCOPLL Clock-to-output delay with PLL clock at IOE output register C1 = 35 pF
Table 10–22. HardCopy APEX Device External Bidirectional Timing Parameters (Part 1 of 2) Note (1)
Symbol Parameter Condition
tINSUBIDIR Setup time for bidirectional pins with global clock at LAB-adjacent input
register
tINHBIDIR Hold time for bidirectional pins with global clock at LAB-adjacent input
register
tOUTCOBIDIR Clock-to-output delay for bidirectional pins with global clock at IOE
register
C1 = 35 pF
tXZBIDIR Synchronous output enable register to output buffer disable delay C1 = 35 pF
10–14 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
Tables 10–23 and 10–24 show the external timing parameters for
HC20K1500 devices.
tZXBIDIR Synchronous output enable register to output buffer enable delay C1 = 35 pF
tINSUBIDIRPLL Setup time for bidirectional pins with PLL clock at LAB-adjacent input
register
tINHBIDIRPLL Hold time for bidirectional pins with PLL clock at LAB-adjacent input
register
tOUTCOBIDIRPLL Clock-to-output delay for bidirectional pins with PLL clock at IOE register C1 = 35 pF
tXZBIDIRPLL Synchronous output enable register to output buffer disable delay with
PLL
C1 = 35 pF
tZXBIDIRPLL Synchronous output enable register to output buffer enable delay with
PLL
C1 = 35 pF
Note to Tables 10–21 and 10–22:
(1) These timing parameters are sample-tested only.
Table 10–22. HardCopy APEX Device External Bidirectional Timing Parameters (Part 2 of 2) Note (1)
Symbol Parameter Condition
Table 10–23. HC20K1500 External Timing Parameters Note (1)
Symbol Min Max Unit
tINSU 2.0 ns
tINH 0.0 ns
tOUTCO 2.0 5.0 ns
tINSUPLL 3.3 ns
tINHPLL 0.0 ns
tOUTCOPLL 0.5 2.1 ns
Table 10–24. HC20K1500 External Bidirectional Timing Parameters
(Part 1 of 2) Note (1)
Symbol Min Max Unit
tINSUBIDIR 1.9 ns
tINHBIDIR 0.0 ns
tOUTCOBIDIR 2.0 5.0 ns
tXZBIDIR 7.1 ns
tZXBIDIR 7.1 ns
tINSUBIDIRPLL 3.9 ns
Altera Corporation 10–15
September 2008
Document Revision History
Document
Revision History
Table 10–25 shows the revision history for this chapter.
tINHBIDIRPLL 0.0 ns
tOUTCOBIDIRPLL 0.5 2.1 ns
tXZBIDIRPLL 4.2 ns
tZXBIDIRPLL 4.2 ns
Note to Tables 10–23 and 10–24:
(1) Timing information is preliminary. Final timing information will be available in a
future version of this data sheet.
Table 10–24. HC20K1500 External Bidirectional Timing Parameters
(Part 2 of 2) Note (1)
Symbol Min Max Unit
Table 10–25. Document Revision History
Date and Document
Version Changes Made Summary of Changes
September 2008,
v2.3
Updated chapter number and metadata. —
June 2007, v2.2 Minor text edits. —
December 2006
v2.1
Updated revision history. —
March 2006 Formerly chapter 12; no content change. —
January 2005
v2.0
Update device names and other minor textual changes. —
June 2003
v1.0
Initial release of Operating Conditions, in the HardCopy
Device Handbook
—
10–16 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
