LC749880TE - ON SEMICONDUCTOR

September, 2014 − Rev. 8 1Publication Order Number:

MC74VHC373/D

MC74VHC373

Octal D-Type Latch

with 3-State Output

The MC74VHC373 is an advanced high speed CMOS octal latch

with 3−state output fabricated with silicon gate CMOS technology. It

achieves high speed operation similar to equivalent Bipolar Schottky

TTL while maintaining CMOS low power dissipation.

This 8−bit D−type latch is controlled by a latch enable input and an

output enable input. When the output enable input is high, the eight

outputs are in a high impedance state.

The internal circuit is composed of three stages, including a buffer

output which provides high noise immunity and stable output. The

inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V

systems to 3.0 V systems.

Features

•High Speed: tPD = 5.0 ns (Typ) at VCC = 5.0 V

•Low Power Dissipation: ICC = 4.0 mA (Max) at TA = 25°C

•High Noise Immunity: VNIH = VNIL = 28% VCC

•Power Down Protection Provided on Inputs

•Balanced Propagation Delays

•Designed for 2.0 V to 5.5 V Operating Range

•Low Noise: VOLP = 0.9 V (Max)

•Pin and Function Compatible with Other Standard Logic Families

•Latchup Performance Exceeds 300 mA

•ESD Performance: HBM > 2000 V; Machine Model > 200 V

•Chip Complexity: 186 FETs or 46.5 Equivalent Gates

•These Devices are Pb−Free and are RoHS Compliant

PIN ASSIGNMENT

GND

Q1 5

VCC

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See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAM

SOIC−20

DW SUFFIX

CASE 751D

VHC373

AWLYYWWG

VHC373 = Specific Device Code

A = Assembly Location

WL, L = Wafer Lot

Y = Year

WW, W = Work Week

G or G= Pb−Free Package

(Note: Microdot may be in either location)

MC74VHC373

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Figure 1. Logic Diagram

DATA

INPUTS

D7 18

NONINVERTING

OUTPUTS

OE LE Q

No Change

INPUTS OUTPUT

FUNCTION TABLE

MAXIMUM RATINGS

Symbol Parameter Value Unit

VCC DC Supply Voltage – 0.5 to + 7.0 V

Vin DC Input Voltage – 0.5 to + 7.0 V

Vout DC Output Voltage – 0.5 to VCC + 0.5 V

IIK Input Diode Current − 20 mA

IOK Output Diode Current ±20 mA

Iout DC Output Current, per Pin ±25 mA

ICC DC Supply Current, VCC and GND Pins ±75 mA

PDPower Dissipation in Still Air, SOIC Package† 500 mW

Tstg Storage Temperature – 65 to + 150 _C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of

these limits are exceeded, device functionality should not be assumed, damage may occur and

reliability may be affected.

†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage 2.0 5.5 V

Vin DC Input Voltage 0 5.5 V

Vout DC Output Voltage 0 VCC V

TAOperating Temperature − 40 + 85 _C

tr, tfInput Rise and Fall Time VCC = 3.3 V

VCC = 5.0 V 0

0100

20 ns/V

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74VHC373

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DC ELECTRICAL CHARACTERISTICS

Symbol Parameter Test Conditions VCC

TA = 25°C TA = − 40 to 85°C

Uni

Min Typ Max Min Max

VIH Minimum High−Level

Input Voltage 2.0

3.0 to

5.5

1.50

VCC x 0. 7 1.50

VCC x 0. 7 V

VIL Maximum Low−Level

Input Voltage 2.0

3.0 to

5.5

0.50

VCC x 0. 3 0.50

VCC x 0. 3 V

VOH Minimum High−Level

Output Voltage Vin = VIH or VIL

IOH = − 50 mA

2.0

3.0

4.5

1.9

2.9

4.4

2.0

3.0

4.5

1.9

2.9

4.4

Vin = VIH or VIL

IOH = − 4 mA

IOH = − 8 mA 3.0

4.5 2.58

3.94 2.48

3.80

VOL Maximum Low−Level

Output Voltage Vin = VIH or VIL

IOL = 50 mA2.0

3.0

4.5

0.0

0.1

Vin = VIH or VIL

IOL = 4 mA

IOL = 8 mA 3.0

4.5 0.36

0.36 0.44

0.44

Iin Maximum Input

Leakage Current Vin = 5.5 V or GND 0 to 5.5 ±0.1 ±1.0 mA

IOZ Maximum

Three−State Leakage

Current

Vin = VIL or VIH

Vout = VCC or GND 5.5 ±0.25 ±2.5 mA

ICC Maximum Quiescent

Supply Current Vin = VCC or GND 5.5 4.0 40.0 mA

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)

Symbol Parameter Test Conditions

TA = 25°C TA = − 40 to 85°C

Uni

Min Typ Max Min Max

tPLH,

tPHL Maximum Propagation Delay,

D to Q VCC = 3.3 ± 0.3 V CL = 15 pF

CL = 50 pF 7.3

9.8 11.4

14.9 1.0

1.0 13.5

17.0 ns

VCC = 5.0 ± 0.5 V CL = 15 pF

CL = 50 pF 4.9

6.4 7.2

9.2 1.0

1.0 8.5

10.5

tPLH,

tPHL Maximum Propagation Delay,

LE to Q VCC = 3.3 ± 0.3 V CL = 15 pF

CL = 50 pF 7.0

9.5 11.0

14.5 1.0

1.0 13.0

16.5 ns

VCC = 5.0 ± 0.5 V CL = 15 pF

CL = 50 pF 5.0

6.5 7.2

9.2 1.0

1.0 8.5

10.5

tPZL,

tPZH Output Enable Time,

OE to Q VCC = 3.3 ± 0.3 V CL = 15 pF

RL = 1 kWCL = 50 pF 7.3

9.8 11.4

14.9 1.0

1.0 13.5

17.0 ns

VCC = 5.0 ± 0.5 V CL = 15 pF

RL = 1 kWCL = 50 pF 5.5

7.0 8.1

10.1 1.0

1.0 9.5

11.5

tPLZ,

tPHZ Output Disable Time,

OE to Q VCC = 3.3 ± 0.3 V CL = 50 pF

RL = 1 kW

9.5 13.2 1.0 15.0 ns

VCC = 5.0 ± 0.5V CL = 50 pF

RL = 1 kW

6.5 9.2 1.0 10.5

tOSLH,

tOSHL Output to Output Skew VCC = 3.3 ± 0.3 V CL = 50 pF

(Note 1) 1.5 1.5 ns

VCC = 5.5 ± 0.5 V CL = 50 pF

(Note 1) 1.0 1.0 ns

MC74VHC373

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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)

Symbol Unit

TA = − 40 to 85°CTA = 25°C

Test ConditionsParameter

Symbol Unit

MaxMinMaxTypMin

Test ConditionsParameter

Cin Maximum Input Capacitance 4 10 10 pF

Cout Maximum Three−State Output

Capacitance (Output in

High−Impedance State)

6 pF

CPD Power Dissipation Capacitance (Note 2)

Typical @ 25°C, VCC = 5.0 V

1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.

2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC/8 (per latch). CPD is used to determine the

no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.

NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50 pF, VCC = 5.0V)

Symbol Parameter

TA = 25°C

Unit

Typ Max

VOLP Quiet Output Maximum Dynamic VOL 0.6 0.9 V

VOLV Quiet Output Minimum Dynamic VOL − 0.6 − 0.9 V

VIHD Minimum High Level Dynamic Input Voltage 3.5 V

VILD Maximum Low Level Dynamic Input Voltage 1.5 V

TIMING REQUIREMENTS (Input tr = tf = 3.0 ns)

Symbol Parameter Test Conditions

TA = 25°CTA = − 40

to 85°C

Unit

Typ Limit Limit

tw(h) Minimum Pulse Width, LE VCC = 3.3 ± 0.3 V

VCC = 5.0 ±0.5 V 5.0

5.0 5.0

5.0 ns

tsu Minimum Setup Time, D to LE VCC = 3.3 ± 0.3 V

VCC = 5.0 ± 0.5 V 4.0

4.0 4.0

4.0 ns

thMinimum Hold Time, D to LE VCC = 3.3 ± 0.3 V

VCC = 5.0 ± 0.5 V 1.0

1.0 1.0

1.0 ns

ORDERING INFORMATION

Device Package Shipping†

MC74VHC373DWR2G SOIC−20

(Pb−Free) 1000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

MC74VHC373

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SWITCHING WAVEFORMS

Figure 2. Figure 3.

VCC

GND

50%

50% VCC

tPLH tPHL

VCC

GND

50%

tPLH tPHL

50% VCC

Figure 4. Figure 5.

50%

50% VCC

tPZL tPLZ

tPZH tPHZ

VOL +0.3V

VOL -0.3V

VCC

GND

HIGH

IMPEDANCE

HIGH

IMPEDANCE

50%

VCC

GND

VALID

tsu

50%

TEST CIRCUITS

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 6. Figure 7.

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.

CONNECT TO GND WHEN

TESTING tPHZ AND tPZH.

1 kW

MC74VHC373

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Figure 8. EXPANDED LOGIC DIAGRAM

Figure 9. INPUT EQUIVALENT CIRCUIT

INPUT

MC74VHC373

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PACKAGE DIMENSIONS

SOIC−20

DW SUFFIX

CASE 751D−05

ISSUE G

B20X

H10X

18X A1

SEATING

PLANE

hX 45_

0.25 M

0.25 S

DIM MIN MAX

MILLIMETERS

A2.35 2.65

A1 0.10 0.25

B0.35 0.49

C0.23 0.32

D12.65 12.95

E7.40 7.60

e1.27 BSC

H10.05 10.55

h0.25 0.75

L0.50 0.90

q0 7

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF B

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

UBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

MC74VHC373/D

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your loc

Sales Representative

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