FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI 3.3 Volt Synchronous x9 First-In/First-Out Queue Memory Configuration Device Memory Configuration Device 8,192 x 9 FQV251 512 x 9 FQV211 4,096 x 9 FQV241 256 x 9 FQV201 2,048 x 9 FQV231 128 x 9 FQV621 1,024 x 9 FQV221 64 x 9 FQV421 Key Features: * * * * * * * * * * * * Industry leading First-In/First-Out Queues (up to 100MHz) Independent Write and Read cycle time 3.3V power supply 5V input tolerant on all control and data input pins 5V output tolerant on all flags and data output pins Full, Empty, Almost Full, and Almost Empty flag indicators Preset for Almost Full ( PRAF ) and Almost Empty ( PRAE ) offset values Programmable PRAF and PRAE offset values Asynchronous output enable tri-state data output drivers Available packages: 32 - pin Plastic Lead Chip Carrier (PLCC), 32 - pin Plastic Thin Quad Flat Package (TQFP) (0C to 70C) Commercial operating temperature available for cycle time of 10ns and above (-40C to 85C) Industrial operating temperature available for cycle time of 10ns and above Product Description: HBA's FlexQTM I offers industry leading FIFO queuing bandwidth (up to 1 Gbps) with a wide range of memory configurations (from 64 x 9 to 8,192 x 9). System designer has full flexibility of implementing deeper and wider queues using the depth and width expansion features. Full and Empty indicators allow easy handshaking between transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel) indicators allow implementation of virtual queue depths. 5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-matching capability. These FlexQTM I devices have low power consumption, hence minimizing system power requirements. In addition, industry standard 32 - pin PLCC and 32 - pin TQFP are offered to save system board space. These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test equipment, network switching, etc. 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 1 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI Block Diagram of Single Synchronous Queue 8,192 x 9 / 4,096 x 9 / 2,048 x 9 / 1,024 x 9 / 512 x 9 / 256 x 9 / 128 x 9 / 64 x 9 RESET ( RST ) WRITE CLOCK (WCLK) WRITE ENABLE 1 ( WEN1) WRITE ENABLE 2/LOAD (WEN2/ LOAD ) DATA IN (D8 - 0) FULL ( FULL ) READ CLOCK (RCLK) FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV621 FQV421 READ ENABLE 1 (REN1) READ ENABLE 2 ( REN 2) DATA OUT (Q 8 - 0) EMPTY ( EMPTY ) ALMOST-EMPTY ( PRAE ) ALMOST-FULL ( PRAF ) OUTPUT ENABLE ( OE ) Figure 1. Single Device Configuration Signal Flow Diagram 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 2 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI WCLK WEN1 WEN2/ LOAD LOAD Write Control Logic EMPTY PRAE Offset Register PRAF Flag Logic FULL Write Pointer D 8-0 Input Register SRAM Output Buffer Output Register Q 8-0 OE Read Pointer Read Control Logic Reset RST RCLK REN1 REN 2 Figure 2. Device Architecture 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 3 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 D2 D3 D4 D5 D6 D7 D8 FlexQTMI 4 3 2 1 32 31 30 Ind e x D1 5 29 D0 6 28 W E N1 PRAF 7 27 W CLK PRAE 8 26 W E N 2/ L O A D GN D 9 25 R EN1 10 24 Q8 RCLK 11 23 Q7 REN 2 12 22 Q6 OE 13 21 Q5 19 V cc 20 Q4 Q2 FULL 18 Q3 17 Q1 16 Q0 15 EMPTY 14 R ST D3 D4 D5 D6 D7 D8 32 31 30 29 28 27 26 RST D2 PL C C - 3 2 (D rw N o : J -0 1 A ; O rde r c o de : J ) T o p V ie w Ind e x 25 PRAF 3 22 W E N 2/L O A D P R AE 4 21 GN D 5 20 Q8 R EN1 6 19 Q7 RCLK 7 18 Q6 REN 2 8 17 Q5 10 EMPTY OE 9 11 12 13 14 15 16 Q4 W CLK Q3 D0 Q2 W E N1 23 Q1 24 2 Q0 1 FULL D1 Vcc T Q FP - 3 2 (D rw N o : PF-0 4 A ; O rde r c o de : PF) T o p V ie w Figure 3. Device Pin-Out 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 4 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI Pin # TQFP Pin # PLCC Symbol Name Description Input/Output 25 29 RST Reset Input Reset is required to initialize Write and Read pointers to the first position of the queue by setting RST low. FULL and PRAF will go high; EMPTY and PRAE will go low. 23 27 WCLK Write Clock Input Writes data into queue during low to high transitions of WCLK if WEN1 is activated. 24 28 WEN1 Write Enable Input Use as first or as only write enable control for the queue depending on the state of WEN2/ LOAD during reset. 22 26 WEN2/ LOAD Write Enable 2 / Load Input During reset, setting WEN2/ LOAD high places the queue into the dual write enable mode. WEN1 must be set low and WEN2/ LOAD must be set high to perform a valid write in this mode. During reset, setting WEN2/ LOAD low places the queue into the single write enable/programmable flag mode. WEN1 must be set low and WEN2/ LOAD must be set high to perform a valid write in this mode. In this mode, WEN1 and WEN2/ LOAD must be set low to program the offset values for PRAF and PRAE . 26,27,28, 29,30,31 32,01,02 30,31,32, 01,02,03, 04,05,06 D8 - 0 Data Inputs Input 9 - bit wide input data bus. 7 11 RCLK Read Clock Input Reads data from queue during low to high transitions of RCLK if REN1 and REN 2 are set to low. 6 10 REN1 Read Enable 1 Input Reads data from queue during low to high transitions of RCLK if REN1 and REN 2 are both set to low. 8 12 REN 2 Read Enable 2 Input Reads data from queue during low to high transitions of RCLK if REN1 and REN 2 are both set to low. 9 13 OE Output Enable Input Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers (High-Z). 20,19,18 17,16,15, 14,13,12 24,23,22, 21,20,19, 18,17,16 Q8 - 0 Data Output Output 9 - bit wide output data bus. 11 15 FULL Full Flag Output Queue is full when FULL goes low during the low to high transition of WCLK. This prohibits further writes into the queue. 10 14 EMPTY Empty Flag Output Queue is empty when EMPTY goes low during the low to high transition of RCLK. This prohibits further reads from the queue. 3 7 PRAF Programmable Almost-Full Flag Output Queue is almost full when PRAF goes low during the low to high transition of WCLK. Default (Full-7) or programmed offset values determine the status of PRAF . 4 8 PRAE Programmable Almost-Empty Flag Output Queue is almost empty when PRAE goes low during the low to high transition of RCLK. Default (Empty+7) or programmed offset values determine the status of PRAE . 21 25 Vcc Power N/A 5V power supply. 5 9 GND Ground N/A 0V Ground. Table 1. Pin Descriptions 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 5 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI Symbol Rating Com'l & Ind'l Unit VTERM Terminal Voltage with respect to GND -0.5 to + 5.0 V TSTG Storage Temperature -55 to +125 IOUT DC Output Current -50 to +50 NOTES: Absolute Max Ratings are for reference only. Permanent damage to the device may occur if extended period of operation is outside this range. Standard operation should fall within the Recommended Operating Conditions. C mA Table 2. Absolute Maximum Ratings FQV251, FQV241 FQV231, FQV221 FQV211, FQV201 FQV621, FQV421 Commercial Clock = 10ns, 15ns, 20ns Symbol Parameter Recommended Operating Conditions VCC Supply Voltage Com'l/Ind'l GND Supply Voltage VIH Input High Voltage Com'l/Ind'l Input Low Voltage Com'l/Ind'l Operating Temperature Commercial Operating Temperature Industrial VIL TA TA Industrial Clock = 10ns, 15ns, 20ns Min. Typ. Max. Min. Typ. Max. Unit 3.0 3.3 3.6 3.0 3.3 3.6 V 0 0 0 0 0 0 V 2.0 - 5.5 2.0 - 5.5 V - - 0.8 - - 0.8 V 0 - 70 0 - 70 -40 - 85 -40 - 85 C C DC Electrical Characteristics ILI(1) Input Leakage Current (any input) -10 - 10 -10 - 10 A ILO Output Leakage Current -10 - 10 -10 - 10 A VOH Output Logic "1" Voltage, IOH=-2mA Output Logic "0" Voltage, IOL = 8mA 2.4 - - 2.4 - - V - - 0.4 - - 0.4 V VOL Power Consumption ICC1(2,3) Active Power Supply Current - - 20 - - 20 mA ICC2(2,3) Standby Current - - 5 - - 5 mA Table 3. DC Specifications 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 6 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI Capacitance at 1.0 MHz Ambient Temperature (25C) Symbol Parameter (4) CIN Input Capacitance COUT(2,4) Output Capacitance Conditions Max. Unit VIN= 0V 10 pF VOUT= 0V 10 pF NOTES: 1. 2. 3. 4. Measurement with 0.4<=VIN<=Vcc With output tri-stated ( OE = High) Icc(1,2) is measured with WCLK and RCLK at 20 MHz Design simulated, not tested. Table 3. DC Specifications (Continued) 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 7 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI Commercial & Industrial FQV251-10 FQV241-10 FQV231-10 FQV221-10 FQV211-10 FQV201-10 FQV621-10 FQV421-10 FQV251-15 FQV241-15 FQV231-15 FQV221-15 FQV211-15 FQV201-15 FQV621-15 FQV421-15 FQV251-20 FQV241-20 FQV231-20 FQV221-20 FQV211-20 FQV201-20 FQV621-20 FQV421-20 Min. Max. Min. Max. Min. Max. Unit fS Clock Cycle Frequency - 100 - 66 - 50 MHz tA Data Access Time 2 6.5 2 10 2 12 ns tWCLK Write Clock Cycle Time 10 - 15 - 20 - ns tWCLKH Write Clock High Time 4.5 - 6 - 8 - ns tWCLKL Write Clock Low Time 4.5 - 6 - 8 - ns tRCLK Read Clock Cycle Time 10 - 15 - 20 - ns tRCLKH Read Clock High Time 4.5 - 6 - 8 - ns tRCLKL Read Clock Low Time 4.5 - 6 - 8 - ns tDS Data Set-up Time 3 - 4 - 5 - ns tDH Data Hold Time 0.5 - 1 - 1 - ns tENS Enable Set-up Time 3 - 4 - 5 - ns tENH Enable Hold Time 0.5 - 1 - 1 - ns Symbol Parameter (1) tRST Reset Pulse Width 10 - 15 - 20 - ns tRSTS Reset Set-up Time 8 - 10 - 12 - ns tRSTR Reset Recovery Time 8 - 10 - 12 - ns tRSTF Reset to Flag and Output Time - 10 - 15 - 20 ns 0 - 0 - 0 - ns 3 6 3 8 3 10 ns (1) tOLZ Output Enable to Output in Low-Z tOE Output Enable to Output Valid (1) tOHZ Output Enable to Output in High-Z 3 6 3 8 3 10 ns tFULL Write Clock to Full Flag - 6.5 - 10 - 12 ns tEMPTY Read Clock to Empty Flag - 6.5 - 10 - 12 ns tPRAF Write Clock to Almost-Full Flag - 6.5 - 10 - 12 ns tPRAE Read Clock to Almost-Empty Flag - 6.5 - 10 - 12 ns tSKEW1(2) Skew time between Read Clock & Write Clock for Full Flag / Empty Flag 5 - 6 - 8 - ns tSKEW2 Skew time between Read Clock & Write Clock for PRAF & PRAE 14 - 18 - 20 - ns NOTES: 1. 2. Design simulated, not tested. Refer to Table 10. Table 4. AC Electrical Characteristics 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 8 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load*, clock = 10ns, 15ns, 20ns Refer to Figure 4 * Include jig and scope capacitances Table 5. AC Test Condition 3.3V 330 D.U.T. 30pF* 510 Figure 4. Output Load for clock = 10ns, 15ns, 20ns *Includes jig and scope capacitances. 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 9 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI Pin Functions RST Reset is required to initialize Write and Read pointers to the first position of the queue by setting RST low. FULL and PRAF will go high; EMPTY and PRAE will go low. All data outputs will be set low. PRAF and PRAE offset will be set to their default values (Full-7 and Empty+7 respectively). WCLK Writes data into queue during low to high transitions of WCLK if WEN1 is activated. Synchronizes FULL and PRAF flags. WCLK and RCLK are independent of each other. WEN1 Use as single or as dual write enable control for the queue depending on the state of WEN2/ LOAD during reset. To perform a write operation in single write enable mode: Set WEN2/ LOAD low during reset. Set WEN1 low, and WEN2/ LOAD high during low to high transition of WCLK. To perform an offset programming operation in single write enable mode: Set WEN2/ LOAD low during reset. Set WEN1 low, and WEN2/ LOAD low during low to high transition of WCLK. To perform a write operation in dual write enable mode: Set WEN2/ LOAD high during reset. Set WEN1 low, and WEN2/ LOAD high during low to high transition of WCLK. WEN2/ LOAD During reset, setting WEN2/ LOAD low puts the queue into single write enable/offset programming mode. Setting WEN2/ LOAD high places the queue into dual write enable mode. D8 - 0 9 - bit wide input data bus RCLK Reads data from queue during low to high transitions of RCLK if REN1 and REN 2 are activated. Synchronizes EMPTY and PRAE flags. RCLK and WCLK are independent of each other. REN1 Reads data from queue during low to high transitions of RCLK if REN1 and REN 2 are both set to low. This also advances the Read pointer of the queue. REN2 Reads data from queue during low to high transitions of RCLK if REN1 and REN 2 are both set to low. This also advances the Read pointer of the queue. OE Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers (High-Z). OE does not control advancement of Read pointer. Q8 - 0 9 - bit wide output data bus. FULL Queue is full when FULL goes low during the low to high transition of WCLK. This prohibits further writes into the queue and prevents advancement of Write pointer. Refer to Table 9 for behavior of FULL . EMPTY Queue is empty when EMPTY goes low during the low to high transition of RCLK. This prohibits further reads from the queue and prevents advancement of Read pointer. Refer to Table 9 for behavior of EMPTY . 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 10 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI Pin Functions (Continued) PRAF Queue is almost full when PRAF goes low during the low to high transition of WCLK. Default (Full7) or programmed offset values determine the status of PRAF . Refer to Table 9 for behavior of PRAF . PRAE Queue is almost empty when PRAE goes low during the low to high transition of RCLK. Default (Empty+7) or programmed offset values determine the status of PRAE . Refer to Table 9 for behavior of PRAE . 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 11 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI WEN2/ LOAD WEN1 FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV621 FQV421 Selection / Sequence WCLK 0 0 Write to offset registers: Empty offset (Low Byte) Empty offset (High Byte) Full offset (Low Byte) Full offset (High Byte) 0 1 No Operation 1 0 Write Memory 1 1 No Operation 1. 2. 3. 4. PRAE Low Byte PRAE High Byte PRAF Low Byte PRAF High Byte Figure 5. Write Offset Register 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 12 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI WEN2/ LOAD REN1 & REN2 FQV251 FQV241 FQV231 FQV221 FQV211 FQV201 FQV621 FQV421 Selection / Sequence RCLK 0 0 Read from offset registers: Empty offset (Low Byte) Empty offset (High Byte) Full offset (Low Byte) Full offset (High Byte) 0 1 No Operation 1 0 Read Memory 1 1 No Operation 1. 2. 3. 4. PRAE Low Byte PRAE High Byte PRAF Low Byte PRAF High Byte Figure 6. Read Offset Register 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 13 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI Device PRAE Programming (bits) PRAF Programming (bits) FQV251 D/Q7-0 D/Q4-0 Low Byte High Byte D/Q7-0 D/Q4-0 Low Byte High Byte FQV241 D/Q7-0 D/Q3-0 Low Byte High Byte D/Q7-0 D/Q3-0 Low Byte High Byte FQV231 D/Q7-0 D/Q2-0 Low Byte High Byte D/Q7-0 D/Q2-0 Low Byte High Byte FQV221 D/Q7-0 D/Q1-0 Low Byte High Byte D/Q7-0 D/Q1-0 Low Byte High Byte FQV211 D/Q7-0 D/Q0 Low Byte High Byte D/Q7-0 D/Q0 Low Byte High Byte FQV201 D/Q7-0 Don't Care Low Byte High Byte D/Q7-0 Don't Care Low Byte High Byte FQV621 D/Q6-0 Don't Care Low Byte High Byte D/Q6-0 Don't Care Low Byte High Byte FQV421 D/Q5-0 Don't Care Low Byte High Byte D/Q5-0 Don't Care Low Byte High Byte ALL Default Value 007H Default Value 007H Table 7. Parallel Offset Register Data Mapping Table and Default Values Device Standard Mode FQV251 8,192 x 9 FQV241 4,096 x 9 FQV231 2,048 x 9 FQV221 1,024 x 9 FQV211 512 x 9 FQV201 256 x 9 FQV621 128 x 9 FQV421 64 x 9 Table 8. Maximum Depth of Queue 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 14 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI Data Width 1st Cycle PRAE (Low Byte) FQV251 - 8,912 x 9 FQV241 - 4,096 x9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 7 6 5 2nd Cycle PRAE (High Byte) 3rd Cycle PRAF (Low Byte) 7 6 5 4th Cycle PRAF (High Byte) Data Width 1st Cycle PRAE (Low Byte) 4 3 2 1 0 12 11 10 9 8 4 3 2 1 0 12 11 10 9 8 7 6 5 4 3 7 6 5 4 3 2 1 0 10 9 8 2 1 0 10 9 8 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 7 6 5 4 3 2 1 7 7 1 0 11 10 9 8 3 2 1 0 11 10 9 8 6 6 5 5 4 4 3 3 2 2 1 0 9 8 1 0 9 8 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 8 FQV621 - 128 x 9 1st Cycle PRAE (Low Byte) 2 FQV201 - 256 x 9 4th Cycle PRAF (High Byte) Data Width 4 3 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 2nd Cycle PRAE (High Byte) 3rd Cycle PRAF (Low Byte) 5 4 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 FQV211 - 512 x 9 1st Cycle PRAE (Low Byte) 6 5 FQV221 - 1,024 x 9 4th Cycle PRAF (High Byte) Data Width 7 6 FQV231 - 2,048 x 9 2nd Cycle PRAE (High Byte) 3rd Cycle PRAF (Low Byte) 7 FQV421 - 64 x 9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 6 5 4 3 2 1 0 5 4 3 2 1 0 6 5 4 3 2 1 0 5 4 3 2 1 0 2nd Cycle PRAE (High Byte) 3rd Cycle PRAF (Low Byte) 4th Cycle PRAF (High Byte) # of Bits for Offset Registers 13 bits for FQV251 12 bits for FQV241 11 bits for FQV231 10 bits for FQV221 9 bits for FQV211 8 bits for FQV201 7 bits for FQV621 6 bits for FQV421 Note: Don't Care applies to all unused bits for both High Byte and Low Byte Figure 7. Parallel Offset Write/Read Cycles Diagram 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 15 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI FQV251 FULL PRAF PRAE EMPTY 0 H H L L 1 to y(1) H H L H (y+1) to [8,192-(x+1)] H H H H (8,192-x(2))to 8,191 H L H H 8,192 L L H H FQV241 FULL PRAF PRAE 0 H H L 1 to y (1) EMPTY L H H L H (y+1) to [4,096-(x+1)] H H H H (4,096-x(2))to 4,095 H L H H 4,096 L L H H FQV231 FULL PRAF PRAE 0 H H L L H H L H (y+1) to [2,048-(x+1)] H H H H (2,048-x(2))to 2,047 H L H H 2,048 L L H H FQV221 FULL PRAF PRAE 1 to y (1) EMPTY EMPTY 0 H H L L 1 to y(1) H H L H (y+1) to [1,024-(x+1)] H H H H (2) (1,024-x )to 1,023 H L H H 1,024 L L H H FQV211 FULL PRAF PRAE 0 H H L 1 to y (1) EMPTY L H H L H (y+1) to [512-(x+1)] H H H H (512-x(2))to 511 H L H H 512 L L H H Table 9. Status Flags 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 16 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI FQV201 FULL PRAF PRAE 0 H H L 1 to y (1) EMPTY L H H L H (y+1) to [256-(x+1)] H H H H (256-x(2))to 255 H L H H 256 L L H H FQV621 FULL PRAF PRAE EMPTY 0 H H L L 1 to y(1) H H L H (y+1) to [128-(x+1)] H H H H (128-x(2))to 127 H L H H 128 L L H H FQV421 FULL PRAF PRAE 0 H H L 1 to y (1) EMPTY L H H L H (y+1) to [64-(x+1)] H H H H (64-x(2))to 63 H L H H 64 L L H H NOTES: 1. 2. y = PRAE offset (y = 7 default value). x = PRAF offset (x = 7 default value). Table 9. Status Flags (Continued) 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 17 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI Timing Diagrams tRST RST tRSTS tRSTR tRSTS tRSTR tRSTS tRSTR REN1 , REN 2 WEN1 WEN2/ LOAD (1) tRSTF EMPTY , PRAE tRSTF FULL , PRAF tRSTF OE = 1(2) Q8 - 0 OE = 0 NOTES: 1. 2. 3. Holding WEN2/ LOAD high during reset will make the pin act as a second Write Enable pin. Holding WEN2/ LOAD low during reset will make the pin act as a Load Enable for the programmable flag offset registers. After reset, the outputs will be low if OE = 0 and high-impedance if OE = 1. The clocks (RCLK, WCLK) can be free-running during reset. Diagram 1. Reset Timing 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 18 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI tWCLK tWCLKH tWCLKL WCLK tDS tDH D8 - 0 Valid Data tENS tENH tENS tENH No Operation WEN1 No Operation WEN2/LOAD tFULL tFULL FULL tSKEW1(1) RCLK REN1 , REN 2 NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FULL to change during the current clock cycle. If the time between the rising edge of RCLK and the rising WCLK is less than tSKEW1, the FULL may not change state until the next WCLK edge. Diagram 2. Write Cycle Timing 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 19 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI tRCLK tRCLKH tRCLKL RCLK tENH tENS No Operation REN1 , REN 2 tEMPTY EMPTY Q8 - 0 tEMPTY tA Valid Data tOLZ tOE tOHZ OE tSKEW1(1) WCLK WEN1 WEN2/LOAD NOTES: tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EMPTY to change during the current clock cycle. If the time 1. between the rising edge of RCLK and the rising edge of WCLK is less than t SKEW1, then EMPTY may not change state until the next RCLK edge. Diagram 3. Read Cycle Timing 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 20 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI WCLK tDS First Valid Write D8 - 0 DW2 DW1 DW3 DW4 DW5 tENS WEN1 tENS WEN2/LOAD tFRL tSKEW1 RCLK tEMPTY EMPTY tENS REN1 , REN 2 tA tA Q8 - 0 DW1 DW2 DW3 tOLZ tOE OE NOTES: 1. tFRL = First Read Latency. When tSKEW1 is greater than or equal to the minimum specification, tFRL = tRCLK + tSKEW1. When tSKEW1 is less than minimum specification, tFRL = 2*tRCLK + tSKEW1 or tRCLK + tSKEW1 2. The Latency Timings apply only at the Empty Boundary ( EMPTY = Low). Diagram 4. First Data Word Latency Timing Speed Grade 100 MHz 66MHz tSKEW1 >= 5 tSKEW1 >= 6 First Word Latency tFRL tRCLK + tSKEW1 2*tRCLK + tSKEW1 tSKEW1 < 5 tSKEW1 < 6 OR tRCLK + tSKEW1 Table 10. Empty Boundary Latency Timing 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 21 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI No Write No Write No Write WCLK tSKEW1 tDS tSKEW1 D8 - 0 tFULL tFULL tFULL FULL tENS tENH tENS(1) tENS tENH tENS(1) WEN1 WEN2/LOAD RCLK tENS tENH tENS tENH REN1 , REN 2 tA OE Q8 - 0 LOW tA Output Register Data Data Read Next Data Read NOTES: 1. Only one of the two Write Enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the Queue. Diagram 5. Full Flag Timing 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 22 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI WCLK tDS tDS D8 - 0 DW1 DW2 tENS tENH tENS tENH tENS tENH tENS tENH WEN1 WEN2/LOAD tFRL(1) tFRL(1) tSKEW1 tSKEW1 RCLK tEMPTY tEMPTY tEMPTY EMPTY REN1 , REN 2 OE LOW tA Q8 - 0 Output Register Data DW1 NOTES: 1. 2. When tSKEW1 is greater than or equal to minimum specification, tFRL = tRCLK + tSKEW1. When tskew1 is less than minimum specification, tFRL maximum = 2*tRCLK + tSKEW1 or tRCLK + tSKEW1 The Latency Timings apply only at Empty Boundary ( EMPTY = Low) * Refer to Table 10. Diagram 6. Empty Flag Timing 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 23 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI tWCLKH tWCLKL WCLK tENS tENH tENS tENH WEN1 WEN2/ LOAD tPRAF PRAF Full -x words in Queue(2) tSKEW2(3) Full - (x + 1) words in Queue(1) tPRAF RCLK tENS tENH REN1 , REN 2 NOTES: 1. 2. 3. x = PRAF offset. 64 - x words in queue for FQV421; 128 - x words for queue for FQV621; 256 - x words in queue for FQV201; 512 - x words for FQV211; 1,024 - x words for FQV221; 2,048 - x words for FQV231; 4,096 - x words for FQV241; 8,192 - x words for FQV251. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PRAF to change during that clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PRAF may not change state until the next WCLK rising edge. Diagram 7. Programmable Full Flag Timing tWCLKH tWCLKL WCLK tENS tENH tENS tENH WEN1 WEN2/ LOAD PRAE y + 1 words in Queue y words in Queue(1) tSKEW2 (2) tPRAE tPRAE RCLK tENS tENH REN1 , REN 2 NOTES: 1. 2. y = PRAE offset tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PRAE to change during that clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tskew2, then PRAE may not change state until the next RCLK rising edge. Diagram 8. Programmable Empty Flag Timing 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 24 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI tWCLK tWCLKH tWCLKL WCLK tENS tENH LOAD tENS WEN1 tDS tDH D7 - 0 PRAE offset PRAE offset (Low Byte) (High Byte) PRAF offset PRAF offset (Low Byte) (High Byte) Diagram 9. Write Offset Registers Timing tRCLK tRCLKH tRCLKL RCLK tENS tENH LOAD tENS REN1 , REN 2 tA Q7 - 0 Output Register Data PRAE offset PRAE offset PRAF offset (Low Byte) (High Byte) (Low Byte) PRAF offset (High Byte) Diagram 10. Read Offset Registers Timing 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 25 of 26 FQV251 * FQV241 * FQV231 * FQV221 * FQV211 * FQV201 * FQV621* FQV421 FlexQTMI Order Information: HBA Device Family Device Type Power Speed (ns)* Package** Temperature Range XX FQ XXXX V251 (8,192 x 9) X Low XX 10 - 100 MHz X J X Blank - Commercial (0C to 70C) V241 (4,096 x 9) 15 - 66 MHz PF I - Industrial (-40 to 85C) V231 (2,048 x 9) 20 - 50 MHz V221 (1,024 x 9) V211 (512 x 9) V201 (256 x 9) V621 (128 x 9) V421 (64 x 9) *Speed - Slower speeds available upon request. **Package - 32 pin Plastic Lead Chip Carrier (PLCC), 32 pin Plastic Thin Quad Flat Pack (TQFP) Example: FQV241L10J FQV231L15JI (4k x 9, 10ns, Commercial temp) (2k x 9, 15ns, Industrial temp) Document Revision History: 02/07/03 pg. 1, 5, 6, 7, 8, 13, 14, 18, 19, 20, 21, 22, 23, 24, 25, 26 USA 2107 North First Street, Suite 415 San Jose, CA 95131, USA www.hba.com Tel: 408.453.8885 Fax: 408.453.8886 3F109C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Taiwan No. 81, Suite 8F-9, Shui-Lee Rd. Hsinchu, Taiwan, R.O.C. www.hba.com Tel: 886.3.516.9118 Fax: 886.3.516.9181 FEBRUARY 2003 Page 26 of 26