WME128K8-XXXE WHITE ELECTRONIC DESIGNS CORPORATION 128Kx8 CMOS MONOLITHIC EEPROM ADVANCED* FEATURES FIG. 1 Access Times of 150, 200, 250, 300ns JEDEC Approved Packages * 32 pin, Hermetic Ceramic, 0.600" DIP (Package 300) * 32 lead, Hermetic Ce.ramic, 0.400" SOJ (Package 101) PIN CONFIGURATION 32 DIP 32 CSOJ TOP VIEW RY/BY A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Organized as 128Kx8. VCC WE RESET A14 A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 CMOS: * Radiation Tolerant with Epitaxial Layer Die Commercial, Industrial and Military Temperature Ranges Write Endurance 10,000 Cycles Data Retention at 25C, 10 Years Low Power CMOS Operation Automatic Page Write Operation * Internal Address and Data Latches for 128 Bytes * Internal Control Timer Page Write Cycle Time 10ms Max. Data Polling for End of Write Detection Hardware and Software Data Protection TTL Compatible Inputs and Outputs PIN DESCRIPTION A0-16 Address Inputs I/O0-7 Data Input/Output CS Chip Select OE Output Enable WE Write Enable VCC +5.0V Power VSS Ground Reset RY/BY Ready/Busy * This data sheet describes a product that may or may not be under development and is subject to change or cancellation without notice. EEPROM MODULES RESET 5 Volt Power Supply 10 September 1998 1 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 WME128K8-XXXE WHITE ELECTRONIC DESIGNS CORPORATION ABSOLUTE MAXIMUM RATINGS Parameter Symbol Operating Temperature Unit -55 to +125 C T STG -65 to +150 C VG -0.6 to +6.25 V -0.6 to +13.5 V TA Storage Temperature Signal Voltage Relative to GND TRUTH TABLE Voltage on OE and A9 CS OE WE RESET RY/BY Mode Data I/O L L H H* High Z Read Data Out H X X X High Z Standby High Z L H L H High Z to VOL Write Data In L H H H High Z Out Disable High Z X X H X Write X L X X Inhibit L L H H VOL Data Polling Data Out (I/O7) X X X L High Z ProgramReset High Z NOTE: * Refer to the recommended DC operating conditions. X = Don't care NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAPACITANCE (TA = +25C) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Unit Supply Voltage V CC 4.5 5.5 V Input capacitance Input High Voltage V IH 2.0 V CC + 0.3 V Output capacitance Input Low Voltage V IL -0.5 +0.8 V Operating Temp. (Mil.) TA -55 +125 C Operating Temp. (Ind.) TA -40 +85 C Parameter Symbol Conditions Max Unit CIN VIN = 0 V, f = 1.0 MHz 20 pF COUT VOUT = 0 V, f = 1.0 MHz 20 pF This parameter is guaranteed by design but not tested. DC CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55C to +125C) Parameter Max Unit Input Leakage Current Symbol ILI VCC = 5.5, VIN = GND to VCC Conditions Min 10 A Output Leakage Current ILO CS = VIH, OE = VIH, VOUT = GND to VCC 10 A Operating Supply Current x 32 Mode ICC CS = VIL, OE = VIH, f = 5MHz 60 mA Standby Current ISB CS = VIH, OE = VIH, f = 5MHz 1 mA Output Low Voltage VOL IOL = 2.1mA, VCC = 4.5V Output High Voltage VOH IOH = -400A, VCC = 4.5V 0.40 V 2.4 V NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V EEPROM MODULES 10 FIG. 2 AC TEST CIRCUIT AC TEST CONDITIONS Parameter I OL Current Source VZ D.U.T. 1.5V (Bipolar Supply) C eff = 50 pf I OH Current Source White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 2 Typ Unit Input Pulse Levels VIL = 0, VIH = 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V NOTES: V Z is programmable from -2V to +7V. I OL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 . V Z is typically the midpoint of VOH and V OL. I OL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. WME128K8-XXXE WHITE ELECTRONIC DESIGNS CORPORATION AC WRITE CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55C to +125C) WRITE A write cycle is initiated when OE is high and a low pulse is on WE or CS with CS or WE low. The address is latched on the falling edge of CS or WE whichever occurs last. The data is latched by the rising edge of CS or WE, whichever occurs first. A byte write operation will automatically continue to completion. Write Cycle Parameter WRITE CYCLE TIMING Figures 3 and 4 show the write cycle timing relationships. A write cycle begins with address application, write enable and chip select. Chip select is accomplished by placing the CS line low. Write enable consists of setting the WE line low. The write cycle begins when the last of either CS or WE goes low. The WE line transition from high to low also initiates an internal 150 sec delay timer to permit page mode operation. Each subsequent WE transition from high to low that occurs before the completion of the 150 sec time out will restart the timer from zero. The operation of the timer is the same as a retriggerable one-shot. Symbol Min Max Unit 10 ms Write Cycle Time, TYP = 6ms tWC Address Set-up Time tAS 0 ns Write Pulse Width (WE or CS) tWP 250 ns Chip Select Set-up Time tCS 0 ns Address Hold Time tAH 150 ns Data Hold Time tDH 10 ns Chip Select Hold Time tCH 0 ns Data Set-up Time tDS 100 ns Output Enable Set-up Time tOES 0 ns Output Enable Hold Time tOEH 0 ns Byte Load Cycle tBL 1 s Reset High Time tRES 1 s Reset Protect Time tRP 100 s EEPROM MODULES 10 3 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 WME128K8-XXXE WHITE ELECTRONIC DESIGNS CORPORATION FIG. 3 WRITE WAVEFORMS WE CONTROLLED t WC ADDRESS t CS tCH t AH CS t BL t AS t WP WE t OEH t OES OE t DS t DH DATA IN t DB HIGH-Z t DW RY/BY t RP t RES RESET Vcc FIG. 4 WRITE WAVEFORMS CS CONTROLLED t WC ADDRESS t WS t WH t AH WE t BL t AS EEPROM MODULES 10 t CW CS t OEH t OES OE t DS t DH DATA IN t DB HIGH-Z RY/BY t RES t RP RESET Vcc White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 4 t DW WME128K8-XXXE WHITE ELECTRONIC DESIGNS CORPORATION READ The WME128K8-XXXE stores data at the memory location determined by the address pins. When CS and OE are low and WE is high, this data is present on the outputs. When CS and OE are high, the outputs are in a high impedance state. This two line control prevents bus contention. AC READ CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55C to +125C) Read Cycle Parameter Symbol -150 Min 150 -200 Max Min 200 -250 Max Min 250 -300 Max Min 300 Unit Max Read Cycle Time t RC Address Access Time t ACC 150 200 250 300 ns Chip Select Access Time t ACS 150 200 250 300 ns Output Hold from Add. Change, OE or CS t OH 0 Output Enable to Output Valid t OE 10 85 ns 0 75 10 0 75 10 ns 0 85 10 ns Chip Select or OE to High Z Output t DF 55 55 70 70 ns RESET Low to Output Float t DFR 350 350 350 350 ns RESET to Output Delay t RR 450 450 450 450 ns FIG. 5 READ WAVEFORMS t RC ADDRESS ADDRESS VALID CS t ACS t OE OE tDF tACC OUTPUT HIGH Z tOH OUTPUT VALID t DFR RESET NOTES: OE may be delayed up to tACS - tOE after the falling edge of CS without impact on tOE or by t ACC - tOE after an address change without impact on tACC . EEPROM MODULES t RR 10 5 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 WHITE ELECTRONIC DESIGNS CORPORATION DATA POLLING The WME128K8-XXXE offers a data polling feature which allows a faster method of writing to the device. Figure 6 shows the timing diagram for this function. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on D7 (for each chip.) Once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. Data polling may begin at any time during the write cycle. DATA POLLING CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55C to +125C) Parameter Symbol Min Data Hold Time tDH 10 OE Hold Time tOEH 0 OE To Output Valid tOE Max Unit ns ns 55 ns FIG. 6 DATA POLLING WAVEFORMS WE CS t OEH OE I/O7 t DH t OE HIGH Z ADDRESS EEPROM MODULES 10 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 6 WME128K8-XXXE WME128K8-XXXE WHITE ELECTRONIC DESIGNS CORPORATION PAGE WRITE OPERATION PAGE WRITE CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55C to +125C) The WME128K8-XXXE has a page write operation that allows one to 128 bytes of data to be written into the device and consecutively loads during the internal programming period. Successive bytes may be loaded in the same manner after the first data byte has been loaded. An internal timer begins a time out operation at each write cycle. If another write cycle is completed within 30s or less, a new time out period begins. Each write cycle restarts the delay period. The write cycles can be continued as long as the interval is less than the time out period. Page Mode Write Characteristics Parameter The usual procedure is to increment the least significant address lines from A0 through A6 at each write cycle. In this manner a page of up to 128 bytes can be loaded in to the EEPROM in a burst mode before beginning the relatively long interval programming cycle. After the 30s time out is completed, the EEPROM begins an internal write cycle. During this cycle the entire page of bytes will be written at the same time. The internal programming cycle is the same regardless of the number of bytes accessed. Symbol Min Max Unit 10 ms Write Cycle Time, TYP = 6ms tWC Address Set-up Time tAS 0 ns Address Hold Time (1) tAH 150 ns Data Set-up Time tDS 100 ns Data Hold Time tDH 10 ns Write Pulse Width tWP 250 ns Byte Load Cycle Time tBLC Byte Load Window tBL 100 s Data Latch Time tDL 300 ns RESET Protect Time tRP 100 s RESET High Time tRES 1 s Time to Device Busy tDB 120 ns Write Start Time tDW 150 ns 30 s 1. Page address must remain valid for duration of write cycle. FIG. 7 PAGE WRITE WAVEFORMS CS CONTROLLED(1) ADDRESS (2) A0-16 tAS tWP WE t BL tAH tDL t CS tCH t BLC t WC CS t OES t OEH OE tDH DATA IN t DW t DB HIGH-Z HIGH-Z RY/BY t RP RESET t RES Vcc NOTES: 1. t DF and t DFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. A7 - A16 are page addresses and must be same within the page write operation. EEPROM MODULES t DS 10 7 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 WHITE ELECTRONIC DESIGNS CORPORATION FIG. 8 SOFTWARE DATA PROTECTION ENABLE ALGORITHM(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA WRITES ENABLED(2) LOAD DATA A0 TO ADDRESS 5555 LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS EEPROM MODULES 10 ENTER DATA PROTECT STATE NOTES: 1. Data Format: D7 - D0 (Hex); Address Format: A16 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded. White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 8 WME128K8-XXXE WME128K8-XXXE WHITE ELECTRONIC DESIGNS CORPORATION SOFTWARE DATA PROTECTION FIG. 9 A software write protection feature may be enabled or disabled by the user. When shipped by White Microelectronics, the WE128K32-XXXE has the feature disabled. Write access to the device is unrestricted. SOFTWARE DATA PROTECTION DISABLE ALGORITHM(1) To enable software write protection, the user writes three access code bytes to three special internal locations. Once write protection has been enabled, each write to the EEPROM must use the same three byte write sequence to permit writing. After setting software data protection, any attempt to write to the device without the three-byte command sequence will start the internal write timers. No data will be written to the device, however, for the duration of tWC. The write protection feature can be disabled by a six byte write sequence of specific data to specific locations. Power transitions will not reset the software write protection. LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 Each 128K byte block of the EEPROM has independent write protection. One or more blocks may be enabled and the rest disabled in any combination. The software write protection guards against inadvertent writes during power transitions, or unauthorized modification using a PROM programmer. LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA HARDWARE DATA PROTECTION (3) These features protect against inadvertent writes to the WME128K8-XXXE. These are included to improve reliability during normal operation: LOAD DATA XX TO ANY ADDRESS(4) a) Write inhibiting Holding OE low and either CS or WE high inhibits write cycles. LOAD LAST BYTE TO LAST ADDRESS b) Noise filter Pulses of <20ns (typ) on WE or CS will not initiate a write cycle. EXIT DATA PROTECT STATE LOAD DATA 20 TO ADDRESS 5555 c) Protection by RESET EEPROM MODULES NOTES: 1. Data Format: D 7 - D0 (Hex); Address Format: A 16 - A 0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded. 10 9 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 WME128K8-XXXE WHITE ELECTRONIC DESIGNS CORPORATION PACKAGE 101: 32 LEAD, CERAMIC SOJ 21.1 (0.830) 0.25 (0.010) 3.96 (0.156) MAX 0.89 (0.035) Radius TYP 0.2 (0.008) 0.05 (0.002) 11.3 (0.446) 0.2 (0.009) 9.55 (0.376) 0.25 (0.010) 1.27 (0.050) 0.25 (0.010) PIN 1 IDENTIFIER 1.27 (0.050) TYP 19.1 (0.750) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES PACKAGE 300: 32 PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED 42.4 (1.670) 0.4 (0.016) 15.04 (0.592) 0.3 (0.012) 4.34 (0.171) 0.79 (0.031) EEPROM MODULES PIN 1 IDENTIFIER 3.2 (0.125) MIN 0.84 (0.033) 0.4 (0.014) 2.5 (0.100) TYP 1.27 (0.050) 0.1 (0.005) 0.46 (0.018) 0.05 (0.002) 0.25 (0.010) 0.05 (0.002) 15.25 (0.600) 0.25 (0.010) ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES 10 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 10 WME128K8-XXXE WHITE ELECTRONIC DESIGNS CORPORATION ORDERING INFORMATION W M E 128K 8 - XXX X X E X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads E = Epitaxial Layer DEVICE GRADE: Q M I C = = = = MIL-STD-883 Compliant Military Screened -55C to +125C Industrial -40C to +85C Commercial 0 to +70C PACKAGE TYPE: C = 32 Pin Ceramic DIP (Package 300) DE = 32 Lead CSOJ (Package 101) ACCESS TIME (ns) ORGANIZATION 128K x 8 EEPROM MONOLITHIC WHITE MICROELECTRONICS EEPROM MODULES 10 11 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520