10
EEPROM MODULES
1
WHITE ELECTRONIC DESIGNS CORPORATION
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
128Kx8 CMOS MONOLITHIC EEPROM
ADVANCED*
WME128K8-XXXE
September 1998
FEATURES
■Access Times of 150, 200, 250, 300ns
■JEDEC Approved Packages
•32 pin, Hermetic Ceramic, 0.600" DIP (Package 300)
•32 lead, Hermetic Ce.ramic, 0.400" SOJ (Package 101)
■Organized as 128Kx8.
■CMOS:
•Radiation Tolerant with Epitaxial Layer Die
■Commercial, Industrial and Military Temperature Ranges
■Write Endurance 10,000 Cycles
■Data Retention at 25°C, 10 Years
■Low Power CMOS Operation
■Automatic Page Write Operation
•Internal Address and Data Latches for 128 Bytes
•Internal Control Timer
■Page Write Cycle Time 10ms Max.
■Data Polling for End of Write Detection
■Hardware and Software Data Protection
■TTL Compatible Inputs and Outputs
■5 Volt Power Supply
* This data sheet describes a product that may or may not be under
development and is subject to change or cancellation without notice.
FIG. 1
PIN CONFIGURATION
32 DIP
32 CSOJ
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RY/BY
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
V
CC
WE
RESET
A14
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
PIN DESCRIPTION
A0-16 Address Inputs
I/O0-7 Data Input/Output
CS Chip Select
OE Output Enable
WE Write Enable
VCC +5.0V Power
VSS Ground
RESET Reset
RY/BY Ready/Busy
2
10
EEPROM MODULES
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WHITE ELECTRONIC DESIGNS CORPORATION WME128K8-XXXE
ABSOLUTE MAXIMUM RATINGS TRUTH TABLE
FIG. 2
AC TEST CIRCUIT AC TEST CONDITIONS
I
Current Source
D.U.T.
C = 50 pf
eff
IOL
V ≈ 1.5V
(Bipolar Supply)
Z
Current Source OH
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
RECOMMENDED OPERATING CONDITIONS
DC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter Typ Unit
Input Pulse Levels VIL = 0, VIH = 3.0 V
Input Rise and Fall 5 ns
Input and Output Reference Level 1.5 V
Output Timing Reference Level 1.5 V
Parameter Symbol Unit
Operating Temperature TA-55 to +125 °C
Storage Temperature TSTG -65 to +150 °C
Signal Voltage Relative to GND VG-0.6 to +6.25 V
Voltage on OE and A9 -0.6 to +13.5 V
NOTE:
Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
CS OE WE RESET RY/BY Mode Data I/O
L L H H* High Z Read Data Out
H X X X High Z Standby High Z
L H L H High Z to VOL Write Data In
L H H H High Z Out Disable High Z
X X H X Write
X L X X Inhibit
LL H H VOL Data Polling Data Out (I/O7)
X X X L High Z ProgramReset High Z
NOTE:
* Refer to the recommended DC operating conditions.
X = Don't care
Parameter Symbol Min Max Unit
Supply Voltage VCC 4.5 5.5 V
Input High Voltage VIH 2.0 VCC + 0.3 V
Input Low Voltage VIL -0.5 +0.8 V
Operating Temp. (Mil.) TA-55 +125 °C
Operating Temp. (Ind.) TA-40 +85 °C
Parameter Symbol Conditions Min Max Unit
Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC 10 µA
Output Leakage Current ILO CS = VIH, OE = VIH, VOUT = GND to VCC 10 µA
Operating Supply Current x 32 Mode ICC CS = VIL, OE = VIH, f = 5MHz 60 mA
Standby Current ISB CS = VIH, OE = VIH, f = 5MHz 1 mA
Output Low Voltage VOL IOL = 2.1mA, VCC = 4.5V 0.40 V
Output High Voltage VOH IOH = -400µA, VCC = 4.5V 2.4 V
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
CAPACITANCE
(TA = +25°C)
Parameter
Symbol
Conditions Max Unit
Input capacitance CIN
V
IN
= 0 V, f = 1.0 MHz
20 pF
Output capacitance COUT
V
OUT
= 0 V, f = 1.0 MHz
20 pF
This parameter is guaranteed by design but not tested.
10
EEPROM MODULES
3
WHITE ELECTRONIC DESIGNS CORPORATION
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WME128K8-XXXE
WRITE
A write cycle is initiated when OE is high and a low pulse is on WE
or CS with CS or WE low. The address is latched on the falling
edge of CS or WE whichever occurs last. The data is latched by
the rising edge of CS or WE, whichever occurs first. A byte write
operation will automatically continue to completion.
WRITE CYCLE TIMING
Figures 3 and 4 show the write cycle timing relationships. A
write cycle begins with address application, write enable and
chip select. Chip select is accomplished by placing the CS line
low. Write enable consists of setting the WE line low. The
write cycle begins when the last of either CS or WE goes low.
The WE line transition from high to low also initiates an
internal 150 µsec delay timer to permit page mode operation.
Each subsequent WE transition from high to low that occurs
before the completion of the 150 µsec time out will restart the
timer from zero. The operation of the timer is the same as a
retriggerable one-shot.
AC WRITE CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Write Cycle Parameter Symbol Min Max Unit
Write Cycle Time, TYP = 6ms tWC 10 ms
Address Set-up Time tAS 0ns
Write Pulse Width (WE or CS) tWP 250 ns
Chip Select Set-up Time tCS 0ns
Address Hold Time tAH 150 ns
Data Hold Time tDH 10 ns
Chip Select Hold Time tCH 0ns
Data Set-up Time tDS 100 ns
Output Enable Set-up Time tOES 0ns
Output Enable Hold Time tOEH 0ns
Byte Load Cycle tBL 1 µs
Reset High Time tRES 1µs
Reset Protect Time tRP 100 µs
4
10
EEPROM MODULES
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WHITE ELECTRONIC DESIGNS CORPORATION WME128K8-XXXE
FIG. 3
WRITE WAVEFORMS
WE CONTROLLED
FIG. 4
WRITE WAVEFORMS
CS CONTROLLED
t
DATA IN
DH
t
WP
t
OEH
t
AH
t
OES
t
AS
t
CS
t
CH
t
WC
t
DS
CS
t
BL
OE
WE
ADDRESS
RESET
Vcc
t
RES
t
RP
RY/BY
DB
t
DW
t
HIGH-Z
t
DATA IN
DH
t
CW
t
OEH
t
AH
t
OES
t
AS
t
WS
t
WH
t
WC
t
DS
WE
t
BL
OE
CS
RESET
Vcc
ADDRESS
t
RES
t
RP
RY/BY
DB
t
DW
t
HIGH-Z
10
EEPROM MODULES
5
WHITE ELECTRONIC DESIGNS CORPORATION
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WME128K8-XXXE
AC READ CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
READ
The WME128K8-XXXE stores data at the memory location
determined by the address pins. When CS and OE are low and
WE is high, this data is present on the outputs. When CS and
OE are high, the outputs are in a high impedance state. This
two line control prevents bus contention.
Read Cycle Parameter Symbol -150 -200 -250 -300 Unit
Min Max Min Max Min Max Min Max
Read Cycle Time tRC 150 200 250 300 ns
Address Access Time tACC 150 200 250 300 ns
Chip Select Access Time tACS 150 200 250 300 ns
Output Hold from Add. Change, OE or CS tOH 0000ns
Output Enable to Output Valid tOE 10 75 10 75 10 85 10 85 ns
Chip Select or OE to High Z Output tDF 55 55 70 70 ns
RESET Low to Output Float tDFR 350 350 350 350 ns
RESET to Output Delay tRR 450 450 450 450 ns
FIG. 5
READ WAVEFORMS
t
ADDRESS
CS
OE
OUTPUT
OH
t
DF
t
ACC
t
RC
t
OE
t
ACS
OUTPUT
VALID
ADDRESS VALID
HIGH Z
RESET t
DFR
t
RR
NOTES:
OE may be delayed up to tACS - tOE after the
falling edge of CS without impact on tOE or by
tACC - tOE after an address change without
impact on tACC.
6
10
EEPROM MODULES
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WHITE ELECTRONIC DESIGNS CORPORATION WME128K8-XXXE
DATA POLLING
The WME128K8-XXXE offers a data polling feature which
allows a faster method of writing to the device. Figure 6
shows the timing diagram for this function. During a byte or
page write cycle, an attempted read of the last byte written
will result in the complement of the written data on D7 (for
each chip.) Once the write cycle has been completed, true data
is valid on all outputs and the next cycle may begin. Data
polling may begin at any time during the write cycle.
DATA POLLING CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
FIG. 6
DATA POLLING
WAVEFORMS
Parameter Symbol Min Max Unit
Data Hold Time tDH 10 ns
OE Hold Time tOEH 0ns
OE To Output Valid tOE 55 ns
WE
tOEH
tDH tOE
HIGH Z
CS
OE
I/O7
ADDRESS
10
EEPROM MODULES
7
WHITE ELECTRONIC DESIGNS CORPORATION
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
PAGE WRITE OPERATION
The WME128K8-XXXE has a page write operation that allows one
to 128 bytes of data to be written into the device and consecutively
loads during the internal programming period. Successive bytes
may be loaded in the same manner after the first data byte has
been loaded. An internal timer begins a time out operation at each
write cycle. If another write cycle is completed within 30µs or
less, a new time out period begins. Each write cycle restarts the
delay period. The write cycles can be continued as long as the
interval is less than the time out period.
The usual procedure is to increment the least significant
address lines from A0 through A6 at each write cycle. In this
manner a page of up to 128 bytes can be loaded in to the
EEPROM in a burst mode before beginning the relatively long
interval programming cycle.
After the 30µs time out is completed, the EEPROM begins an
internal write cycle. During this cycle the entire page of bytes
will be written at the same time. The internal programming
cycle is the same regardless of the number of bytes accessed.
PAGE WRITE CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
FIG. 7
PAGE WRITE WAVEFORMS
CS CONTROLLED(1)
WME128K8-XXXE
1. Page address must remain valid for duration of write cycle.
Page Mode Write Characteristics
Parameter Symbol Min Max Unit
Write Cycle Time, TYP = 6ms tWC 10 ms
Address Set-up Time tAS 0ns
Address Hold Time (1) tAH 150 ns
Data Set-up Time tDS 100 ns
Data Hold Time tDH 10 ns
Write Pulse Width tWP 250 ns
Byte Load Cycle Time tBLC 30 µs
Byte Load Window tBL 100 µs
Data Latch Time tDL 300 ns
RESET Protect Time tRP 100 µs
RESET High Time tRES 1µs
Time to Device Busy tDB 120 ns
Write Start Time tDW 150 ns
DATA IN
t
CS t
CH
t OEH
t
WP
t
OES
t
BLC
t
AS t
AH t
BL
t WC
t
DS
WE t
DL
OE
RY/BY
CS
RESET
Vcc
ADDRESS (2)
A0-16
t RES
t
RP
t
DH
t
DB
HIGH-Z HIGH-Z
t
DW
NOTES:
1. tDF and tDFR are defined as the time at which the outputs achieve the
open circuit conditions and are no longer driven.
2. A7 - A16 are page addresses and must be same within the page write
operation.
8
10
EEPROM MODULES
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WHITE ELECTRONIC DESIGNS CORPORATION
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
WME128K8-XXXE
FIG. 8
SOFTWARE DATA PROTECTION
ENABLE ALGORITHM(1)
➞
➞➞➞
WRITES ENABLED(2)
NOTES:
1. Data Format: D7 - D0 (Hex);
Address Format: A16 - A0 (Hex).
2. Write Protect state will be activated at end of write even if no other
data is loaded.
3. Write Protect state will be deactivated at end of write period even if
no other data is loaded.
4. 1 to 128 bytes of data may be loaded.
ENTER DATA
PROTECT STATE
10
EEPROM MODULES
9
WHITE ELECTRONIC DESIGNS CORPORATION
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
HARDWARE DATA PROTECTION
These features protect against inadvertent writes to the
WME128K8-XXXE. These are included to improve reliability
during normal operation:
a) Write inhibiting
Holding OE low and either CS or WE high inhibits write
cycles.
b) Noise filter
Pulses of <20ns (typ) on WE or CS will not initiate a write
cycle.
c) Protection by RESET
SOFTWARE DATA PROTECTION
A software write protection feature may be enabled or disabled
by the user. When shipped by White Microelectronics, the WE-
128K32-XXXE has the feature disabled. Write access to the
device is unrestricted.
To enable software write protection, the user writes three
access code bytes to three special internal locations. Once
write protection has been enabled, each write to the EEPROM
must use the same three byte write sequence to permit writing.
After setting software data protection, any attempt to write to
the device without the three-byte command sequence will start
the internal write timers. No data will be written to the device,
however, for the duration of tWC. The write protection feature
can be disabled by a six byte write sequence of specific data to
specific locations. Power transitions will not reset the
software write protection.
Each 128K byte block of the EEPROM has independent write
protection. One or more blocks may be enabled and the rest
disabled in any combination. The software write protection
guards against inadvertent writes during power transitions, or
unauthorized modification using a PROM programmer.
FIG. 9
SOFTWARE DATA PROTECTION
DISABLE ALGORITHM(1)
➞ ➞
➞➞➞➞➞
EXIT DATA
PROTECT STATE
WME128K8-XXXE
NOTES:
1. Data Format: D7 - D0 (Hex);
Address Format: A16 - A0 (Hex).
2. Write Protect state will be activated at end of write even if no other
data is loaded.
3. Write Protect state will be deactivated at end of write period even if
no other data is loaded.
4. 1 to 128 bytes of data may be loaded.
(3)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
10
10
EEPROM MODULES
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WHITE ELECTRONIC DESIGNS CORPORATION WME128K8-XXXE
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 101: 32 LEAD, CERAMIC SOJ
1.27 (0.050) TYP
21.1 (0.830) ± 0.25 (0.010)
PIN 1 IDENTIFIER
19.1 (0.750) TYP
11.3 (0.446)
± 0.2 (0.009)
3.96 (0.156) MAX
0.2 (0.008)
± 0.05 (0.002)
9.55 (0.376) ± 0.25 (0.010)
1.27 (0.050) ± 0.25 (0.010)
0.89 (0.035)
Radius TYP
PACKAGE 300: 32 PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED
2.5 (0.100)
TYP 1.27 (0.050)
± 0.1 (0.005) 0.46 (0.018)
± 0.05 (0.002)
0.84 (0.033)
± 0.4 (0.014)
3.2 (0.125) MIN
15.04 (0.592)
± 0.3 (0.012)
0.25 (0.010)
± 0.05 (0.002)
15.25 (0.600)
± 0.25 (0.010)
42.4 (1.670) ± 0.4 (0.016)
4.34 (0.171) ± 0.79 (0.031)
PIN 1 IDENTIFIER
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
10
EEPROM MODULES
11
WHITE ELECTRONIC DESIGNS CORPORATION
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
E = Epitaxial Layer
DEVICE GRADE:
Q = MIL-STD-883 Compliant
M = Military Screened -55°C to +125°C
I = Industrial -40°C to +85°C
C = Commercial 0 to +70°C
PACKAGE TYPE:
C = 32 Pin Ceramic DIP (Package 300)
DE = 32 Lead CSOJ (Package 101)
ACCESS TIME (ns)
ORGANIZATION 128K x 8
EEPROM
MONOLITHIC
WHITE MICROELECTRONICS
ORDERING INFORMATION
W M E 128K 8 - XXX X X E X
WME128K8-XXXE
