LM392-N
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SNOSBT5D APRIL 1998REVISED MARCH 2013
lm392-N Low Power Operational Amplifier/Voltage Comparator
Check for Samples: LM392-N
1FEATURES DESCRIPTION
The lm392-N series consists of 2 independent
2 Wide Power Supply Voltage Range building block circuits. One is a high gain, internally
Single Supply: 3V to 32V frequency compensated operational amplifier, and the
Dual Supply: ±1.5V to ±16V other is a precision voltage comparator. Both the
operational amplifier and the voltage comparator
Low Supply Current Drain—Essentially have been specifically designed to operate from a
Independent of Supply Voltage: 600 μAsingle power supply over a wide range of voltages.
Low Input Biasing Current: 50 nA Both circuits have input stages which will common-
Low Input Offset Voltage: 2 mV mode input down to ground when operating from a
single power supply. Operation from split power
Low Input Offset Current: 5 nA supplies is also possible and the low power supply
Input Common-Mode Voltage Range Includes current is independent of the magnitude of the supply
Ground voltage.
Differential Input Voltage Range Equal to the Application areas include transducer amplifier with
Power Supply Voltage pulse shaper, DC gain block with level detector, VCO,
ADDITIONAL OP AMP FEATURES as well as all conventional operational amplifier or
voltage comparator circuits. Both circuits can be
Internally Frequency Compensated for operated directly from the standard 5 VDC power
Unity Gain supply voltage used in digital systems, and the output
Large DC Voltage Gain: 100 dB of the comparator will interface directly with either
Wide Bandwidth (Unity Gain): 1 MHz TTL or CMOS logic. In addition, the low power drain
makes the lm392-N extremely useful in the design of
Large Output Voltage Swing: 0V to V+portable equipment.
1.5V
ADDITIONAL COMPARATOR FEATURES
Low Output Saturation Voltage: 250 mV at 4
mA
Output Voltage Compatible with all Types
of Logic Systems
ADVANTAGES
Eliminates Need for Dual Power Supplies
An Internally Compensated Op Amp and a
Precision Comparator in the Same Package
Allows Sensing at or Near Ground
Power Drain Suitable for Battery Operation
Pin-Out is the Same as Both the LM358 Dual
Op Amp and the LM393 Dual Comparator
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1998–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM392-N
SNOSBT5D APRIL 1998REVISED MARCH 2013
www.ti.com
Connection Diagram
Top View
(Amplifier A = Comparator)
(Amplifier B = Operational Amplifier)
Figure 1. SOIC and PDIP Packages
See Package Numbers D0008A and P0008E
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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LM392-N
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SNOSBT5D APRIL 1998REVISED MARCH 2013
Absolute Maximum Ratings (1)(2)
lm392-N
Supply Voltage, V+32V or ±16V
Differential Input Voltage 32V
Input Voltage 0.3V to +32V
Power Dissipation (3)
Molded DIP (LM392N) 820 mW
Small Outline Package (LM392M) 530 mW
Output Short-Circuit to Ground (4) Continuous
Input Current (VIN <0.3 VDC)(5) 50 mA
Operating Temperature Range 0°C to +70°C
Storage Temperature Range 65°C to +150°C
Lead Temperature (Soldering, 10 seconds) 260°C
ESD rating to be determined.
Soldering Information
Dual-in-Line Package
Soldering (10 seconds) 260°C
Small Outline Package
Vapor Phase (60 seconds) 215°C
Infrared (15 seconds) 220°C
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) For operating at temperatures above 25°C, the lm392-N must be derated based on a 125°C maximum junction temperature and a
thermal resistance of 122°C/W which applies for the device soldered in a printed circuit board, operating in still air ambient. The
dissipation is the total of both amplifiers—use external resistors, where possible, to allow the amplifier to saturate or to reduce the power
which is dissipated in the integrated circuit.
(4) Short circuits from the output to V+can cause excessive heating and eventual destruction. When considering short circuits to ground,
the maximum output current is approximately 40 mA for the op amp and 30 mA for the comparator independent of the magnitude of V+.
At values of supply voltage in excess of 15V, continuous short circuits can exceed the power dissipation ratings and cause eventual
destruction.
(5) This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of
the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is
also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the amplifiers to go to
the V+voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive and
normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than 0.3V (at 25°C).
Electrical Characteristics
(V+= 5 VDC; specifications apply to both amplifiers unless otherwise stated) (1)
lm392-N
Parameter Conditions Units
Min Typ Max
Input Offset Voltage TA= 25°C, (2) ±2 ±5 mV
Input Bias Current IN(+) or IN(), TA=25°C, (3) , VCM = 0V 50 250 nA
Input Offset Current IN(+) IN(), TA= 25°C ±5 ±50 nA
Input Common-Mode Voltage Range V+= 30 VDC, TA= 25°C, (4) 0 V+1.5 V
Supply Current RL=, V+= 30 V 1 2 mA
Supply Current RL=, V+= 5 V 0.5 1 mA
(1) These specifications apply for V+= 5V, unless otherwise stated. For the lm392-N, temperature specifications are limited to 0°C TA
+70°C.
(2) At output switch point, VO1.4V, RS= 0Ωwith V+from 5V to 30V; and over the full input common-mode range (0V to V+1.5V).
(3) The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the input lines.
(4) The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end
of the common-mode voltage range is V+1.5V, but either or both inputs can go to 32V without damage.
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SNOSBT5D APRIL 1998REVISED MARCH 2013
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Electrical Characteristics (continued)
(V+= 5 VDC; specifications apply to both amplifiers unless otherwise stated) (1)
lm392-N
Parameter Conditions Units
Min Typ Max
Amplifier-to-Amplifier Coupling f = 1 kHz to 20 kHz, TA= 25°C, Input Referred, (5) 100 dB
Input Offset Voltage (2) ±7 mV
Input Bias Current IN(+) or IN() 400 nA
Input Offset Current IN(+) IN() 150 nA
Input Common-Mode Voltage Range V+= 30 VDC,(4) 0 V+2 V
Differential Input Voltage Keep All VIN's0 VDC (or V, if used ) (6) 32 V
OP AMP ONLY
Large Signal Voltage Gain V+= 15 VDC, Voswing = 1 VDC to 11 VDC, RL= 2 25 100 V/mV
kΩ, TA= 25°C
Output Voltage Swing RL= 2 kΩ, TA= 25°C 0 V+1.5 V
Common-Mode Rejection Ratio DC, TA= 25°C, VCM= 0, VDC to V+1.5 VDC 65 70 dB
Power Supply Rejection Ratio DC, TA= 25°C 65 100 dB
Output Current Source VIN(+) = 1 VDC, VIN()= 0 VDC,20 40 mA
V+= 15 VDC, Vo= 2 VDC, TA= 25°C
Output Current Sink VIN()= 1 VDC, VIN(+) = 0 VDC, 10 20 mA
V+= 15 VDC, Vo=2VDC, TA= 25°C
VIN()= 1 VDC, VIN(+) = 0 VDC, 12 50 µA
V+= 15 VDC, Vo=200 mV, TA= 25°C
Input Offset Voltage Drift RS= 0Ω7μV/°C
Input Offset Current Drift RS= 0Ω10 pADC/°C
COMPARATOR ONLY
Voltage Gain RL15 kΩ, V+= 15 VDC, TA= 25°C 50 200 V/mV
Large Signal Response Time(7) VIN = TTL Logic Swing, VREF = 1.4 VDC 300 ns
VRL = 5 VDC, RL= 5.1 k, TA= 25°C
Response Time VRL = 5 VDC, RL= 5.1 k, TA= 25°C 1.3 µs
Output Sink Current VIN()=1 VDC, VIN(+) = 0 VDC, 6 16 mA
VO1.5 VDC, TA= 25°C
Saturation Voltage VIN()1 VDC, VIN(+) = 0, 250 400 mV
ISINK 4 mA, TA= 25°C
VIN()1 VDC, VIN(+) = 0, 700 mV
ISINK 4 mA
Output Leakage Current VIN()= 0, VIN(+) 1 VDC, 0.1 nA
Vo= 5 VDC, TA= 25°C
VIN()= 0, VIN(+) 1 VDC, 1.0 μA
Vo= 30 VDC
(5) Due to proximity of external components, insure that coupling is not originating via the stray capacitance between these external parts.
This typically can be detected as this type of capacitive coupling increases at higher frequencies.
(6) Positive excursions of input voltage may exceed the power supply level. As long as the other input voltage remains within the common-
mode range, the comparator will provide a proper output state. The input voltage to the op amp should not exceed the power supply
level. The input voltage state must not be less than 0.3V (or 0.3V below the magnitude of the negative power supply, if used) on either
amplifier.
(7) The response time specified is for a 100 mV input step with 5 mV overdrive. For larger overdrive signals 300 ns can be obtained.
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SNOSBT5D APRIL 1998REVISED MARCH 2013
Schematic Diagram
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LM392-N
SNOSBT5D APRIL 1998REVISED MARCH 2013
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APPLICATION HINTS
Please refer to the application hints section of the LM193 and the LM158 datasheets.
6Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated
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LM392-N
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SNOSBT5D APRIL 1998REVISED MARCH 2013
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 6
Copyright © 1998–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM392M ACTIVE SOIC D 8 95 Non-RoHS
& Green Call TI Call TI 0 to 70 LM392
M
LM392M/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM 0 to 70 LM392
M
LM392MX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM 0 to 70 LM392
M
LM392N/NOPB ACTIVE PDIP P 8 40 RoHS & Green Call TI | SN Level-1-NA-UNLIM 0 to 70 LM
392N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM392MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Sep-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM392MX/NOPB SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Sep-2019
Pack Materials-Page 2
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PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
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EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
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EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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