Freescale Semiconductor
Data Sheet: Technical Data Document Number: MPC5668X
Rev. 6, 03/2011
© Freescale Semiconductor, Inc., 2010, 2011. All rights reserved.
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
MPC5668x
MAPBGA–208
17 mm x 17 mm MAPBGA–256
17 mm x 17 mm
MPC5668x features:
32-bit CPU core complex (e200z650)
Compliant with Power Architecture embedded category
32 KB unified cache with line locking and eight-entry
store buffer16
Execution speed static to 116 MHz
32-bit I/O processor (e200z0)
Execution speed static to 1/2 CPU core speed (58 MHz)
2 MB on-chip flash
Supports read during program and erase operations, and
multiple blocks allowing EEPRO M emul ation
512 KB + 80 KB (592 KB) on-chip ECC SRAM
(MPC5668G)
128 KB on-chip ECC SRAM (MPC5668 E)
16-entry Memory Protection Unit (MPC5668E only)
Direct memory access controller
16-channel on MPC5668G
32-channel on MPC5668E
Fast ethernet controller
Supports 10-Mbps and 100-Mbps IEEE 802.3 MII,
10-Mbps 7-wire interface
IEEE 802.3 MAC (compliant with IEEE 802.3 1998
edition)
Media Local Bus (MLB) interface (MPC5668G only)
Supports 16 logical channels, max speed 1024 Fs
Interrupt controller (INTC) supports 316 external interrupt
vectors (22 are reserved)
System clocks
Frequency-modulated phase-locked loop (FMPLL)
4–40MHz crystal oscillator (XTAL)
32 kHz crystal oscillator (XTAL)
Dedicated 16 MHz and 128 kHz internal RC oscillators
Analog to Digital Converter (ADC) module
10-bit A/D resolution
32 external channels
36 internal channels (MPC5668G)
64 internal channels (MPC5668E)
Cross-Triggering Unit (MPC5668E only)
Internal conversion triggering for ADC
Triggerable by internal timers or eMIOS200
Deserial Serial Peripheral Interface (DSPI)
Four individual DSPI modul es
Full duplex, synchronous transfers
Master or slave operation
Inter-IC communication (I2C) interface
Four individual I2C modules
Multi-master operation
Serial Communication Interface (eSCI) module
Two-channel DMA interface
Configurable as LIN bus master
eMIOS200 timed input/output
24 channels, 16-bit timers (MPC5668G)
32 channels, 16-bit timers (MPC56 68E)
Controller Area Network (FlexCAN) module
Compliant with CAN protocol specification, Version
2.0B active
64 mailboxes, each configurable as transmit or receive
Dual-channel FlexRay controller
Full implementation of FlexRay Protocol Specification
2.1, RevA
128 message buffers
JTAG controller (MPC5668G only)
Compliant with the IEEE 11 49.1-2001
Nexus Development Interface (NDI)
Available in 256 M APBGA package only
Compliant with IEEE-ISTO 5001-2003
Nexus class 3 development support on e200z650
Nexus class 2+ development support on e200z0
Internal voltage regulator allows operation from single
3.3 V or 5 V su pp ly
MPC5668x Microcontroller
Data Sheet
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor2
Table of Contents
1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Orderable Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2 MPC5668x Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.1 208-ball MAPBGA Pin Assignments. . . . . . . . . . . . . . . .6
3.2 256-ball MAPBGA Pin Assignments. . . . . . . . . . . . . . . .7
3.3 Pin Muxing and Reset States . . . . . . . . . . . . . . . . . . . . .8
3.3.1 Power and Ground Supply Summary . . . . . . . .25
4 Electrical Characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .27
4.2.1 General Notes for Specifications at Maximum
Junction Temperature . . . . . . . . . . . . . . . . . . . .27
4.3 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.4 VRC Electrical Specifications . . . . . . . . . . . . . . . . . . . .30
4.5 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .30
4.6 Operating Current Specifications . . . . . . . . . . . . . .32
4.7 I/O Pad Current Specifications . . . . . . . . . . . . . . . . . . .34
4.7.1 I/O Pad VDD33 Current Specifications . . . . . . . .35
4.8 Low Voltage Characteristics . . . . . . . . . . . . . . . . . . . . 36
4.9 Oscillators Electrical Characteristics . . . . . . . . . . . . . . 36
4.10 FMPLL Electrical Characteristics. . . . . . . . . . . . . . . . . 38
4.11 ADC Electrical Characteristics. . . . . . . . . . . . . . . . . . . 39
4.12 Flash Memory Electrical Characteristics . . . . . . . . . . . 39
4.13 Pad AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.14 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.14.1 Reset and Boot Configuration Pins . . . . . . . . . 43
4.14.2 External Interrupt (IRQ) and Non-Maskable
Interrupt (NMI) Pins . . . . . . . . . . . . . . . . . . . . . 43
4.14.3 JTAG (IEEE 1149.1) Interface . . . . . . . . . . . . . 44
4.14.4 Nexus Debug Interface. . . . . . . . . . . . . . . . . . . 47
4.14.5 Enhanced Modular I/O Subsystem (eMIOS) . . 49
4.14.6 Deserial Serial Peripheral Interface (DSPI) . . . 50
4.14.7 MLB Interface. . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.14.8 Fast Ethernet Interface . . . . . . . . . . . . . . . . . . 57
5 Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.1 Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . 61
6 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 1. MPC5668G/MPC5668E Comparison
Feature MPC5668G MPC5668E
Package 208 MAPBGA 256 MAPBGA 208 MAPBGA 256 MAPBGA
RAM with ECC 592 KB 128 KB
MPU No 16 entry
DMA 16-channel 32-channel
Ethernet (FEC) Yes No
MediaLB (MLB-DIM) Yes No
FlexRay Yes (128 Message Buffers) No
ADC (10-bit) 36 internal channels
Supports 32 external channels 64 internal channels
Supports 32 external channels
Total Timer I/O (eMIOS200) 24 channels, 16-bit 32 channels, 16-bit
Cross Trigger Unit (CTU) No Yes
SCI (eSCI) 6 12
SPI (DSPI) 4 4
CAN (FlexCAN) 6 5
I2C44
Nexus3 Debug (e200Z6)
Nexus2+ Debug (e200Z0) Supported on 256BGA
emulation package Supported on 256BGA
emulation package
Ordering Information
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 3
1 Ordering Information
1.1 Orderable Parts
Table 1 show s th e orderable part num bers for the MPC5668x.
Table 1. Orderable Part Numbers
Freescale Part Number1
1All packaged devices are PPC5668x, rather than MPC5668x or SPC5668x, until product qualifications are complete. The
unpackaged device prefix is PCC, rather than SCC, until product qualification is complete.
Not all configurations are available in the PPC parts.
Package D escription Speed (MHz) Operating Temperature2
2The lowest ambient operating temperature (T A) is referenced by TL; the highest ambient operating temperature is referenced
by TH.
Max3 (fMAX)
3Maximum speed is the maximum frequency allowed including frequency modulation (FM).
Min (TL)Max (T
H)
PPC5668GF1AVMJ4
4The 256 MAPBGA package for the MPC5668x is not intended for full production qualification, and is supplied for
dev el o pment use only.
MPC5668G 256 MAPBGA package
Lead-free (PbFree) 116 –40 °C 105 °C
SPC5668GF1AMMG MPC5668G 208 MAPBGA package
Lead-free (PbFree) 116 –40 °C 125 °C
SPC5668EF1A VMG MPC5668G 208 MAPBGA package
Lead-free (PbFree) 116 –40 °C 105 °C
SPC5668EF1A VMGR MPC5668G 208 MAPBGA package
Lead-free (PbFree) 116 –40 °C 105 °C
SPC5668GF1AMMGR MPC5668G 208 MAPBGA package
Lead-free (PbFree) 116 –40 °C 125 °C
SPC5668GF1A VMG MPC5668G 208 MAPBGA package
Lead-free (PbFree) 116 –40 °C 105 °C
SPC5668GF1A VMGR MPC5668G 208 MAPBGA package
Lead-free (PbFree) 116 –40 °C 105 °C
SPC F MG
R
Qualification status
Core code
De vice number
Fabrication Site
Revision
Temperature range
Package identifier
Tape and reel status
Temperature Range
V = –40 °C to 105 °C
M =4C to 12C
Package Identifier
MG = 208 MAPBGA Pb-free
MJ = 256 MAPBGA Pb-free
Core Code PC = Power Architecture Ta pe and Reel Status
R = Tape and reel
(blank) = Trays
Qualification Status
P = Prototype
M = Fully spec. qualified, general market flow
S = Fully spec. qu alified, automotive flow
Note: Not all options are available on all devices. Refer to Table 1.
5668G 0A
V
Fabrication Site
F = Freescale
MPC5668x Microcontroller Data Sheet, Rev. 6
MPC5668x Block Diagrams
Freescale Semiconductor4
2 MPC5668x Block Diagrams
Figure 1 shows a top-level block diagram of the MPC5668G device.
Figure 1. MPC5668G Block Diagram
ADC – Analog to Digital Converter
BAM – Boot Assist Module
DSPI – Serial Peripherals Interface
ECC – Error Correction Code
ECSM – Error Correction Status Module
eMIOS – Timed Input Output
eDMA – Enhanced Direct Memory Access controller
eSCI – Serial Communications Interface
FEC – Fast Ethernet Controller
FlexCAN – Controller Area Network controller
FlexRay™ – FlexRay Bus Controller
FMPLL – Frequency Modulated Phase Locked Loop
4–40 MHz
SPP Crossbar Switch (XBAR)
FMPLL
e200z650 Core
32K Cache
16ChDMA
16 MHz
FPU/SPE
VLE
MMU(32TLB)
LEGEND
e200z0 Core
VLE
MASTERS
Mux
Flash
(ECC)
SRAM
(ECC)
512 KB
2 MB
AIPS(0) Bridge B
6 x eSCI
36 x ADC
2 x I2C
2 x DSPI
24 x eMIOS 6 x FlexCAN
JTAG
NDI
Nexus3(Z6)
DEBUG
NDI
Nexus2+(Z0)
AIPS(1) Bridge A
2 x I2C
2 x DSPI
VREG
4/8 Way FEC MLB-DIM FlexRay
ControllerIRCXTAL
MPC5668G
Standby RAM
SRAM
(ECC)
80 KB
I2C– Inter IC Controller
INTC – Interrupt Controller
JTAG – Joint Test Action Group interface
MLB-DIM – Media Local Bus Device Interface Module
NDI – Nexus Debug Interface
PIT – Periodic Interrupt Timer
RTC – Real Time Clock
SIU – System Integration
STM System Timer Module
SWT – Software Watchdog Timer
VREG – Voltage Regulator
128 kHz
IRC
32 kHz
XTAL
SWT
INTC
SIU
PIT
BAM
RTC/API
STM
ECSMECSM ECSM
Semaphores
MPC5668x Block Diagrams
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 5
Figure 2 shows a top level block diagram for the MPC5668E device.
Figure 2. MPC5668E Block Diagram
I2C– Inter IC Controller
INTC – Interrupt Controller
JTAG – Joint Test Action Group interface
MPU – Memory Protection Unit
NDI – Nexus Debug Interface
PIT – Periodic Interrupt Timer
RTC – Real Time Clock
SIU – System Integration
STM System Timer Module
SWT – Software Watchdog Timer
VREG – Voltage Regulator
ADC – Analog to Digital Converter
BAM – Boot Assist Module
CTU – Cross Triggering Unit
DSPI – Serial Peripherals Interface controller
ECC – Error Correction Code
ECSM – Error Correction Status Module
eDMA – Enhanced Direct Memory Access controller
eMIOS200 – Timed Input Output
eSCI – Serial Communications Interface
FlexCAN – Controller Area Network controller
FMPLL – Frequency Modulated Phase Locked Loop
4–40 MHz
SPP Crossbar Switch (XBAR)
FMPLL
e200z650 Core
32K Cache
16 MHz
128 kHz
FPU/SPE
VLE
MMU(32TLB)
LEGEND
32 kHz
e200z0 Core
VLE
MASTERS
Mux
Memory Protection Unit (MPU)
Flash
(ECC)
SRAM
(ECC)
128 KB
2 MB
AIPS(0) Bridge B
64 x ADC
32 x eMIOS
5 x FlexCAN
2 x DSPI
8 x eSCI
CTU
2 x I2C
JTAG
NDI
Nexus3(Z6)
DEBUG
NDI
Nexus2+(Z0)
AIPS(1) Bridge A
4 x eSCI
2 x I2C
2 x DSPI
SWT
VREG
INTC
SIU
PIT
BAM
RTC/API
STM
4/8 Way
ControllerIRCXTAL XTAL
IRC
MPC5668E
Standby RAM
Semaphores
32ChDMA
Standby RAM
ECSMECSM
MPC5668x Microcontroller Data Sheet, Rev. 6
Pin Assignments
Freescale Semiconductor6
3 Pin Assignments
3.1 208-ball MAPBGA Pin Assignments
Figure 3 shows the 208-ball MAPBGA pin assignments.
Figure 3. MPC5668x 208-ball MAPBGA (ful l diagram)
Note: This ballmap is preliminary and
should not be used for board
design.
V
DD33
TEST
V
DD
1 2 3 4 5 6 7 8 9 10111213141516
V
DDA
PA8
V
SSA
PB14
PB6
PC3
PC7
PC10 V
RCCTL
V
DD
A
V
DD
V
RH
V
RL
PA12
PB0
PB5PC0PC4
PC8PC11
PC12
B
V
SS
PA9PA11 PA15
PB1PB4
PB7
PC1PC5
PC9
V
SS
PC13PC14
C
V
SS
PA10 PA14
PB11
V
DDE1
V
SS
PD0
PD1
D
PD2
PD3 PD4
E
PD6
PD7
PD9
F
PD8
GV
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
PE6
H
V
SS
V
SS
V
SS
V
SS
PE9
PD14
J
PD15
PE0
K
PE1
L
M
V
SS
PF0
V
SS
N
PG3
PF1
EXTAL
P
PG5
PF2 TDI
R
V
DD
PG6
T
A
B
C
D
E
F
G
H
J
K
L
M
1 2 3 4 5 6 7 8 9 10111213141516
PA13
208 MAPBGA Ball Map
(as viewed from top through the package)
N
P
R
T
PB9
PB8
PD10
PD11
PA6
PA3
RESET
PK0
PA7 PA5
PB3
PD13
PD12
PE7
PA4
PA0
PG7
XTAL
TMS
PC6
PD5
PE2
V
SSSYN
PJ2
V
DDE3
PA1
PA2
PJ13
PJ14
PJ15
PJ12 PH5 PH6
PH7
PJ8
PJ9
V
DDE2
PH0
PH2
PG13
PG14
PG9
PG10
PG11
PG0
PJ4PF7 PF11 PJ6
PG2
PF13
PJ3 PJ7
PF10
PG1
PF4
PF9 PJ5
TDO
V
DDSYN
PB12PB15
PB13 PB10PC2
PB2
PC15
V
RCSEL
V
RC
PK9PK7
PK8
PK5
PK6
PK3
PK4
PE3
PE8
PE5
PE4
PJ0
PJ1
PE11PE10 PE14 V
SS
PF3 PE15 PF12PH11PH9 PJ10 PH3 PG15PH15
PF6 V
DDE4
V
DD
PK1 JCOMP V
DD
PG4 PG12
PG8V
DDEMLB
PK2
PE12 PE13TCK PF15
PH10 PF14
PF8 PH12 PH13 PJ11 PH4 PH1PF5 PH14
PH8
PK10
Pin Assignments
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 7
3.2 256-ball MAPBGA Pin Assignments
Figure 4 shows the 256-ball MAPBGA pin assignments.
Figure 4. MPC5668x 256-ball MAPBGA (ful l diagram)
Note: This ballmap is preliminary and
should not be used for board
design.
TEST
V
DD33
V
DDE3
V
SS
V
SS
V
SS
PA9PA11 PA15
PD7 PD8 PE0 PE1 PA1
V
DDENEX
MDO0 V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
V
DDA
PA8
V
SSA
PB14
PB6
PC3
PC7
PC10
V
DD
V
DD
V
RH
V
RL
PA12
PB0
PB5PC0PC4
PC8PC11
PC12
V
SS
PB1PB4
PB7
PC1PC5
PC9
V
SS
PC13PC14
V
SS
PA10 PA14
PB11
V
DDE1
V
SS
PD0
PD1PD2
PD3 PD4
PD6
PD9
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
PE6
V
SS
V
SS
V
SS
V
SS
PE9
PD14
PD15
V
SS
PF0
V
SS
PG3
PF1
EXTAL
PG5
PF2 TDI
V
DD
PG6
PA13
PB9
PB8
PD10
PD11
PA6
PA3
RESET
PK0
PA7 PA5
PB3
PD13
PD12
PE7
PA4
PA0
XTAL
TMS
PC6
PD5
PE2
V
SSSYN
PJ2
PA2
PJ13
PJ14
PJ15
PJ12 PH5 PH6
PH7
PJ8
PJ9
V
DDE2
PH0
PH2
PG13
PG14
PG9
PG10
PG11
PG0
PJ4PF7 PF11 PJ6
PG2
PF13
PJ3 PJ7
PF10
PG1
PF4
PF9 PJ5
TDO
V
DDSYN
PB12PB15
PB13 PB10PC2
PB2
PC15
V
RCSEL
PK9PK7
PK8
PK5
PK6
PK3
PK4
PE3
PE8
PE5
PE4
PJ0
PJ1
PE11PE10 PE14 V
SS
PF3 PE15 PF12PH11PH9 PJ10 PH3 PG15PH15
PF6 V
DDE4
V
DD
PK1 JCOMP V
DD
PG4 PG12
PG8V
DDEMLB
PK2
PE12 PE13TCK PF15
PH10 PF14
PF8 PH12 PH13 PJ11 PH4 PH1PF5 PH14
PH8
PK10
PG7
V
DDENEX
V
DDENEX
V
RCCTL
V
RC
MSEO0
MDO4MDO3
MDO2
MDO1
MDO11MDO10
MDO8
MDO9
MDO7
MDO5MDO6
MSEO1 MCKO EVTI EVTO
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
256 MAPBGA Ball Map
(as viewed from top through the package)
1 2 3 4 5 6 7 8 9 10111213141516
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
A
B
C
D
E
F
G
H
J
K
L
M
1 2 3 4 5 6 7 8 9 10111213141516
N
P
R
T
MPC5668x Microcontroller Data Sheet, Rev. 6
Pin Assignments
Freescale Semiconductor8
3.3 Pin Muxing and Reset States
Table 2 shows the signals properties for each pin on MPC5668x. For all port pins that have an associated SIU_PCRn register
to control pin properties, the supported functions column lists the functi ons associ ated with the programming of the
SIU_PCRn[PA ] bit in the order: gene ral-purpose input/output (GPIO), function 1, function 2, and function 3 (see Figure 5).
When an alternate function is not implemented for a value of SIU_PCR n[PA], a dash is shown in the Description column and
the respective value in the PA bit field is reserved.
Figure 5. Supported Functions Example
Table 2. MPC5668x Signal Properties
Pin
Name1Supported
Functions2
GPIO
(PCR)
Num3PA4Description I/O
Type Volt-
age Pad
Type5
Status Package Pin
Locations
During
Reset6After
Reset7208
BGA 256
BGA
Port A (16)
PA0 PA[0]
AN[0] 000
01
10
11
Port A GPI
ADC Analog Input
I
I
VDDA IHA — D15 D15
PA1 PA[1]
AN[1] 100
01
10
11
Port A GPI
ADC Analog Input
I
I
VDDA IHA — E15 E15
PA2 PA[2]
AN[2] 200
01
10
11
Port A GPI
ADC Analog Input
I
I
VDDA IHA — F16 F16
PA3 PA[3]
AN[3] 300
01
10
11
Port A GPI
ADC Analog Input
I
I
VDDA IHA — F15 F15
PA4 PA[4]
AN[4] 400
01
10
11
Port A GPI
ADC Analog Input
I
I
VDDA IHA — G16 G16
PA5 PA[5]
AN[5] 500
01
10
11
Port A GPI
ADC Analog Input
I
I
VDDA IHA — G15 G15
PA[0]
AN[0] GPIO
Function 1
Functions 2 and 3
not implemented
000
01
10
11
Supported
Functions2
GPIO
(PCR)
Num3 PA4 Description
Port A GPI
ADC Analog Input
Pin Assignments
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 9
PA6 PA[6]
AN[6] 600
01
10
11
Port A GPI
ADC Analog Input
I
I
VDDA IHA — H16 H16
PA7 PA[7]
AN[7] 700
01
10
11
Port A GPI
ADC Analog Input
I
I
VDDA IHA — G14 G14
PA8 PA[8]
AN[8] 800
01
10
11
Port A GPI
ADC Analog Input
I
I
VDDA IHA — F14 F14
PA9 PA[9]
AN[9] 900
01
10
11
Port A GPI
ADC Analog Input
I
I
VDDA IHA — E14 E14
PA10 PA[10]
AN[10] 10 00
01
10
11
Port A GPI
ADC Analog Input
I
I
VDDA IHA — D13 D13
PA11 PA[11]
AN[11] 11 00
01
10
11
Port A GPI
ADC Analog Input
I
I
VDDA IHA — E13 E13
PA12 PA[12]
AN[12] 12 00
01
10
11
Port A GPI
ADC Analog Input
I
I
VDDA IHA — D14 D14
PA13 PA[13]
AN[13] 13 00
01
10
11
Port A GPI
ADC Analog Input
I
I
VDDA IHA — F13 F13
PA14 PA[14]
AN[14]
EXTAL32
14 00
01
10
11
Port A GPI
ADC Analog Input
External 32 kHz Crystal In
I
I
I
VDDA IHA — D16 D16
PA15 PA[15]
AN[15]
XTAL32
15 00
01
10
11
Port A GPI
ADC Analog Input
External 32 kHz Crystal Out
I
I
O
VDDA IHA — E16 E16
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1Supported
Functions2
GPIO
(PCR)
Num3PA4Description I/O
Type Volt-
age Pad
Type5
Status Package Pin
Locations
During
Reset6After
Reset7208
BGA 256
BGA
MPC5668x Microcontroller Data Sheet, Rev. 6
Pin Assignments
Freescale Semiconductor10
Port B (16)
PB0 PB[0]
AN[16]/ANW 16 00
01
10
11
Port B GPIO
ADC Analog Input/Mux In
I/O
I
VDDE1 SHA — B14 B14
PB1 PB[1]
AN[17]/ANX 17 00
01
10
11
Port B GPIO
ADC Analog Input/Mux In
I/O
I
VDDE1 SHA — C14 C14
PB2 PB[2]
AN[18]/ANY 18 00
01
10
11
Port B GPIO
ADC Analog Input/Mux In
I/O
I
VDDE1 SHA — B13 B13
PB3 PB[3]
AN[19]/ANZ 19 00
01
10
11
Port B GPIO
ADC Analog Input/Mux In
I/O
I
VDDE1 SHA — C13 C13
PB4 PB[4]
AN[20] 20 00
01
10
11
Port B GPIO
ADC Analog Input
I/O
I
VDDE1 SHA — C12 C12
PB5 PB[5]
AN[21] 21 00
01
10
11
Port B GPIO
ADC Analog Input
I/O
I
VDDE1 SHA — D12 D12
PB6 PB[6]
AN[22] 22 00
01
10
11
Port B GPIO
ADC Analog Input
I/O
I
VDDE1 SHA — C11 C11
PB7 PB[7]
AN[23] 23 00
01
10
11
Port B GPIO
ADC Analog Input
I/O
I
VDDE1 SHA — D11 D11
PB8 PB[8]
AN[24]
PCS_A[2]
24 00
01
10
11
Port B GPIO
ADC Analog Input
DSPI_A Peripheral Chip Select
I/O
I
O
VDDE1 SHA — A10 A10
PB9 PB[9]
AN[25]
PCS_A[3]
25 00
01
10
11
Port B GPIO
ADC Analog Input
DSPI_A Peripheral Chip Select
I/O
I
O
VDDE1 SHA — B12 B12
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1Supported
Functions2
GPIO
(PCR)
Num3PA4Description I/O
Type Volt-
age Pad
Type5
Status Package Pin
Locations
During
Reset6After
Reset7208
BGA 256
BGA
Pin Assignments
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 11
PB10 PB[10]
AN[26]
PCS_B[4]
26 00
01
10
11
Port B GPIO
ADC Analog Input
DSPI_B Peripheral Chip Select
I/O
I
O
VDDE1 SHA — A9 A9
PB11 PB[11]
AN[27]
PCS_B[5]
27 00
01
10
11
Port B GPIO
ADC Analog Input
DSPI_B Peripheral Chip Select
I/O
I
O
VDDE1 SHA — B9 B9
PB12 PB[12]
AN[28]
PCS_C[1]
28 00
01
10
11
Port B GPIO
ADC Analog Input
DSPI_C Peripheral Chip Select
I/O
I
O
VDDE1 SHA — C10 C10
PB13 PB[13]
AN[29]
PCS_C[2]
29 00
01
10
11
Port B GPIO
ADC Analog Input
DSPI_C Peripheral Chip Select
I/O
I
O
VDDE1 SHA A8 A8
PB14 PB[14]
AN[30]
PCS_D[3]
30 00
01
10
11
Port B GPIO
ADC Analog Input
DSPI_D Peripheral Chip Select
I/O
I
O
VDDE1 SHA — B8 B8
PB15 PB[15]
AN[31]
PCS_D[4]
31 00
01
10
11
Port B GPIO
ADC Analog Input
DSPI_D Peripheral Chip Select
I/O
I
O
VDDE1 SHA — C9 C9
Port C (16)
PC0 PC[0]
AN[32] 32 00
01
10
11
Port C GPIO
ADC Analog Input
I/O
I
VDDE1 SHA — D9 D9
PC1 PC[1]
AN[33] 33 00
01
10
11
Port C GPIO
ADC Analog Input
I/O
I
VDDE1 SHA — C8 C8
PC2 PC[2]
AN[34]
EVTI
34 00
01
10
11
Port C GPIO
ADC Analog Input
Nexus Event In
I/O
I
I
VDDE1 SHA — A7 A7
PC3 PC[3]
AN[35]
EVTO
35 00
01
10
11
Port C GPIO
ADC Analog Input
Nexus Event Out
I/O
I
O
VDDE1 SHA — B7 B7
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1Supported
Functions2
GPIO
(PCR)
Num3PA4Description I/O
Type Volt-
age Pad
Type5
Status Package Pin
Locations
During
Reset6After
Reset7208
BGA 256
BGA
MPC5668x Microcontroller Data Sheet, Rev. 6
Pin Assignments
Freescale Semiconductor12
PC4 PC[4]
AN[36] 36 00
01
10
11
Port C GPIO
ADC Analog Input
I/O
I
VDDE1 SHA — D8 D8
PC5 PC[5]
AN[37]
Z6NMI
37 00
01
10
11
Port C GPIO
ADC Analog Input
Z6 Core Non-Maskab l e Interrupt
I/O
I
I
VDDE1 SHA — C6 C6
PC6 PC[6]
AN[38]
Z0NMI
38 00
01
10
11
Port C GPIO
ADC Analog Input
Z0 Core Non-Maskab l e Interrupt
I/O
I
I
VDDE1 SHA — C7 C7
PC7 PC[7]
AN[39]
FR_DBG3
39 00
01
10
11
Port C GPIO
ADC Analog Input
Fle xRay Debug
I/O
I
O
VDDE1 SHA — A6 A6
PC8 PC[8]
AN[40]
FR_DBG2
40 00
01
10
11
Port C GPIO
ADC Analog Input
Fle xRay Debug
I/O
I
O
VDDE1 SHA — B6 B6
PC9 PC[9]
AN[41]
FR_DBG1
41 00
01
10
11
Port C GPIO
ADC Analog Input
Fle xRay Debug
I/O
I
O
VDDE1 SHA — A5 A5
PC10 PC[10]
AN[42]
FR_DBG0
42 00
01
10
11
Port C GPIO
ADC Analog Input
Fle xRay Debug
I/O
I
O
VDDE1 SHA — B5 B5
PC11 PC[11]
AN[43]
SCL_C
43 00
01
10
11
Port C GPIO
ADC Analog Input
I2C_C Serial Clock
I/O
I
I/O
VDDE1 SHA — B4 B4
PC12 PC[12]
AN[44]
SDA_C
44 00
01
10
11
Port C GPIO
ADC Analog Input
I2C_C Serial Data
I/O
I
I/O
VDDE1 SHA — A4 A4
PC13 PC[13]
AN[45]
MA[0]
45 00
01
10
11
Port C GPIO
ADC Analog Input
ADC Ext. Mux Address Select
I/O
I
O
VDDE1 SHA — C5 C5
PC14 PC[14]
AN[46]
MA[1]
46 00
01
10
11
Port C GPIO
ADC Analog Input
ADC Ext. Mux Address Select
I/O
I
O
VDDE1 SHA — C4 C4
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1Supported
Functions2
GPIO
(PCR)
Num3PA4Description I/O
Type Volt-
age Pad
Type5
Status Package Pin
Locations
During
Reset6After
Reset7208
BGA 256
BGA
Pin Assignments
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 13
PC15 PC[15]
AN[47]
MA[2]
47 00
01
10
11
Port C GPIO
ADC Analog Input
ADC Ext. Mux Address Select
I/O
I
O
VDDE1 SHA — D5 D5
Port D (16)
PD0 PD[0]
CNTX_A 48 00
01
10
11
Port D GPIO
FlexCAN_A Transmit
I/O
O
VDDE2 SH A2 A2
PD1 PD[1]
CNRX_A 49 00
01
10
11
Port D GPIO
FlexCAN_A Receive
I/O
I
VDDE2 SH B2 B2
PD2 PD[2]
CNTX_B 50 00
01
10
11
Port D GPIO
FlexCAN_B Transmit
I/O
O
VDDE2 SH B1 B1
PD3 PD[3]
CNRX_B 51 00
01
10
11
Port D GPIO
FlexCAN_B Receive
I/O
I
VDDE2 SH C1 C1
PD4 PD[4]
CNTX_C 52 00
01
10
11
Port D GPIO
FlexCAN_C Transmit
I/O
O
VDDE2 SH C2 C2
PD5 PD[5]
CNRX_C 53 00
01
10
11
Port D GPIO
Fle xCAN_C Receive
I/O
I
VDDE2 SH D1 D1
PD6 PD[6]
CNTX_D
TXD_K
SCL_B
54 00
01
10
11
Port D GPIO
FlexCAN_D Transmit
SCI_K Transmit
I2C_B Serial Clock
I/O
O
O
I/O
VDDE2 SH D2 D2
PD7 PD[7]
CNRX_D
RXD_K
SDA_B
55 00
01
10
11
Port D GPIO
Fle xCAN_D Receive
SCI_K Receive
I2C_B Serial Data
I/O
I
I
I/O
VDDE2 SH E1 E1
PD8 PD[8]
CNTX_E
TXD_L
SCL_C
56 00
01
10
11
Port D GPIO
FlexCAN_E Transmit
SCI_L Transmit
I2C_C Serial Clock
I/O
O
O
I/O
VDDE2 SH E2 E2
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1Supported
Functions2
GPIO
(PCR)
Num3PA4Description I/O
Type Volt-
age Pad
Type5
Status Package Pin
Locations
During
Reset6After
Reset7208
BGA 256
BGA
MPC5668x Microcontroller Data Sheet, Rev. 6
Pin Assignments
Freescale Semiconductor14
PD9 PD[9]
CNRX_E
RXD_L
SDA_C
57 00
01
10
11
Port D GPIO
FlexCAN_E Receive
SCI_L Receive
I2C_C Serial Data
I/O
I
I
I/O
VDDE2 SH F1 F1
PD10 PD[10]
CNTX_F
TXD_M
SCL_D
58 00
01
10
11
Port D GPIO
FlexCAN_F Transmit
SCI_M Transmit
I2C_D Serial Clock
I/O
O
O
I/O
VDDE2 SH F2 F2
PD11 PD[11]
CNRX_F
RXD_M
SDA_D
59 00
01
10
11
Port D GPIO
FlexCAN_F Receive
SCI_M Receive
I2C_D Serial Data
I/O
I
I
I/O
VDDE2 SH G1 G1
PD12 PD[12]
TXD_A 60 00
01
10
11
Port D GPIO
eSCI_A Transmit
I/O
O
VDDE2 SH G2 G2
PD13 PD[13]
RXD_A 61 00
01
10
11
Port D GPIO
eSCI_A Receive
I/O
I
VDDE2 SH H1 H1
PD14 PD[14]
TXD_B 62 00
01
10
11
Port D GPIO
eSCI_B Transmit
I/O
O
VDDE2 SH C3 C3
PD15 PD[15]
RXD_B 63 00
01
10
11
Port D GPIO
eSCI_B Receive
I/O
I
VDDE2 SH D3 D3
Port E (16)
PE0 PE[0]
TXD_C
eMIOS[31]
64 00
01
10
11
Port E GPIO
eSCI_C Transmit
eMIOS Channel
I/O
O
I/O
VDDE2 SH E3 E3
PE1 PE[1]
RXD_C
eMIOS[30]
65 00
01
10
11
Port E GPIO
eSCI_C Recei ve
eMIOS Channel
I/O
I
I/O
VDDE2 SH E4 E4
PE2 PE[2]
TXD_D
eMIOS[29]
66 00
01
10
11
Port E GPIO
eSCI_D Transmit
eMIOS Channel
I/O
O
I/O
VDDE2 SH F4 F4
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1Supported
Functions2
GPIO
(PCR)
Num3PA4Description I/O
Type Volt-
age Pad
Type5
Status Package Pin
Locations
During
Reset6After
Reset7208
BGA 256
BGA
Pin Assignments
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 15
PE3 PE[3]
RXD_D
eMIOS[28]
67 00
01
10
11
Port E GPIO
eSCI_D Recei ve
eMIOS Channel
I/O
I
I/O
VDDE2 SH F3 F3
PE4 PE[4]
TXD_E
eMIOS[27]
68 00
01
10
11
Port E GPIO
eSCI_E Transmit
eMIOS Channel
I/O
O
I/O
VDDE2 SH G3 G3
PE5 PE[5]
RXD_E
eMIOS[26]
69 00
01
10
11
Port E GPIO
eSCI_E Receive
eMIOS Channel
I/O
I
I/O
VDDE2 SH H3 H3
PE6 PE[6]
TXD_F
eMIOS[25]
70 00
01
10
11
Port E GPIO
eSCI_F Transmit
eMIOS Channel
I/O
O
I/O
VDDE2 SH M2 M2
PE7 PE[7]
RXD_F
eMIOS[24]
71 00
01
10
11
Port E GPIO
eSCI_F Receive
eMIOS Channel
I/O
I
I/O
VDDE2 SH L2 L2
PE8 PE[8]
TXD_G
PCS_A[1]
72 00
01
10
11
Port E GPIO
eSCI_G Transmit
DSPI_A Peripheral Chip Select
I/O
O
O
VDDE2 SH J4 J4
PE9 PE[9]
RXD_G
PCS_A[4]
73 00
01
10
11
Port E GPIO
eSCI_G Receive
DSPI_A Peripheral Chip Select
I/O
I
O
VDDE2 SH M4 M4
PE10 PE[10]
TXD_H
PCS_B[3]
74 00
01
10
11
Port E GPIO
eSCI_H Transmit
DSPI_B Peripheral Chip Select
I/O
O
O
VDDE2 SH N3 N3
PE11 PE[11]
RXD_H
PCS_B[2]
75 00
01
10
11
Port E GPIO
eSCI_H Recei ve
DSPI_B Peripheral Chip Select
I/O
I
O
VDDE2 SH N4 N4
PE12 PE[12]
TXD_J
PCS_C[5]
76 00
01
10
11
Port E GPIO
eSCI_J Transmit
DSPI_C Peripheral Chip Select
I/O
O
O
VDDE2 SH P4 P4
PE13 PE[13]
RXD_J
PCS_C[3]
77 00
01
10
11
Port E GPIO
eSCI_J Receive
DSPI_C Peripheral Chip Select
I/O
I
O
VDDE2 SH P5 P5
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1Supported
Functions2
GPIO
(PCR)
Num3PA4Description I/O
Type Volt-
age Pad
Type5
Status Package Pin
Locations
During
Reset6After
Reset7208
BGA 256
BGA
MPC5668x Microcontroller Data Sheet, Rev. 6
Pin Assignments
Freescale Semiconductor16
PE14 PE[14]
SCL_A
PCS_D[2]
78 00
01
10
11
Port E GPIO
I2C_A Serial Clock
DSPI_D Peripheral Chip Select
I/O
I/O
O
VDDE2 SH N7 N7
PE15 PE[15]
SDA_A
PCS_D[5]
79 00
01
10
11
Port E GPIO
I2C_A Serial Data
DSPI_D Peripheral Chip Select
I/O
I/O
O
VDDE2 SH N6 N6
Port F (16)
PF0 PF[0]
SCK_A 80 00
01
10
11
Port F GPIO
DSPI_A Serial Clock
I/O
I/O
VDDE2 MH H2 H2
PF1 PF[1]
SOUT_A 81 00
01
10
11
Port F GPIO
DSPI_A Serial
Data Out
I/O
O
VDDE2 MH J1 J1
PF2 PF[2]
SIN_A 82 00
01
10
11
Port F GPIO
DSPI_A Serial
Data In
I/O
I
VDDE2 SH J2 J2
PF3 PF[3]
PCS_A[0]
PCS_B[5]
PCS_C[4]
83 00
01
10
11
Port F GPIO
DSPI_A Peripheral Chip Select
DSPI_B Peripheral Chip Select
DSPI_C Peripheral Chip Select
I/O
I/O
O
O
VDDE2 SH N2 N2
PF4 PF[4]
SCK_B
PCS_A[1]
PCS_C[2]
84 00
01
10
11
Port F GPIO
DSPI_B Serial Clock
DSPI_A Peripheral Chip Select
DSPI_C Peripheral Chip Select
I/O
I/O
O
O
VDDE2 MH M1 M1
PF5 PF[5]
SOUT_B
PCS_A[2]
PCS_C[3]
85 00
01
10
11
Port F GPIO
DSPI_B Serial
Data Out
DSPI_A Peripheral Chip Select
DSPI_C Peripheral Chip Select
I/O
O
O
O
VDDE2 MH P2 P2
PF6 PF[6]
SIN_B
PCS_A[3]
PCS_C[5]
86 00
01
10
11
Port F GPIO
DSPI_B Serial
Data In
DSPI_A Peripheral Chip Select
DSPI_C Peripheral Chip Select
I/O
I
O
O
VDDE2 SH N1 N1
PF7 PF[7]
PCS_B[0]
PCS_C[5]
PCS_D[4]
87 00
01
10
11
Port F GPIO
DSPI_B Peripheral Chip Select
DSPI_C Peripheral Chip Select
DSPI_D Peripheral Chip Select
I/O
I/O
O
O
VDDE2 SH R2 R2
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1Supported
Functions2
GPIO
(PCR)
Num3PA4Description I/O
Type Volt-
age Pad
Type5
Status Package Pin
Locations
During
Reset6After
Reset7208
BGA 256
BGA
Pin Assignments
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 17
PF8 PF[8]
SCK_C 88 00
01
10
11
Port F GPIO
DSPI_C Serial Clock
I/O
I/O
VDDE2 MH P1 P1
PF9 PF[9]
SOUT_C 89 00
01
10
11
Port F GPIO
DSPI_C Serial Data Out
I/O
O
VDDE2 MH T2 T2
PF10 PF[10]
SIN_C 90 00
01
10
11
Port F GPIO
DSPI_C Serial Data In
I/O
I
VDDE2 SH R1 R1
PF11 PF[11]
PCS_C[0]
PCS_D[5]
PCS_A[4]
91 00
01
10
11
Port F GPIO
DSPI_C Peripheral Chip Select
DSPI_D Peripheral Chip Select
DSPI_A Peripheral Chip Select
I/O
I/O
O
O
VDDE2 SH R3 R3
PF12 PF[12]
SCK_D 92 00
01
10
11
Port F GPIO
DSPI_D Serial Clock
I/O
I/O
VDDE3 MH N14 N14
PF13 PF[13]
SOUT_D 93 00
01
10
11
Port F GPIO
DSPI_D Serial Data Out
I/O
O
VDDE3 MH M14 M14
PF14 PF[14]
SIN_D 94 00
01
10
11
Port F GPIO
DSPI_D Serial Data In
I/O
I
VDDE3 SH P14 P14
PF15 PF[15]
PCS_D[0]
PCS_A[5]
PCS_B[4]
95 00
01
10
11
Port F GPIO
DSPI_D Peripheral Chip Select
DSPI_A Peripheral Chip Select
DSPI_B Peripheral Chip Select
I/O
I/O
O
O
VDDE3 SH P13 P13
Port G (16)
PG0 PG[0]
PCS_A[4]
PCS_B[3]
AN[48]
96 00
01
10
11
Port G GPIO
DSPI_A Peripheral Chip Select
DSPI_B Peripheral Chip Select
ADC Analog Input
I/O
O
O
I
VDDE2 SHA — B3 B3
PG1 PG[1]
PCS_A[5]
PCS_B[4]
AN[49]
97 00
01
10
11
Port G GPIO
DSPI_A Peripheral Chip Select
DSPI_B Peripheral Chip Select
ADC Analog Input
I/O
O
O
I
VDDE2 SHA — A3 A3
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1Supported
Functions2
GPIO
(PCR)
Num3PA4Description I/O
Type Volt-
age Pad
Type5
Status Package Pin
Locations
During
Reset6After
Reset7208
BGA 256
BGA
MPC5668x Microcontroller Data Sheet, Rev. 6
Pin Assignments
Freescale Semiconductor18
PG2 PG[2]
PCS_D[1]
SCL_C
AN[50]
98 00
01
10
11
Port G GPIO
DSPI_D Peripheral Chip Select
I2C_C Serial Clock
ADC Analog Input
I/O
O
I/O
I
VDDE3 SHA — H14 H14
PG3 PG[3]
PCS_D[2]
SDA_C
AN[51]
99 00
01
10
11
Port G GPIO
DSPI_D Peripheral Chip Select
I2C_C Serial Data
ADC Analog Input
I/O
O
I/O
I
VDDE3 SHA — J14 J14
PG4 PG[4]
PCS_D[3]
SCL_B
AN[52]
100 00
01
10
11
Port G GPIO
DSPI_D Peripheral Chip Select
I2C_B Serial Clock
ADC Analog Input
I/O
O
I/O
I
VDDE3 SHA — K14 K14
PG5 PG[5]
PCS_D[4]
SDA_B
AN[53]
101 00
01
10
11
Port G GPIO
DSPI_D Peripheral Chip Select
I2C_B Serial Data
ADC Analog Input
I/O
O
I/O
I
VDDE3 SHA — L14 L14
PG6 PG[6]
PCS_C[1]
FEC_MDC
AN[54]
102 00
01
10
11
Port G GPIO
DSPI_C Peripheral Chip Select
Ethernet Mgmt. Data Clock
ADC Analog Input
I/O
O
O
I
VDDE3 MHA — H15 H15
PG7 PG[7]
PCS_C[2]
FEC_MDIO
AN[55]
103 00
01
10
11
Port G GPIO
DSPI_C Peripheral Chip Select
Ethernet Mgmt. Data I/O
ADC Analog Input
I/O
O
I/O
I
VDDE3 MHA — J15 J15
PG8 PG[8]
eMIOS[7]
FEC_TX_CLK
AN[56]
104 00
01
10
11
Port G GPIO
eMIOS Channel
Ethernet Transmit Clock
ADC Analog Input
I/O
I/O
I
I
VDDE3 SHA — K15 K15
PG9 PG[9]
eMIOS[6]
FEC_CRS
AN[57]
105 00
01
10
11
Port G GPIO
eMIOS Channel
Ethernet Carrier Sense
ADC Analog Input
I/O
I/O
I
I
VDDE3 SHA — L15 L15
PG10 PG[10]
eMIOS[5]
FEC_TX_ER
AN[58]
106 00
01
10
11
Port G GPIO
eMIOS Channel
Ethernet Transmit Error
ADC Analog Input
I/O
I/O
O
I
VDDE3 MHA — M15 M15
PG11 PG[11]
eMIOS[4]
FEC_RX_CLK
AN[59]
107 00
01
10
11
Port G GPIO
eMIOS Channel
Ethernet Receive Clock
ADC Analog Input
I/O
I/O
I
I
VDDE3 SHA J16 J16
PG12 PG[12]
eMIOS[3]
FEC_TXD[0]
AN[60]
108 00
01
10
11
Port G GPIO
eMIOS Channel
Etherne t Transmit Data
ADC Analog Input
I/O
I/O
O
I
VDDE3 MHA — K16 K16
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1Supported
Functions2
GPIO
(PCR)
Num3PA4Description I/O
Type Volt-
age Pad
Type5
Status Package Pin
Locations
During
Reset6After
Reset7208
BGA 256
BGA
Pin Assignments
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 19
PG13 PG[13]
eMIOS[2]
FEC_TXD[1]
AN[61]
109 00
01
10
11
Port G GPIO
eMIOS Channel
Etherne t Transmit Data
ADC Analog Input
I/O
I/O
O
I
VDDE3 MHA — L16 L16
PG14 PG[14]
eMIOS[1]
FEC_TXD[2]
AN[62]
110 00
01
10
11
Port G GPIO
eMIOS Channel
Etherne t Transmit Data
ADC Analog Input
I/O
I/O
O
I
VDDE3 MHA — M16 M16
PG15 PG[15]
eMIOS[0]
FEC_TXD[3]
AN[63]
111 00
01
10
11
Port G GPIO
eMIOS Channel
Etherne t Transmit Data
ADC Analog Input
I/O
I/O
O
I
VDDE3 MHA — N16 N16
Port H (16)
PH0 PH[0]
eMIOS[31]
FEC_COL
112 00
01
10
11
Port H GPIO
eMIOS Channel
Ethernet Collision
I/O
I/O
I
VDDE3 SH T14 T14
PH1 PH[1]
eMIOS[30]
FEC_RX_DV
113 00
01
10
11
Port H GPIO
eMIOS Channel
Ethernet Receive Data Valid
I/O
I/O
I
VDDE3 SH P16 P16
PH2 PH[2]
eMIOS[29]
FEC_TX_EN
114 00
01
10
11
Port H GPIO
eMIOS Channel
Ethernet Transmit Enable
I/O
I/O
O
VDDE3 MH R16 R16
PH3 PH[3]
eMIOS[28]
FEC_RX_ER
115 00
01
10
11
Port H GPIO
eMIOS Channel
Ethernet Receive Error
I/O
I/O
I
VDDE3 SH N15 N15
PH4 PH[4]
eMIOS[27]
FEC_RXD[0]
116 00
01
10
11
Port H GPIO
eMIOS Channel
Etherne t Rece ive Data
I/O
I/O
I
VDDE3 SH P15 P15
PH5 PH[5]
eMIOS[26]
FEC_RXD[1]
117 00
01
10
11
Port H GPIO
eMIOS Channel
Etherne t Rece ive Data
I/O
I/O
I
VDDE3 SH R14 R14
PH6 PH[6]
eMIOS[25]
FEC_RXD[2]
118 00
01
10
11
Port H GPIO
eMIOS Channel
Etherne t Rece ive Data
I/O
I/O
I
VDDE3 SH R15 R15
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1Supported
Functions2
GPIO
(PCR)
Num3PA4Description I/O
Type Volt-
age Pad
Type5
Status Package Pin
Locations
During
Reset6After
Reset7208
BGA 256
BGA
MPC5668x Microcontroller Data Sheet, Rev. 6
Pin Assignments
Freescale Semiconductor20
PH7 PH[7]
eMIOS[24]
FEC_RXD[3]
119 00
01
10
11
Port H GPIO
eMIOS Channel
Etherne t Rece ive Data
I/O
I/O
I
VDDE3 SH T15 T15
PH8 PH[8]
eMIOS[23] 120 00
01
10
11
Port H GPIO
eMIOS Channel
I/O
I/O
VDDE4 SH P7 P7
PH9 PH[9]
eMIOS[22] 121 00
01
10
11
Port H GPIO
eMIOS Channel
I/O
I/O
VDDE4 SH N8 N8
PH10 PH[10]
eMIOS[21] 122 00
01
10
11
Port H GPIO
eMIOS Channel
I/O
I/O
VDDE4 SH P8 P8
PH11 PH[11]
eMIOS[20] 123 00
01
10
11
Port H GPIO
eMIOS Channel
I/O
I/O
VDDE4 SH N9 N9
PH12 PH[12]
eMIOS[19] 124 00
01
10
11
Port H GPIO
eMIOS Channel
I/O
I/O
VDDE4 SH P9 P9
PH13 PH[13]
eMIOS[18] 125 00
01
10
11
Port H GPIO
eMIOS Channel
I/O
I/O
VDDE4 SH P10 P10
PH14 PH[14]
eMIOS[17] 126 00
01
10
11
Port H GPIO
eMIOS Channel
I/O
I/O
VDDE4 SH P11 P11
PH15 PH[15]
eMIOS[16] 127 00
01
10
11
Port H GPIO
eMIOS Channel
I/O
I/O
VDDE4 SH N11 N11
Port J (16)
PJ0 PJ[0]
eMIOS[15]
PCS_A[4]
128 00
01
10
11
Port J GPIO
eMIOS Channel
DSPI_A Peripheral Chip Select
I/O
I/O
O
VDDE4 SH R7 R7
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1Supported
Functions2
GPIO
(PCR)
Num3PA4Description I/O
Type Volt-
age Pad
Type5
Status Package Pin
Locations
During
Reset6After
Reset7208
BGA 256
BGA
Pin Assignments
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 21
PJ1 PJ[1]
eMIOS[14]
PCS_A[5]
129 00
01
10
11
Port J GPIO
eMIOS Channel
DSPI_A Peripheral Chip Select
I/O
I/O
O
VDDE4 SH T7 T7
PJ2 PJ[2]
eMIOS[13]
PCS_B[1]
130 00
01
10
11
Port J GPIO
eMIOS Channel
DSPI_B Peripheral Chip Select
I/O
I/O
O
VDDE4 SH R8 R8
PJ3 PJ[3]
eMIOS[12]
PCS_B[2]
131 00
01
10
11
Port J GPIO
eMIOS Channel
DSPI_B Peripheral Chip Select
I/O
I/O
O
VDDE4 SH T8 T8
PJ4 PJ[4]
eMIOS[11]
PCS_C[3]
132 00
01
10
11
Port J GPIO
eMIOS Channel
DSPI_C Peripheral Chip Select
I/O
I/O
O
VDDE4 SH R9 R9
PJ5 PJ[5]
eMIOS[10]
PCS_C[4]
133 00
01
10
11
Port J GPIO
eMIOS Channel
DSPI_C Peripheral Chip Select
I/O
I/O
O
VDDE4 SH T9 T9
PJ6 PJ[6]
eMIOS[09]
PCS_D[5]
134 00
01
10
11
Port J GPIO
eMIOS Channel
DSPI_D Peripheral Chip Select
I/O
I/O
O
VDDE4 SH R10 R10
PJ7 PJ[7]
eMIOS[08]
PCS_D[1]
135 00
01
10
11
Port J GPIO
eMIOS Channel
DSPI_D Peripheral Chip Select
I/O
I/O
O
VDDE4 SH T10 T10
PJ8 PJ[8]
eMIOS[07] 136 00
01
10
11
Port J GPIO
eMIOS Channel
I/O
I/O
VDDE4 SH T11 T11
PJ9 PJ[9]
eMIOS[06] 137 00
01
10
11
Port J GPIO
eMIOS Channel
I/O
I/O
VDDE4 SH R11 R11
PJ10 PJ[10]
eMIOS[05] 138 00
01
10
11
Port J GPIO
eMIOS Channel
I/O
I/O
VDDE4 SH N12 N12
PJ11 PJ[11]
eMIOS[04] 139 00
01
10
11
Port J GPIO
eMIOS Channel
I/O
I/O
VDDE4 SH P12 P12
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1Supported
Functions2
GPIO
(PCR)
Num3PA4Description I/O
Type Volt-
age Pad
Type5
Status Package Pin
Locations
During
Reset6After
Reset7208
BGA 256
BGA
MPC5668x Microcontroller Data Sheet, Rev. 6
Pin Assignments
Freescale Semiconductor22
PJ12 PJ[12]
eMIOS[03] 140 00
01
10
11
Port J GPIO
eMIOS Channel
I/O
I/O
VDDE4 SH R12 R12
PJ13 PJ[13]
eMIOS[02] 141 00
01
10
11
Port J GPIO
eMIOS Channel
I/O
I/O
VDDE4 SH T12 T12
PJ14 PJ[14]
eMIOS[01] 142 00
01
10
11
Port J GPIO
eMIOS Channel
I/O
I/O
VDDE4 SH R13 R13
PJ15 PJ[15]
eMIOS[00] 143 00
01
10
11
Port J GPIO
eMIOS Channel
I/O
I/O
VDDE4 SH T13 T13
Port K (11)
PK0 PK[0]
MLBCLK
SCK_B
CLKOUT
144 00
01
10
11
Port K GPIO
Media Local Bus Clock
DSPI_B Serial Clock
CLKOUT (Test Only)
I/O
I
I/O
O
V
DDEMLB
F— L1L1
PK1 PK[1]
MLBSIG
SOUT_B
PCS_D[4]
145 00
01
10
11
Port K GPIO
Media Local Bus Signal
DSPI_B Serial Data Out
DSPI_D Peripheral Chip Select
I/O
I/O
O
O
V
DDEMLB
F— K1K1
PK2 PK[2]
MLBDAT
SIN_B
PCS_D[5]
146 00
01
10
11
Port K GPIO
Media Local Bus Data
DSPI_B Serial Data In
DSPI_D Peripheral Chip Select
I/O
I/O
I
O
V
DDEMLB
F— K2K2
PK3 PK[3]
FR_A_RX
MA[0]
PCS_C[1]
147 00
01
10
11
Port K GPIO
FlexRay A Receive Data
ADC Ext. Mux Address Select
DSPI_C Peripheral Chip Select
I/O
I
O
O
VDDE2 SH T3 T3
PK4 PK[4]
FR_A_TX
MA[1]
PCS_C[2]
148 00
01
10
11
Port K GPIO
FlexRay A Transmit Data
ADC Ext. Mux Address Select
DSPI_C Peripheral Chip Select
I/O
O
O
O
VDDE2 MH R4 R4
PK5 PK[5]
FR_A_TX_EN
MA[2]
PCS_C[3]
149 00
01
10
11
Port K GPIO
FlexRay A Transmit Enable
ADC Ext. Mux Address Select
DSPI_C Peripheral Chip Select
I/O
O
O
O
VDDE2 MH T4 T4
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1Supported
Functions2
GPIO
(PCR)
Num3PA4Description I/O
Type Volt-
age Pad
Type5
Status Package Pin
Locations
During
Reset6After
Reset7208
BGA 256
BGA
Pin Assignments
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 23
PK6 PK[6]
FR_B_RX
PCS_B[1]
PCS_C[4]
150 00
01
10
11
Port K GPIO
FlexRay B Receive Data
DSPI_B Peripheral Chip Select
DSPI_C Peripheral Chip Select
I/O
I
O
O
VDDE2 SH R5 R5
PK7 PK[7]
FR_B_TX
PCS_B[2]
PCS_C[5]
151 00
01
10
11
Port K GPIO
FlexRay B Transmit Data
DSPI_B Peripheral Chip Select
DSPI_C Peripheral Chip Select
I/O
O
O
O
VDDE2 MH T5 T5
PK8 PK[8]
FR_B_TX_EN
PCS_B[3]
PCS_A[1]
152 00
01
10
11
Port K GPIO
FlexRay B Transmit Enable
DSPI_B Peripheral Chip Select
DSPI_A Peripheral Chip Select
I/O
O
O
O
VDDE2 MH R6 R6
PK9 PK[9]
CLKOUT
PCS_D[1]
PCS_A[2]
BOOTCFG
153 00
01
10
11
Port K GPIO
CLKOUT (User mode)
DSPI_D Peripheral Chip Select
DSPI_A Peripheral Chip Select
Boot Configuration
I/O
O
O
O
I
VDDE2 MH BOOT
CFG
(Pull-
down)
GPIO T6 T6
PK10 PK[10]
PCS_B[5]
PCS_D[2]
PCS_A[3]
154 00
01
10
11
Port K GPIO
DSPI_B Peripheral Chip Select
DSPI_D Peripheral Chip Select
DSPI_A Peripheral Chip Select
I/O
O
O
O
VDDE2 SH P6 P6
Nexus Pins (17)
EVTI EVTI Nexus Event In I
V
DDENEX
F— M11
EVTO EVTO ——Nexus Event Out O
V
DDENEX
F— M12
MSEO0 MSEO[0] Nexus Message Start/End Out O
V
DDENEX
F— M9
MSEO1 MSEO[1] Nexus Message Start/End Out O
V
DDENEX
F— M8
MCKO MCKO Nexus Message Clock Out O
V
DDENEX
F— M10
MDO0 MDO[0] Nexus Message Data Out O
V
DDENEX
F— E5
MDO1 MDO[1] Nexus Message Data Out O
V
DDENEX
F— F5
MDO2 MDO[2] Nexus Message Data Out O
V
DDENEX
F— G5
MDO3 MDO[3] Nexus Message Data Out O
V
DDENEX
F— H5
MDO4 MDO[4] Nexus Message Data Out O
V
DDENEX
F— H6
MDO5 MDO[5] Nexus Message Data Out O
V
DDENEX
F— J6
MDO6 MDO[6] Nexus Message Data Out O
V
DDENEX
F— J5
MDO7 MDO[7] Nexus Message Data Out O
V
DDENEX
F— K5
MDO8 MDO[8] Nexus Message Data Out O
V
DDENEX
F— L5
MDO9 MDO[9] Nexus Message Data Out O
V
DDENEX
F— M5
MDO10 MDO[10] Nexus Message Data Out O
V
DDENEX
F— M6
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1Supported
Functions2
GPIO
(PCR)
Num3PA4Description I/O
Type Volt-
age Pad
Type5
Status Package Pin
Locations
During
Reset6After
Reset7208
BGA 256
BGA
MPC5668x Microcontroller Data Sheet, Rev. 6
Pin Assignments
Freescale Semiconductor24
MDO11 MDO[11] Nexus Message Data Out O
V
DDENEX
F— M7
Miscellaneous Pins (9)
EXTAL EXTAL
EXTCLK Main Crystal Oscillator Input
External Clock Input I
I
V
DDSYN
A EXTAL A14 A14
XTAL XTAL Main Cr ystal Oscillator Output O
V
DDSYN
AXTALA13A13
TDI TDI JTAG Test Data Input I VDDE2 SH TDI (Pull Up) J3 J3
TDO TDO JTAG Test Data Output O VDDE2 MH TDO (Pull Up8)M3 M3
TMS TMS JTAG Test Mode Select Input I VDDE2 MH TMS (Pull Up) L3 L3
TCK TCK JTAG Test Clock Input I VDDE2 SH TCK (Pull Down) P3 P3
JCOMP JCOMP JTAG Compliancy I VDDE2 SH
JCOMP (Pull Down)
K3 K3
TEST TEST Test Mode Select I VDDE3 IH TEST9M13 M13
RESET RESET External Reset I/O VDDE1 MH RESET (Pull Up) A11 A11
1The primary signal name is used as the pin label on the BGA map for identification purposes.
2Each line in the Signal Name column corresponds to a separate signal function on the pin. F or all device I/O pins, the primary,
alternate, or GPIO signal functions are designated in the PA field of the System Integration Unit (SIU) PCR registers except
where explicitly noted.
3The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number.
4The PA bitfield in the SIU_PCRn register selects the signal function for the pin. A dash in the Description field of this table
indicates that this value for PC is reserved on this pin, and should not be used.
5The pad type is indicated by one or more of the f ollowing abbre viations: A–analog, F—fast speed, H–high voltage , I—input-only,
M–medium speed, S–slow speed. For example, pad type SH designates a slow high-voltage pad.
6The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high
impedance. The terminology used in this column is: O – output, I – input, Up – weak pull up enabled, Down – weak pulldown
enabled, Lo w – output driven lo w, High – output driven high. A dash on the left side of the slash denotes that both the input and
output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on
the pin. The signal name to the left or r ight of the slash indicates the pin is enabled.
7The Function After Reset of a GPI function is general purpose input. A dash on the left side of the slash denotes that both the
input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down
enabled on the pin.
8Pullup is enabled only when JCOMP is negated.
9Tie to VSS for normal operation.
Table 2. MPC5668x Signal Properties (continued)
Pin
Name1Supported
Functions2
GPIO
(PCR)
Num3PA4Description I/O
Type Volt-
age Pad
Type5
Status Package Pin
Locations
During
Reset6After
Reset7208
BGA 256
BGA
Pin Assignments
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 25
3.3.1 Power and Ground Supply Summary
Table 3. MPC5668x Power/Ground
Pin
Name Function Description Voltage1
1Nominal voltages.
Package Pin Locations
208 256
VDD Internal Logic Power 1.2 V D4, D10, H4, G13, K13, N5 D4, D10, H4, G13, K13, N5
VDDE1 External I/O Power
3.3–5.0 V
D6 D6
VDDE2 L4 L4
VDDE3 J13 J13
VDDE4 N10 N10
VDDA Analog Power
3.3–5.0 V
B15 B15
VDD33 3.3 V I/O Power 3.3 V L13 L13
VDDEMLB Media Local Bus Power 2.5 or 3.3 V K4 K4
VDDENEX2
2Dedicated Nexus power pin on 256-pin package only. On the 208-pin package, VDDENEX is tied to VSS internal to the
package substrate and is not available externally.
Nexus Power 3.3 V E6, K11, L7
VRCSEL Voltage Regulator Select VSSA / VDDA H13 H13
VRC Voltage Regulator Control Voltage
3.3–5.0 V
B10 B10
VRCCTL Voltage Regula tor Control Output 3
3Base current to external NPN power transistor. Voltage may vary.
B11 B11
VDDSYN Clock Synthesizer Power 3.3 V A12 A12
VRH Analog High Voltage Reference
3.3–
5.0 V B16 B16
VRL Analog Low Voltage Reference 0 V C16 C16
VSS Ground 0 V A1, A16, D7, G4, G[7:10],
H[7:10], J[7:10], K[7:10], N13,
T1, T16
A1, A16, D7, E[7:12], F[7:12],
G4, G[6:12], H[7:12], J[7:12],
K[6:10], K12, L[8:10], L12,
N13, T1, T16
VSSA Analog Ground 0 V C15 C15
VSSSYN Clock Synthesizer Ground 0 V A15 A15
MPC5668x Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor26
4 Electrical Characteristics
This section contains detailed inform at ion on power considerations, DC/AC electrical characteristics, and AC timing
specifications for the MPC5668x.
4.1 Maximum Ratings
Table 4. Absolute Maximum Ratings1
1Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings
only , and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability
or cause per manent damage to the device.
Spec Characteristic Symbol Min Max Unit
1 1.2 V Core Supply Voltage2
2Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
VDD –0.3 1.323
32.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining.
V
2 3.3 V Clock Synthesizer Voltage2, 4
45.3 V for 10 hours cumulative time, 3.3 V +10% for time remaining.
VDDSYN –0.3 3.6 V
3 3.3 V I/O Buffer Voltage 2, 4VDD33 –0.3 3.6 V
4 3.3–5.0 V Voltage Regulator Con trol Voltage 2, 5, 6
56.4 V for 10 hours cumulative time, 5.0 V +10% for time remaining.
6VRC cannot be 100mV higher than VDDA. VDDSYN and VDD33 canno t be 100mV higher than VRC.
VRC –0.3 5.5 V
5 3.3–5.0 V Analog Supply Voltage (reference to VSSA) 2, 5VDDA –0.3 5.5 V
6 3.3–5.0 V Exter nal I/O Supply Voltage 2, 5, 7VDDE18
VDDE28
VDDE38
VDDE48
–0.3
–0.3
–0.3
–0.3
5.5
5.5
5.5
5.5
V
7 2.5–3.3 V Exter nal I/O Supply Voltage (MLB) 2, 4VDDEMLB8–0.3 3.6 V
8 3.3 V External I/O Supply Voltage (Nexus) 2, 4VDDENEX8–0.3 3.6 V
9 DC Inpu t Voltage9
VDDE1, VDDE2, VDDE3, VDDE4
VDDEMLB, VDDENEX
VIN –1.010
–1.09
V
DDEx
+
0.3
V
11
V
DDEx
+
0.3
V
10
V
10 Analog Ref erence High Voltage VRH –0.3 Minimum of
5.5
or
VDDA +0.3
V
11 Analog Ref erence Low Voltage VRL –0.3 5.5 V
12 VSS to VSSA Differential Voltage VSS –V
SSA –100 100 mV
13 VSS to VSSSYN Differential Voltage VSS –V
SSSYN –100 100 mV
14 Maximum DC Digital Input Current12 (per pin, applies to all
digital F, MH, SH, and IH pins) IMAXD –2 2 mA
15 Maximum DC Analog Input Current13 (per pin, applies to all
analog AE and A pins) IMAXA –3 3 mA
16 Storage Temperature Range TSTG –55.0 150.0 oC
17 Maximum Solder Temperature14 TSDR —235.0
oC
18 Moisture Sensitivity Level15 MSL 3
Electrical Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 27
4.2 Thermal Characteristics
4.2.1 General Notes for Specifications at Maxim um Junction Temperature
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
7All functional non-supply I/O pins are clamped to VSS and VDDEx.
8VDDEx are separate power segments and may be powered independently with no differential voltage constr aints between
the power segments.
9A C signal over and undershoot of the input voltages of up to ±2.0 V is permitted for a cum ulativ e duration of 60 hours ov er
the complete lifetime of the device (injection current does not need to be limited for this duration).
10 Internal structures will hold the input voltage above –1.0 V if the injection current limit of 2 mA is met.
11 Internal stru ctures hold the input voltage below this maximum voltage on all pads powered by VDDE supplies, if the
maximum injection current specification is met (25 mA for all pins) and VDDE is within Operating Voltage specifications.
12 Total injection current for all pins (including both digital and analog) must not exceed 25 mA.
13 Total injection current for all analog input pins must not exceed 15 mA.
14 Solder profile per CDF-AEC-Q100.
15 Moisture sensitivity per JEDEC test method A112.
Table 5. Thermal Characteristics
Spec Characteristic Symbol Unit Value
208 MAPBGA 2 56 MAPBGA
1 Junction to Ambient1, 2
Natural Convection
(Single layer board)
1Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
RJA °C/W 39 39
2 Junction to Ambient1, 3
Natural Convection
(Four layer board 2s2p)
3Per JEDEC JESD51-6 with the board horizontal.
RJA °C/W 24 24
3 Junction to Ambient1, 3
(@200 ft./min., Single layer board) RJMA °C/W 31 31
4 Junction to Ambient1, 3
(@200 ft./min., Four layer board 2s2p) RJMA °C/W 20 20
5 Junction to Board4
4Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
RJB °C/W 13 13
6 Junction to Case5
5Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
RJC °C/W 6 6
7 Junction to Package Top6
Natural Convection
6Thermal characterization parameter indicating the temperature diff erence between package top and the junction temperature
per JEDEC JESD51-2.
JT °C/W 2 2
MPC5668x Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor28
TJ=T
A+(R
JA PD)Eqn. 1
where:
TA = ambient temperature for the package (oC)
RJA = junction to ambient thermal resistance (oC/W)
PD = power dissipation in the package (W)
The supplied thermal resistances are provided based on JEDEC JESD51 series of standards to provide consistent values for
estimations and comparisons. The difference between the values determined on the single-layer (1s) board and on the four -layer
board with two signal layers and a power and a ground plane (2s2p) clearly demonstrate that the ef fective thermal resistance of
the component is not a constant. It depends on the construction of the application board (number of planes), the effective size
of the board which cools the component, how well the component is thermally and electrically connected to the planes, and the
power being dissipated by adjacent components.
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package
to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance
between through vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value
obtained on the board with the internal planes is usually appropriate if the application board has one oz. (35 micron nominal
thickness) internal planes, the components are well separated, and the overall power dissip ation on the board is less than 0.02
W/cm2.
The thermal performance of any component depends strongly on the power dissipation of surrounding components. In addition,
the ambient temperature varies widely within the application. For many natural convection and especially closed box
applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature
near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description
of the local ambient conditions that determine the temperature of the device.
At a known board temperature, the junctio n temperature is estimated using the following equation:
TJ=T
B+(R
JB PD)Eqn. 2
where:
TJ = junction temperature (oC)
TB = board temperature at the package perimeter (oC/W)
RJB = junction to board thermal resistance (oC/W) per JESD51-8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made.
The application board should be similar to the thermal test condition, with the component soldered to a board with internal
planes.
Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case
to ambient thermal resistance:
RJA =R
JC +R
CA Eqn. 3
where:
RJA = junction to ambient thermal resistance (oC/W)
RJC = junction to case thermal resistance (oC/W)
RCA = case to ambient thermal resistance (oC/W)
Electrical Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 29
RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
ambient thermal resistance, RCA. For instance, the user can chan ge the air flow around the device, a dd a heat sink, change the
mounting arrangement on printed circu it board, or change the thermal dissipation on the printed circuit board surrounding the
device. This description is most useful for packages with heat sinks where some 90% of the heat flow is through the case to the
heat sink to ambient. For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction to board thermal resistance and the junction
to case thermal resistance. The junction to case covers the situation where a heat sink will be used or where a substantial amount
of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance
when most of the heat is conducted to the printed circuit board. This model can be used for either hand estimations or for a
computational fluid dynamics (CFD) thermal model.
To determine the junction temperatu re of the device in the application after prototypes are available, the Thermal
Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at
the top center of the package case using the following equation:
TJ=T
T+(JT PD)Eqn. 4
where:
TT = thermocouple temperature on top of the package (oC)
JT = thermal characterization parameter (oC/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling ef fects
of the thermocouple wire.
References:
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic
Packaging and Production, pp. 53–58, March 1998.
3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application
in Thermal Modeling,” Proceedings of Sem iTherm , San Diego, 1999, pp. 212 –220.
MPC5668x Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor30
4.3 ESD Characteristics
4.4 VRC Electrical Specifications
4.5 DC Electrical Specifications
Table 6. ESD Ratings1, 2
1All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicab le device specification at room
temperature follo wed by hot temperature, unless specified otherwise in the device specification.
Characteristic Symbol Value Unit
ESD for Human Body Model (HBM) 2000 V
HBM Circuit Description R1 1500 Ohm
C100 pF
ESD for Field Induced Charge Model (FDCM) 750 (co rner pins) V
250 (all other pins)
Number of Pulses p er pin :
Positive Pulses (HBM)
Negative Pulses (HBM)
1
1
Inter val of Pulses 1 second
Table 7. VRC Electrical Specifications
Spec Characteristic Symbol Min Max Units
1Current which can be sourced by VRCCTL I_VRCCTL 6.25 µA 20 mA
2
Minimum Required Gain from external circuit:
IDD / I_VRCCTL (@VDD =1.32V)
1
–40C
25C
150C
1Assumes “typical usage” currents which will vary with application.
BETA 50
50
50 500
Table 8. DC Electrical Specifi cations
Spec Characteristic Symbol Min Max Unit
1
Maximum Opera ting Temp erature Ra nge — Die J unction Temperature
TJ–40.0 150.0 oC
2 3.3 V Clock Synthesizer Voltage1VDDSYN 3.0 3.6 V
3 3.3 V I/O Buffer Voltage1VDD33 3.0 3.6 V
4 3.3–5.0 V Voltage Regula tor Reference Voltage1
VRCSEL =V
SSA
VRCSEL =V
DDA
VVRC 3.0
4.5 3.6
5.5
V
5 3.3–5.0 V Analog Supply Voltage VDDA
maximum of
3.0 V or
V
VRC
–0.1
5.5 V
Electrical Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 31
6 3.3–5.0 V External I/O Supply Voltage2
VDDE1
VDDE2
VDDE3
VDDE4
3.0
3.0
3.0
3.0
5.5
5.5
5.5
5.5
V
7 2.5 V 3.3 V Exter nal I/O Supply Voltage (MLB) VDDEMLB32.375 3.6 V
8 3.3 V External I/O Supply Voltage (Nexus) VDDENEX 3.0 3.6 V
9 Pad Input High Voltage
Hysteresis enabled
Hysteresis disabled (IHA/SH/SHA/MH/MHA)4, 5
Hysteresis disabled (F)
VIH 0.65 VDDE
0.55 VDDE
0.55 VDDE
VDDE +0.3 V
10 Pad Input Low Voltage
Hysteresis enabled
Hysteresis disabled (IHA/SH/SHA/MH/MHA)4, 5
Hysteresis disabled (F)
VIL VSS –0.3 0.35 VDDE
0.40 VDDE
0.40 VDDE
V
11 Pad Input Hysteresis VHYS 0.1 VDDE V
12 Analog (IHA) Input Voltage VINDC VSSA –0.3 V
DDA +0.3 V
13 Pad Output High Voltage6, 7, 8 V
OH 0.8 VDDE —V
14 Pad Output Low Voltage8VOL —0.2VDDE V
15 Input Capacitance (Digital Pins: Pad type F, MH, SH)4 C
IN —7pF
16 Input Capacitance (Analog Pins: Pad type IHA)4, 5CIN_A —10pF
17 Input Capacitance (Shared digital/analog pins: MHA, SHA)4 CIN_M —12pF
18 I/O Weak Pull Up/Down Absolute Current4, 9
Pad F: 2.375 V 3.6 V
Pad SH/MH/IHA: 3.0 V 3.6 V
Pad SH/MH/IHA: 4.5 V 5.5 V
IACT 25
10
35
180
95
200
A
19 I/O Input Leakage Current10 IINACT_D –2.5 2.5 A
20 DC Injection Current (per pin) IIC –1.0 1.0 mA
21 Analog Input Current, Channel Off11 (Analog pins IHA)4, 5IINACT_A –150 150 nA
22 Analog Reference High Voltage VRH VDDA –500 V
DDA mV
23 Analog Reference Low Voltage VRL VSSA VSSA +500 mV
24 VSS to VSSA Differential Voltage VSS –V
SSA –100 100 mV
25 VSSSYN to VSS Differential Voltage VSSSYN –V
SS –100 100 mV
26 Slew rate on VDDA, VDDEx, VDDSYN, VDD33, and VRC pow er supply
pins VRamp —100V/ms
27 Capacitive Supply Load (VDD)V
Load 8—µF
28 Capacitive Supply Load (VDD33, VDDSYN)V
Load 1—µF
1When VRCSEL = VSSA (low), VDDSYN and VDD33 are externally supplied. When VRCSEL = VDDA (high), VDDSYN and VDD33 are
generated by internal v oltage regulators. When VRCSEL = VSSA (low), VDDSYN and VDD33 cannot be 100 mV higher than VRC.
Table 8. DC Electrical Specifi cations
Spec Characteristic Symbol Min Max Unit
MPC5668x Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor32
4.6 Operating Current Specifications
2VDDE1 – VDDE4 are separate power segments and may be powered independently with no differential voltage constraints
between the power segments. VDDE1 – VDDE3 pad power segments contain ADC analog input channels and thus the input
analog signal le vel ma y be clamped to the VDDE lev el, resulting in inaccurate ADC results if the VDDE v oltage le v el is less than
VDDA.
3When VRCSEL = VDDA (high), the internally generated VDD33 voltage may be used to power VDDEMLB as long as the PK[0:2 ]
pads remain in the disabled default state with their output buffers, input buffers, and pull devices disabled.
4The pad type is indicated by one or more of the following abbreviations: A–analog, F—fast speed, H–high voltage, I—input-only ,
M–medium speed, S–slow speed. For example, pad type SH designates a slow high-voltage pad.
5The IHA pads are related to VDDA.
6Characterization Based Capability:
IOH_F = {12, 20, 30, 40} mA and IOL_F = {24, 40, 50, 65} mA for {00, 01,10, 11} dr ive mode with VDDE = 3.0 V;
IOH_F = {7, 13, 18, 25} mA and IOL_F = {18, 30, 35, 50} mA for {00, 01, 10, 11} drive mode with VDDE =2.25 V;
IOH_F = {3, 7, 10, 15} mA and IOL_F = {12, 20, 27, 35} mA for {00, 01, 10, 11} drive mode with VDDE =1.62 V.
7Characterization Based Capability:
IOH_S = {6, 11.6} mA and IOL_S = {9.2, 17.7} mA for {slow, medium} I/O with VDDEH = 4.5 V;
IOH_S = {2.8, 5.4} mA and IOL_S = {4.2, 8.1} mA for {slow, medium} I/O with VDDEH = 3.0 V
8All VOL/VOH values 100% tested with ±2 mA load .
9Absolute value of current, measured at VIL and VIH.
10 W eak pull up/down inactive. Measured at VDDE = 5.25 V. Applies to pad types: SH and MH. Leakage specification guaranteed
only when power supplies are within specified operating conditions.
11 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by appro ximately one-half for each
8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types: pad_a and pad_ae.
Table 9. Operating Currents
Spec Characteristic Symbol Typ1
25 C
Ambient
Max1
–40–150 C
Junction Unit
Equations ITOTAL =I
DDE +I
DDA +I
RH +I
DD33 +I
DDSYN +I
RC +I
DD
IDDE =I
DDE1 +I
DDE2 +I
DDE3 +I
DDE4 +I
DDEMLB
1V
DDE Current
VDDE(1,2,3,4) @ 3.0V–5.5V
VDDEMLB @ 2.375V–3.6V
Static2
Dynamic3
IDDE
0
Note 3 30
25 A
mA
2V
DDA Current
VDD A @ 3.0V–5.5V
Run mode
Sleep mode
– Optional 32 kHz osc enabled
IDDA
1
20
+5
30
50
+15
mA
A
A
3V
RH Current
VRH @ 3.0V–5.5V
Run mode
Sleep mode
IRH
300
1700
30 A
A
4V
DD33 Current
VDD33 @ 3.0V–3.6V
Run mode
Sleep mode
IDD33
10
10 20
20 mA
A
Electrical Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 33
5V
DDSYN Current
VDD33 @ 3.0V–3.6V
Run mode
Sleep mode
– Optional4 4–40 MHz osc ena bled w/ no clock
– Optional4 4–40 MHz osc enabled w/ clock
IDDSYN
5
1
+150
+300
10
20
+350
+400
mA
A
A
A
6V
RC Current (excluding IDD, IDD33, IDDSYN)5
VRC @ 3.135 V 5.5 V
Run mode
Sleep mode
– Optional4 16MIRC enabled
IRC
1
0
+40
10
10
+60
mA
A
A
7V
DD Current
VDD @ 1.08 V 1.32 V
Run mode (Maximum @ 116 MHz)6
Sleep mode
– Optional4 128KIRC enabled
– Optional4 16MIRC enabled
– Optional4 32 kHz osc enabled
– Optional4 4–40 MHz osc ena bled w/ no clock
– Optional4 4–40 MHz osc enabled w/ clock
– Optional4 32 KB RAM
– Optional4 64 KB RAM
– Optional4 128 KB RAM
IDD
200
100
+5
+200
+5
+5
+150
+10
+20
+40
340
900
+10
+220
+20
+20
+200
+150
+300
+600
mA
A
A
A
A
A
A
A
A
A
1Typ Nomi nal voltage levels and functiona l ac tivity. Max Maximum voltage levels and functional activity.
2Static state of pins is when input pins are disabled or not being toggled and driven to a valid input level, output pins are not
toggling or dr iving against any current loads, and internal pull devices are disabled or not pulling against any current loads.
3Dynamic current from pins is application-specific and depends on active pull devices , s witching outputs, output capacitiv e and
current loads, and switching inputs. Refer to Table 10 for more information.
4Optional currents are values that should be added to their respective current specifications to obtain the actual value for that
specification when the optional functio n is ac tive. The plus sign (+) in the Typ and Max columns indicates these optional
currents. For example, VDDSYN in Sleep mode draws 1 .A (typ). With the optional 4–40 MHz osc enabled w/ no clock, add
150 .A for a total of 151 .A (typ).
5VRC Current excluding the current supply to VDD33, VDDSYN and VDD from VRC.
6Maximum supply current transition: 50mA per 20S observation window.
Table 9. Operating Currents (continued)
Spec Characteristic Symbol Typ1
25 C
Ambient
Max1
–40–150 C
Junction Unit
MPC5668x Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor34
4.7 I/O Pad Current Specifications
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption
is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 10 based on
the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load
parameters that fall outside the values given in Table 10.
Table 10. I/O Pad Average IDDE Specifications1
1These are typical values that are estimated from simulation and not tested. Currents apply to outp ut pins only.
Spec Pad
Type2
2Slow = SH or SHA; Medium = MH or MHA; F a st = F; Input = IHA. See Table 2.
Symbol Period
(ns) Load3
(pF)
3All loads are lumped.
VDDE
(V) Drive/Slew
Rate Select IDDE Avg
(mA) IDDE RMS
(mA)
1
Slow IDRV_SSR_HV
37 50 5.5 11 14
2 130 50 5.5 01 5.3
3 650 50 5.5 00 1.1
4 840 200 5.5 00 3
6
Medium IDRV_MSR_HV
24 50 5.5 11 9
7 62 50 5.5 01 2.5
8 317 50 5.5 00 0.5
9 425 200 5.5 00 1.5
11
Fast IDRV_FC
10 50 3.6 11 50.4 101.6
12 10 30 3.6 10 14.2 57.3
13 10 20 3.6 01 16.4 43.6
14 10 10 3.6 00 9.8 15.9
15 10 50 2.75 11 22.9 45.3
16 10 30 2.75 10 6.7 25.3
17 10 20 2.75 01 4.5 17.3
18 10 10 2.75 00 3 9.6
19 Input
IDRV_I_HV 7 0.5 5.5 N/A N/A N/A
Electrical Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 35
4.7.1 I/O Pad VDD33 Current Specifications
The power consumption of the VDD33 supply is dependent on the usage of the pins on all I/O segments. The power consumption
is the sum of all input and output pin VDD33 currents for all I/O segments. The output pin VDD33 current can be calculated from
Table 11 based on the voltage, frequency, and load on all Pad F pins. The input pin VDD33 current can be calculated from
Table 11 based on the voltage, frequency, and load on all Pad MH pins. Use linear scaling to calculate pin currents for voltage,
frequency, and load parameters that fall outside the values given in Table 11.
Table 11. I/O Pad Average IDD33 Specifications1
1These are typical values that are estimated from simulation and not tested. Currents apply to output pins only.
Spec Pad
Type2
2Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 2.
Symbol Period
(ns) Load3
(pF)
3All loads are lumped.
Drive
Select IDD33 Avg
(µA) IDD33 RMS
(µA)
1
Slow IDRV_SSR_HV
100 50 11 0.8 235.7
2 200 50 01 0.04 87.4
3 800 50 00 0.06 47.4
4 800 200 00 0.009 47
5
Medium IDRV_MSR_HV
40 50 11
6 100 50 01 0.11 76.5
7 500 50 00 0.02 56.2
8 500 200 00 0.01 56.2
9 Input IDRV_I_HV 70.5N/A
Table 12. IDD33 Pad Average DC Current1
1These are typical values that are estimated from simulation and not tested. Currents apply to output pins only.
Spec Pad
Type2
2Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 2.
Symbol Period
(ns) Load3
(pF)
3All loads are lumped.
VDD33
(V) VDDE
(V) Drive
Select IDD33 Avg
(µA) IDD33 RMS
(µA)
1
Fast IDRV_FC
10 50 3.6 3.6 11 3.32 11.77
2 10 30 3.6 3.6 10 2.28 7.07
3 10 20 3.6 3.6 01 1.73 5.75
4 10 10 3.6 3.6 00 1.39 4.77
5 10 50 3.6 2.75 11 2.3 7.81
6 10 30 3.6 2.75 10 1.64 4.96
7 10 20 3.6 2.75 01 1.37 4.31
8 10 10 3.6 2.75 00 1.06 4.09
MPC5668x Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor36
4.8 Low Voltage Characteristics
4.9 Oscillators Electrical Characteristics
Table 13. Low Voltage Monitors
Spec Characteristic Symbol Min Typical Max Unit
1 Power-on-Reset Assert Level1
1Monitors VDDA.
VPOR 1.5 2.8 V
2 Low Voltage Moni tor 3.3 V2
Assert Level
De-assert Level
2Monitors VDD33.
VLVI33A
VLVI33D
3.00
3.04 3.05
3.12 3.10
3.19
V
3 Low Voltage Monitor Synthesizer3
Assert Level
De-assert Level
3Monitors VDDSYN.
VLVISYNA
VLVISYND
3.00
3.04 3.05
3.12 3.10
3.19
V
4
Low Voltage Monitor 3.0 V Low Threshold
1
VRCSEL = V
SSA
Assert Level
De-assert Level
VRCSEL
=V
DDA
Assert Level
De-assert Level
VLVI_VDDA_LOA
VLVI_VDDA_LOD
VLVI_VDDA_LOA
VLVI_VDDA_LOD
3.00
3.04
3.25
3.35
3.05
3.12
3.35
3.45
3.10
3.19
3.48
3.55
V
5 Low Voltage Moni tor 5.0 V1, 4
Assert Level
De-assert Level
4Disabled when VRCSEL =V
SSA.
VLVI_VDDA_A
VLVI_VDDA_D
4.35
4.45 4.475
4.575 4.55
4.65
V
6 Low Voltage Monitor 5.0 V High Threshold1, 5
Assert Level
De-assert Level VLVI_VDDA_HA
VLVI_VDDA_HD
4.50
4.50 4.675
4.675 4.80
4.80
V
Table 14. 3.3 V High Frequency External Oscillator
Spec Characteristic Symbol Min Max Unit
1 Frequency Range fref 4
140 MHz
2 Duty Cycle of reference tDC 40 60 %
3 EXTAL Input High Voltage
External crystal mode2
External clock mode
VIHEXT VXTAL +0.4
0.65 VDDSYN
VDDSYN +0.3
VDDSYN +0.3
V
4 EXTAL Input Low Voltage
External crystal mode3
External clock mode
VILEXT VDDSYN –0.3
VDDSYN –0.3 VXTAL –0.4
0.35 VDDSYN
V
5 XTAL Current4IXTAL 13mA
6 Total On -chip stray capacitance on XTAL CS_XTAL —3pF
7 Total On -chip stray capacitance on EXTAL CS_EXTAL —3pF
Electrical Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 37
8 Crystal manufacturer’s recommended
capacitive load CLSee crystal
specification See crystal
specification pF
9 Discrete load capacitance to be connected
to EXTAL CL_EXTAL —2CL–C
S_EXTAL
CPCB_EXTAL5pF
10 Discrete load capacitance to be connected
to XTAL CL_XTAL —2CL–C
S_XTAL –C
PCB_XTAL5pF
11 Startup Time tstartup —10ms
1When PLL frequency modulation is active, ref erence frequencies less than 8 MHz will distort the modulated wa vef orm and the
effects of this on emissions is not characterized.
2This parameter is meant f or those who do not use quartz crystals or resonators, but instead use CAN oscillators in crysta l
mode. In that case, Vextal –V
xtal 400 mV criteria has to be met for oscillator’s comparator to produce output clock.
3This parameter is meant f or those who do not use quartz crystals or resonators, but instead use CAN oscillators in crysta l
mode. In that case, Vxtal –V
extal 400 mV criteria has to be met for oscillator’s comparator to produce output clock.
4Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
5CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
Table 15. 5 V Low Frequency (32 kHz) External Osci lla tor
Spec Characteristic Symbol Min Max Unit
1 Frequency Range fref32 32 40 kHz
2 Duty Cycle of reference tdc32 40 60 %
3 XTAL32 Current1
1Ixtal32 is the oscillator bias current out of the XTAL32 pin with both EXTAL32 and XTAL32 pins grounded.
IXTAL32 —3A
4 Crystal manufacturer’s recommended
capacitive load CL32 See crystal
specification See crystal
specification pF
5 Startup Time tStartup —2s
Table 16. 5 V High Frequency (16 MHz) Internal RC Oscillator
Spec Characteristic Symbol Range Min Typ Max Unit
1 Frequency before trim1
1Across process, voltage, and temperature.
fut 35% 10.4 16 21.6 MHz
2 Frequency after loading factory trim2
2Across voltage and temperature.
ft7% 14.9 16 17.1 MHz
3 Application trim resolution3
3Fixed voltage and temperature.
ts—— 05%
4 Application frequency trim step3fs 300 kHz
5 Startup Time tStartup 500 ns
Table 14. 3.3 V High Frequency External Oscillator (cont inued)
Spec Characteristic Symbol Min Max Unit
MPC5668x Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor38
4.10 FMPLL Electrical Characteristics
Table 17. 5V Low Frequency (128 kHz) Internal RC Oscillator
Spec Characteristic Symbol Range Min Typ Max Unit
1 Frequency bef o re trim1
1Across process, voltage, and temperature.
Fut128 35% 83.2 128 172.8 kHz
2 Frequency after loading factory trim2
2Across voltage and temperature.
Ft128 7% 119.0 128 137.0 kHz
3 Application trim resolution3
3Fixed voltage and temperature.
Ts128 —— 2%
4 Application frequency tr im step3Fs128 4 kHz
5 Startup Time St128 —— 100s
Table 18. FMPLL Electrical Specifications 1
1VDDSYN = 3.0 V to 3.6 V, VSS =V
SSSYN =0V, T
A=T
L to TH.
Spec Characteristic Symbol Min Max Unit
1 System Frequency2fSYS 116 MHz
2 PLL Reference Frequency Rang e fREF 440MHz
3 PLL Frequency fPLL MHz
4 Loss of Reference Frequency 3fLOR 100 2000 kHz
5 Self Clocked Mode Frequency fSCM 16 64 MHz
6PLL Lock Time4tLPLL 400 s
7Duty Cycle of Reference tDC 40 60 %
8 Frequency un-LOCK Range fUL –4.0 4.0 % fSYS
9 Frequency LOCK Range fLCK –2.0 2.0 % fSYS
10 CLKOUT Period Jitter,5 Measured at fSYS Max
Cycle-to-cycle Jitter CJitter –5 5
%
fSYS
11 CLKOUT Jitter at 50 µs period CJitter –250 250
ns
12
Peak-to-Peak Frequency Modulat ion Range Limit
6,7
(fSYSMax must not be exceeded) Cmod 04
%fSYS
13 FM Depth Tolerance8Cmod_err –0.50 0.50 %fSYS
14 VCO Frequency9fVCO 192 600 MHz
15 Modulation Rate Limits10 fMOD 0.400 1 MHz
fvco min
ERFD 1+
------------------------------
Electrical Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 39
4.11 ADC Electrical Characteristics
4.12 Flash Memory Electrical Characteristics
2The maximum frequency value is with frequency modulation disabled. If frequency modulation is enabled, the maximum
frequency value should be de-rated by the percentage of modulation enabled so that the maximum frequency is not exceeded.
3“Loss of Reference F requency” is the reference frequency detected internally, which transitions the PLL into self clock ed mode.
4This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillato r reference, lock time will be additive with crystal
startup time.
5Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter +C
mod.
6Modulation depth selected must not result in fPLL value greater than the fPLL maximum specified value.
7Maximum and minimum variations from programmed modulation depth are 2%, 3%, and 4% peak-to-peak. Use only these
settings.
8Depth tolerance is the programmed modulation depth ±0.25% of fSYS.
9See the Block Guide for VCO frequency synthesis equations.
10 Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than
1 MHz will result in reduced calibration accuracy.
Table 19 . ADC Conversion Specifications (Operating)
Spec Characteristic Symbol Min Max Unit
1 Analog High Reference Voltage VRH VDDA –0.5 V
DDA V
2 Analog Low Reference Voltage VRL 00.5V
3 Analog Input Voltage AVIN VRL VRH V
4 Sampling Frequency FS—1.53MHz
5 Maximum ADC Clock Frequency FMAX —60MHz
6 Sampling Time
VDDA =3.0V–3.6V
VDDA >3.6V–5.5V
tS250
125
—ns
7 Differential Non Linearity DNL –1.0 1.0 LSB
8 Integral Non Linearity INL –1.5 1.5 LSB
9 Offset Error OFS –1.0 1.0 LSB
10 Gain Error GNE –2.0 2.0 LSB
11 Total Unadjusted Error 1
1TUE assumes no pin activity on pins adjacent to analog channel or output driver activity on corresponding VDDE segment.
TUE –2.0 2.0 LSB
Table 20. Flash Pr ogram and Erase Specifications1
Spec Characteristic Symbol Min Initial
Max2Max3Unit
1 Double Word (64 bits) Program Time4tdwprogram —— 500 s
2 Page (128 bits and 256 bits) Program Time4tpprogram 160 500 s
3 16 KB Block Pre-program and Erase Time t16kpperase 1000 5000 ms
4 64 KB Block Pre-program and Erase Time t64kpperase 1800 5000 ms
5 128 KB Block Pre-program and Erase Time t128kpperase 2600 7500 ms
MPC5668x Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor40
4.13 Pad AC Specifications
6 256 KB Block Pre-program and Erase Time t256kpperase 5200 15,000 ms
7 Wait States Relative to System Frequency5
PFCRPn[RWSC] = PFCRPn[APC] = 0b000; PFCRPn[WWSC] = 0b01
PFCRPn[RWSC] = PFCRPn[APC] = 0b001; PFCRPn[WWSC] = 0b01
PFCRPn[RWSC] = PFCRPn[APC] = 0b010; PFCRPn[WWSC] = 0b01
PFCRPn[RWSC] = PFCRPn[APC] = 0b011 0b111; PFCRPn[WWSC] = 0b01
trwsc
30
60
90
fSYS max
MHz
8 Recovery Time tRecover —— 45 s
1Typical program and erase times assume nominal supply values and operation at 25 oC.
2Initial factory condition: 100program/erase cycles, nominal supply values and operation at 25 oC.
3The maximum time is at worst case conditions after the specified number of program/erase cycles. This maximum value is
characterized but not guaranteed.
4Actual hardware programming time. This does not include software overhead.
5Wait state timing is based on the system clock frequency and thus is same for all masters.
Table 21. Flash EEPROM Module Life (Full Temperature Range)
Spec Characteristic Symbol Min Typical1
1Typical endurance is evaluated at 25 oC. Product qualification is performed to the minimum specification. For additional
information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance
for Nonvolatile Memory.
Unit
1 Number of Program/Erase cycles per block for 16 KB and 64 KB blocks
over the operating temperature range (TJ)P/E 100,000 cycles
2 Number of Program/Erase cycles per block for 128 KB blocks over the
operating temperature range (TJ)P/E 1,000 100,000 cycles
3 Minimum Data Retention at 85 °C ambient temperature2
Blocks with 0–1,000 P/E cycles
Blocks with 1,001–10,000 P/E cycles
Blocks with 10,001–100,000 P/E cycles
2Ambient temperature averaged over duration of application, not to exceed product operating temperature range.
Retention 20
10
1–5
—years
Table 22. Pad AC Specific at ions (5 .0 V, 2.5 V) 1
Spec Pad Type2SRC/DSC3Output Delay4,4 (ns) Rise/Fall5,6
(ns) Load Drive
(pF)
1Slow7
00 318/343 155/173 50
408/431 188/204 200
01 61/67 30/34 50
80/90 38/44 200
11 18/18 10/11 50
27/28 15/17 200
Table 20. Flash Program and Erase Specifications1 (continued)
Spec Characteristic Symbol Min Initial
Max2Max3Unit
Electrical Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 41
2Medium
00 142/186 65/89 50
195/253 91/122 200
01 20/35 8.7/16.6 50
41/64 24/35 200
11 12/11 5.3/5.9 50
32/34 21/23 200
3Fast8
00
2.7 1.5
10
01 20
10 30
11 50
4 Input N/A 1.9/1.9 1.5/1.5 0.5
1These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
FSYS = 116 MHz, VDD = 1.08 1.32 V, VDDE = 1.62 1.98 V, VDDEH =4.5–5.5V, V
RC33 and VDDPLL =3.0–3.6V, T
A=T
L to
TH.
2Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 2.
3SRC/DSC are bit fields in the Pad Configuration Registers. SRC—Slew Rate Control (slow and medium pad types only),
DSC—Drive Strength Control (fast pad type only).
4This parameter is supplied for reference and is not guaranteed by design and not tested.
5This parameter is guaranteed by characterization before qualification rather than 100% tested.
6Delay and r ise/fall are measured to 20% or 80% of the respective signal.
7Add a maximum of one system clock to the output delay for delay with respect to system clock.
8Output delay is shown in. Add a maximum of one system clock to the output delay for delay with respect to system clock.
Table 23. De-rated Pad AC Specifications (3.3 V, 3.3 V)1
Spec Pad Type2SRC/DSC3Out Delay4,5
(ns) Rise/Fall6,
(ns) Load Drive
(pF)
1Slow7
00 408/431 188/204 50
533/592 250/288 200
01 80/90 38/44 50
146/167 82/96 200
11 27/28 15/17 50
81/92 57/67 200
2Medium
00 184/240 79/107 50
253/330 114/153 200
01 28/47 11.8/21.8 50
58/88 34/49 200
11 18/17 7.6/8.9 50
46/51 30/35 200
Table 22. Pad A C Specifications (5.0 V, 2.5 V)1 (continued)
Spec Pad Type2SRC/DSC3Output Delay4,4 (ns) Rise/Fall5,6
(ns) Load Drive
(pF)
MPC5668x Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor42
Figure 6. Pad Output Delay
3Fast8
00
2.5
1.2 10
01 1.2 20
10 1.2 30
11 1.2 50
4 Input N/A 3/3 1.5/1.5 0.5
1These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
FSYS = 116 MHz, VDD = 1.08 1.32 V, VDDE =3.0–3.6V, V
DDEH =3.0–3.6V, V
RC33 and VDDPLL = 3.0 3.6 V, TA=T
L to
TH.
2Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 2.
3SRC/DSC are bit fields in the Pad Configuration Registers. SRC—Slew Rate Control (slow and medium pad types only),
DSC—Drive Strength Control (fast pad type only).
4This parameter is supplied for reference and is not guaranteed by design and not tested.
5Delay and r ise/fall are measured to 20% or 80% of the respective signal.
6This parameter is guaranteed by characterization before qualification rather than 100% tested.
7Add a maximum of one system clock to the output delay for delay with respect to system clock.
8Output delay is shown in Figure 6. Add a maximum of one system clock to the output delay f or delay with respect to system
clock.
Table 23. De-rated Pad AC Specifications (3.3 V, 3.3 V )1 (continued)
Spec Pad Type2SRC/DSC3Out Delay4,5
(ns) Rise/Fall6,
(ns) Load Drive
(pF)
VDD/2
VOH
VOL
Rising
Edge
Out
Delay
Falling
Edge
Out
Delay
Pad
Internal Data Input Signal
Pad
Output
Electrical Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 43
4.14 AC Timing
4.14.1 Reset and Boot Configuration Pins
Figure 7. Reset and Boot Configuration Timing
4.14.2 External Interrupt (IRQ) and Non-Maskable Interrupt (NMI) Pins
Figure 8. IRQ and NMI Timing
Table 24. Reset and Boot Configuration Timing
Spec Characteristic Symbol Min Max Unit
1 RESET Pulse Width tRPW 150 ns
2 BOOTCFG Setup Time after RESET Valid tRCSU 100 s
3 BOOTCFG Hold Time from RESET Va lid tRCH 0—s
Table 25. IRQ/NMI Timing
Spec Characteristic Symbol Min Max Unit
1 IRQ/NMI Pulse Width Low tIPWL 3—t
SYS
2 IRQ/NMI Pulse Width High TIPWH 3—t
SYS
3 IRQ/NMI Edge to Edge Time1
1Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both.
tICYC 6—t
SYS
1RESET
3
BOOTCFG
2
IRQ/NMI
1,2 1,2
3
MPC5668x Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor44
4.14.3 JTAG (IEEE 1149.1) Interface
Figure 9. JTAG Test Clock Input Timing
Table 26. JTAG Interface Timi ng1
1These specifications apply to JTAG boundary scan only. JTAG timing specified at VDDE =3.0–5.5V, T
A=T
L to TH, and
CL= 30 pF with SRC = 0b11.
Spec Characteristic Symbol Min Max Unit
1 TCK Cycle Time tJCYC 100 ns
2 TCK Clock Pulse Width (Measured at VDDE/2) tJDC 40 60 ns
3 TCK Rise and Fall Times (40% 70%) tTCKRISE —3ns
4 TMS, TDI Data Setup Time tTMSS, tTDIS 5—ns
5 TMS, TDI Data Hold Time tTMSH, tTDIH 25 ns
6 TCK Low to TDO Data Valid tTDOV —25ns
7 TCK Low to TDO Data Invalid tTDOI 0—ns
8 TCK Low to TDO High Impedance tTDOHZ —20ns
9 JCOMP Assertion Time tJCMPPW 100 ns
10 JCOMP Setup Time to TCK Low tJCMPS 40 ns
11 TCK Falling Edge to Output Valid tBSDV —50ns
12 TCK Fa lling Edge to Output Valid out of High Impedance tBSDVZ —50ns
13 TCK Fa lling Edge to Output High Impedance tBSDHZ —50ns
14 Boundary Scan Input Valid to TCK Rising Edge tBSDST 50 ns
15 TCK Rising Edge to Boundary Scan Input Invalid tBSDHT 50 ns
TCK
1
2
2
3
3
Electrical Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 45
Figure 10. JTAG Test Access Port Timing
Figure 11. JTAG JCOMP Timing
TCK
4
5
6
78
TMS, TDI
TDO
TCK
JCOMP
9
10
MPC5668x Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor46
Figure 12. JTAG Boundary Scan Timing
TCK
Output
Signals
Input
Signals
Output
Signals
11
12
13
14
15
Electrical Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 47
4.14.4 Nexus Debug Interface
Figure 13. Nexus Output Timing
Table 27. Nexus Debug Port Timing1
1JTA G specifications in this table apply when used f or deb ug functionality. All Ne xus timing relative to MC KO is measured f rom
50% of MCKO and 50% of the respective signal. Ne xus timing specified at VDDE =3.0–5.5V, T
A=T
L to TH, and CL=30pF
with SRC = 0b11.
Spec Characteristic Symbol Min Max Unit
1 MCKO Cycle Time tMCYC 15.6 ns
2 MCKO Duty Cycle tMDC 40 60 %
3 MCKO Low to MDO, MSEO, EVTO Data Valid2
2MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
tMDOV –0.1 0.25 tMCYC
4 EVTI Pulse Width tEVTIPW 4.0 tTCYC
5 EVTO Pulse Width tEVTOPW 1t
MCYC
6 TCK Cycle Time3
3The system clock frequency needs to be three times faster than the TCK frequency.
tTCYC 40 ns
7 TCK Duty Cycle tTDC 40 60 %
8 TDI, TMS Data Setup Time tNTDIS, tNTMSS 8—ns
9 TDI, TMS Data Hold Time tNTDIH, tNTMSH 5—ns
10 TCK Low to TDO Data Valid tJOV 025ns
1
2
MCKO
MDO
MSEO
EVTO Output Data Valid
3
EVTI 4
5
MPC5668x Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor48
Figure 14. Nexus TDI, TMS, TDO Timing
TDO
8
9
TMS, TDI
10
TCK
6
7
Electrical Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 49
4.14.5 Enhanced Modular I/O Subsystem (eMIOS)
Figure 15. eMIOS Timing
Table 28. eMIOS Timing1
1eMIOS timing specified at VDDE = 3.0 5.5 V, TA=T
L to TH, and CL = 30 pF with SRC = 0b11.
Spec Characteristic Symbol Min Max Unit
1 eMIOS Input Pulse Width tMIPW 4—t
CYC
2 eMIOS Output Pulse Width tMOPW 12
2This specification does not include the rise and f all times. When calculating the minimum eMIOS pulse width, include the rise
and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
—t
CYC
D_CLKOUT
1
2
eMIOS output
eMIOS input
MPC5668x Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor50
4.14.6 Deserial Serial Peripheral Interface (DSPI)
Table 29. DSPI Timing
Spec Characteristic Symbol 116 MHz1
1116 MHz timing specified at CL = 50 pF with SRC = 0b11.
Unit
Min. Value Max. Value
1 DSPI Cycle Time
Master (MTFE = 0)
Slave (MTFE = 0)
Master (MTFE = 1)
Slave (MTFE = 1)
tSCK 100
100
50
50
ns
ns
ns
ns
2 PCS to SCK Delay2
2The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK].
tCSC 7—ns
3 After SCK Delay3
3The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC].
tASC 14 ns
4 SCK Duty Cycle tSDC 0.4 tSCK 0.6 tSCK ns
5 Slave Access Time
(SS active to SOUT valid) tA25 ns
6 Slave SOUT Disable Time
(SS inactive to SOUT High-Z or invalid) tDIS 25 ns
7 PCSx to PCSS time tPCSC 0—ns
8PCSS
to PCSx time tPASC 0—ns
9 Da ta Setup Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)4
Master (MTFE = 1, CPHA = 1)
4This number is calculated assuming the SMPL_PT bit fi eld in DSPI_MCR is set to 0b10.
tSUI 25
5
10
25
ns
ns
ns
ns
10 Data Hold Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)4
Master (MTFE = 1, CPHA = 1)
tHI –4
7
12
–4
ns
ns
ns
ns
11 Data Valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tSUO
8
28
15
8
ns
ns
ns
ns
12 Data Hold Time for Outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tHO –7
2
1
–7
ns
ns
ns
ns
Electrical Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 51
Figure 16. DSPI Classic SPI Timing — Master, CPHA = 0
Figure 17. DSPI Classic SPI Timing — Master, CPHA = 1
Data Last Data
First Data
First Data Data Last Data
SIN
SOUT
PCSx
SCK Output 4
9
12
1
11
10
4
SCK Output
(CPOL = 0)
(CPOL = 1)
3
2
PCSx
SIN
SCK Output
SCK Output
(CPOL = 0)
(CPOL = 1)
SOUT
Data Last Data
First Data
12 11
10
Last Data
Data
First Data
9
MPC5668x Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor52
Figure 18. DSPI Classic SPI Timing — Slave, CPHA = 0
Figure 19. DSPI Classic SPI Timing — Slave, CPHA = 1
Last Data
First Data
3
4
1
Data
Data
SIN
SOUT
SS
4
5 6
9
11
10
12
SCK Input
First Data Last Data
SCK Input
2
(CPOL = 0)
(CPOL = 1)
5 6
9
12
11
10
Last Data
Last Data
SIN
SOUT
SS
First Data
First Data
Data
Data
SCK Input
SCK Input
(CPOL = 0)
(CPOL = 1)
Electrical Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 53
Figure 20. DSPI Modified Transfer Format Timing — Master, CPHA = 0
Figure 21. DSPI Modified Transfer Format Timing — Master, CPHA = 1
PCSx3
1
4
10
4
9
12 11
SCK Output
SCK Output
SIN
SOUT
First Data Data Last Data
First Data Data Last Data
2
(CPOL = 0)
(CPOL = 1)
PCSx
10
9
12 11
SCK Output
SCK Output
SIN
SOUT
First Data Data Last Data
First Data Data Last Data
(CPOL = 0)
(CPOL = 1)
MPC5668x Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor54
Figure 22. DSPI Modified Transfer Format Timing — Slave, CPHA = 0
Figure 23. DSPI Modified Transfer Format Timing — Slave, CPHA = 1
Figure 24. DSPI PCS Strobe (PCSS) Timing
Last Data
First Data
3
4
1
Data
Data
SIN
SOUT
SS
4
5 6
9
11
10
SCK Input
First Data Last Data
SCK Input
2
(CPOL = 0)
(CPOL = 1)
12
5 6
9
12
11
10
Last Data
Last Data
SIN
SOUT
SS
First Data
First Data
Data
Data
SCK Input
SCK Input
(CPOL = 0)
(CPOL = 1)
PCSx
78
PCSS
Electrical Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 55
4.14.7 MLB Interface
4.14.7.1 Media Local Bus DC Electrical Characteristics
Table 30 provides the DC electrical characteristics for the Media Local Bus interface.
Table 30. Media Local Bus DC Ele ct rica l Ch ara ct e ri st ic s
4.14.7.2 Media Local Bus (MLB) AC Electrical Characteristics
Table 31 and Table 32 provide the AC electrical characteristics for the Media Local Bus interface.
Parameter Symbol Min Typ Max Unit Comments
Maximum Input Voltage 3.6 V
Low Level Input Threshold VIL ——0.7 V
High Level Input Threshold VIH 1.81
1Higher VIH thresholds can be used; howe v er , the risks associated with less noise margin in the system must be e valuated and
assumed by the customer.
—— V
Low Level Output Threshold VOL ——0.4 V I
OL =6mA
High Level Output Threshold VOH 2.0 V IOH =–6mA
Input Leakage Current IL——±1 µA 0<V
in <V
DDE4
Table 31. MLB Timing for MLB Speed 256 Fs or 512 Fs
Spec Parameter Symbol Min Typ Max Unit Comments
1 MLBCLK Operating Frequency1fmck 11.264
12.288
24.576
24.6272
25.600
MHz
256 Fs at 44.0 kHz
256 Fs at 48.0 kHz
512 Fs at 48.0 kHz
512 Fs at 48.1 kHz
512 Fs PLL unlocked
2 MLBCLK rise time tmckr —— 3nsV
IL to VIH
3 MLBCLK fall time tmckf —— 3nsV
IH to VIL
4 MLBCLK cycle time tmckc —81
40 —ns256Fs
512 Fs
5 MLBCLK low time tmckl 31.5
30 37
35.5 —ns256Fs
256 Fs PLL unlocked
14.5
14 17
16.5 —ns512Fs
512 Fs PLL unlocked
6 MLBCLK high time tmckh 31.5
30 38
36.5 ns 256xFs
256 Fs PLL unlocked
14.5
14 17
16.5 —ns512Fs
512 Fs PLL unlocked
7 MLBCLK pulse width variation2tmpwv 2 ns p-p
8 MLBSIG/MLBDAT input valid to
MLBCLK falling tdsmcf 1—ns
9 MLBSIG/MLBDAT input hold from
MLBCLK low tdhmcf 0—ns
MPC5668x Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor56
10 MLBSIG/MLBDAT output high
impedance from MLBCLK low tmcfdz 0—t
mckl ns
11 Bus Hold time3tmdzh 4—ns
12 MLBSIG/MLBDAT output valid from
MLBCLK rising tmcrdv —— 8ns
Ground = 0.0V
Load Capacitance = 60 pF, SIU_PCR144–SIU_PC R146[DSC] = 0b11.
MLB speed of 256 Fs or 512 Fs (Fs = 48 kHz)
Unless otherwise noted, all timing parameters are specified from the valid v oltage threshold in Table 30.
1The Controller can shut off MLBCLK to place MLB in a low-power state.
2Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (ns p-p).
3The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit f or this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
Table 32. MLB Timing for MLB Speed 1024 Fs
Spec Parameter Symbol Min Typ Max Unit Comments
1 MLBCLK Operating Frequency1fmck 45.056
49.152
49.2544
51.200 MHz
1024 Fs at 44.0 kHz
1024 Fs at 48.0 kHz
1024 Fs at 48.1 kHz
1024 Fs PLL unlocked
2 MLBCLK rise time tmckr —— 1nsV
IL to VIH
3 MLBCLK fall time tmckf —— 1nsV
IH to VIL
4 MLBCLK cycle time tmckc 20.3 ns VIL to VIH
5 MLBCLK low time tmckl 6.5
6.1 7.7
7.3 —ns1024Fs
PLL unlocked
6 MLBCLK high time tmckh 9.7
9.3 10.6
10.2 —ns1024Fs
PLL unclocked
7 MLBCLK pulse width variation2tmpwv 0.7 ns p-p
8 MLBSIG/MLBDAT input valid to
MLBCLK falling tdsmcf 1—ns
9 MLBSIG/MLBDAT input hold from
MLBCLK low tdhmcf 0—ns
10 MLBSIG/MLBDAT output high
impedance from MLBCLK low tmcfdz 0—t
mckl ns
11 Bus Hold time3tmdzh 2—ns
12 MLBSIG/MLBDAT output valid from
MLBCLK rising tmcrdv —— 7ns
Ground = 0.0V
Load Capacitance = 40 pF, SIU_PCR144–SIU_PC R146[DSC] = 0b00.
MLB speed = 1024Fs (Fs = 48 kHz)
Unless otherwise noted, timing parameters are spec ified from the valid voltage threshold in Table 30.
Table 31. MLB Timing for MLB Speed 256 Fs or 512 Fs (contin ued)
Spec Parameter Symbol Min Typ Max Unit Comments
Electrical Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 57
Figure 25. Media Local Bus (MLB) Timing
4.14.8 Fast Ethernet Interface
MII signals use CMOS signal levels compatible with devices operating at either 5.0 V or 3.3 V. Signals are not TTL compatible.
They follow the CMOS electrical characteristics.
4.14.8.1 MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. In addition, the system clock frequency must exceed four times the RX_CLK frequency.
1The Controller can shut off MLBCLK to place MLB in a low-power state.
2Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (ns p-p).
3The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit f or this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
Table 33. MII Receive Signal Timing
Spec Characteristic Min Max Unit
M1 RXD[3:0], RX_DV, RX_ER to RX_CLK setup 5 ns
M2 RX_CLK to RXD[3:0], RX_DV, RX_ER hold 5 ns
M3 RX_CLK pulse width high 35% 65% RX_CLK period
M4 RX_CLK pulse width low 35% 65% RX_CLK period
MLBCLK
MLBSIG/
263
5
11
MLBDAT
(output)
10
4
valid data
valid data
MLBSIG/
MLBDAT
(input)
9
8
12
MPC5668x Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor58
Figure 26. MII Receive Signal Timing Diagram
4.14.8.2 MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. In addition, the system clock frequency must exceed four times the TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of
TX_CLK, and the timing is the same in either case. This options allo ws the use of non-compliant MII PHYs.
Refer to the Ethernet chapter for details of this option and how to enable it.
Figure 27. MII Transmit Signal Timing Diagram
Table 34. MII Transmit Signal Timing1
1Output pads configured with SRC = 0b11.
Spec Characteristic Min Max Unit
M5 TX_CLK to TXD[3:0], TX_EN, TX_ER invalid 5 ns
M6 TX_CLK to TXD[3:0], TX_EN, TX_ER valid 25 ns
M7 TX_CLK pulse width high 35% 65% TX_CLK period
M8 TX_CLK pulse width low 35% 65% TX_CLK period
M1 M2
RX_CLK (input)
RXD[3:0] (inputs)
RX_DV
RX_ER
M3
M4
M6
TX_CLK (input)
TXD[3:0] (outputs)
TX_EN
TX_ER
M5
M7
M8
Electrical Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 59
4.14.8.3 MII Async Inputs Signal Timing (CRS and COL)
Figure 28. MII Async Inputs Timing Diagram
4.14.8.4 MII Serial Management Channel Timing (MDIO and MDC)
The FEC functions correctly with a maximum MDC frequen cy of 2.5 MHz.
Table 35. MII Async Inputs Signal Timing1
1Output pads configured with SRC = 0b11.
Spec Characteristic Min Max Unit
M9 CRS, COL minimum pulse width 1.5 TX_CLK period
Table 36. MII Serial Management Channel Timing1
1Output pads configured with SRC = 0b11.
Spec Characteristic Min Max Unit
M10 MDC falling edge to MDIO output invalid (minimum propagation delay) 0 ns
M11 MDC falling edge to MDIO output valid (max prop delay) 25 ns
M12 MDIO (input) to MDC rising edge setup 10 ns
M13 MDIO (input) to MDC rising edge hold 0 ns
M14 MDC pulse width high 40% 60% MDC period
M15 MDC pulse width low 40% 60% MDC period
CRS, COL
M9
MPC5668x Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor60
Figure 29. MII Serial Management Channel Timing Diagram
M11
MDC (output)
MDIO (output)
M12 M13
MDIO (input)
M10
M14 M15
Package Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 61
5 Pac kage Characteristics
5.1 Package Mechanical Data
Figure 30. 208 MAPBGA Package Mechanical Drawing
MPC5668x Microcontroller Data Sheet, Rev. 6
Package Characteristics
Freescale Semiconductor62
Figure 31. 208 MAPBGA Package Detail
Package Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 63
Figure 32. 256 MAPBGA Package Mechanical Drawing
MPC5668x Microcontroller Data Sheet, Rev. 6
Package Characteristics
Freescale Semiconductor64
Figure 33. 256 MAPBGA Package Detail
Revision History
MPC5668x Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor 65
6 Re vision History
Table 37 describes the changes made to this docum ent between revisions.
Table 37. Revision History
Revision Date Description
0 April 2008 Preliminary release.
1 June 2008 Initial release: Advance Information.
2 Jan 2009 Release: Advance Information.
3 September 2009 Release: Advance Information, interim updates.
4 January 2011 Release: Technical Data, interim updates.
5 January 2011 Release: Technical Data, interim updates.
6 March 2011 Release: Technical Data, interim updates.
Document Number : MPC5668X
Rev. 6
2010, 2011
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