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Product Specification 1-800-255-7778
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All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
XQ4000X Series Features
• Certified to MIL-PRF-38535 Appendix A QML
(Qualified Manufacturer List ing)
• Ceramic and plastic packages
• Also av ailable under the foll owing standard microcircuit
drawings (SMD)
- X Q4013 XL 596 2-98513
- X Q4036 XL 596 2-98510
- X Q4062 XL 596 2-98511
- X Q4085 XL 596 2-99575
• For more information contact the Defense Suppl y
Center Columb us (DSCC)
http://www.dscc.dla.mis/v/va/smd/smdsrch.html
• Available in -3 speed
• System feat ured Field-Programmable Gate Arra ys
- SelectRAM™ memory: on-chip ultra-f ast RAM with
·synchronous w rite option
·dual-port RAM option
- A bundant flip-fl ops
- Flexible function generators
- Dedicat ed high -speed carr y logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- E ight global low-skew clo ck or signal distri bution
networks
•System performance beyond 50 MHz
•Flexible ar ray arch itec tur e
•Low power segm ented routing arch itecture
•Systems-or iented features
- IEEE 1 149 .1-co mp a tible boundary scan logic
support
- Individual ly programmable output slew rate
- P rogrammable input pull-up or pull -down resistors
- 12 mA sink current per XQ4000XL output
•Configured by loading binary file
- Unlimited reprogramm ability
•Readback capability
- Program verification
- Internal node observability
•Development system runs on most common computer
platforms
- I nterfaces to popular de sign environments
- F ully autom atic mapping, placement and routi ng
- I nteractive design editor for d esign optim ization
•Highest capacity—over 180,000 usable gates
•Addi tional routing over XQ4000E
- A lmos t twice the routing capacity for high-density
designs
•Buffered Inte rcon nect for maximum speed
•New latch capability in conf igurable logic blocks
•Improved VersaRing™ I/O interconnect for better Fix ed
pinout flexi bility
- Virtually unlimited number of clock signals
•Optional multiplexer or 2-input func tion generator on
device outputs
•5V tolerant I/Os
•0.35 µm SRAM process
Introduction
The QPRO™ XQ4000XL Series high-performance,
high-capacity Field Programmable Gate Arrays (FPGAs)
provide the ben efits of custom CMOS VLSI, while avoidi ng
the initial cost, long development cycle, and inherent risk of
a convention al masked gate array.
The result of thirteen y ears of F PGA design experience and
feedbac k from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased speed,
abundant routing resources, and new, sophisticated
soft-ware to achieve fully automated implementation of
complex, high-density, high-performance designs.
Refer to the comple te Commercial X C4000XL Se ries Field
Programmable Gate Arrays Data Sheet for more informa-
tion on device architecture and t imi ng, and the latest Xilinx
databook for package pinouts other than the CB228
(included in this data sheet). (Pinouts for XQ4000XL device
are identical to XC4000X L.)
0QPRO XQ4000XL Series QML
High-R e liability FPGAs
DS029 (v1.3) June 25, 2000 02P rod uc t Sp ec if i c ation
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Table 1: XQ4000XL Series High Reliability Field Progammable Gate Arra ys
Device Logic
Cells
Max
Logic
Gates
(No
RAM)(1)
Max.
RAM
Bits (No
Logic)
Typical Gate
Range
(Logic and
RAM)(1) CLB
Matrix Total
CLBs
Number
of
Flip-Flops
Max.
User
I/O Packages
XQ 4013X L 2432 13,000 1 8,43 2 10,000-30,000 24x24 576 1,536 192 PG223, CB228,
PQ240, BG256
XQ 4036X L 3078 36,000 4 1,47 2 22,000-65,000 36x36 1,296 3,168 288 PG411, CB228,
HQ240, BG352
XQ 4062X L 5472 62,000 7 3,72 8 40,000-13 0,00 0 48x48 2,304 5,376 384 PG475, CB228,
HQ240, BG432
XQ 4085X L 7448 85,000 100,352 55,000-180,000 56x56 3,136 7,168 448 P G47 5, CB228,
HQ240, BG432
Notes:
1. Maxim um values of typi cal gate ra nge includes 20% to 30% of CLBs used as RAM.
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Product Specification 1-800-255-7778
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XQ4000XL Switching Characteristics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or
devicefamilies. Values are subject to change. Use as estimates, not for prod uc tion.
Preliminary: Based on preliminary characterization. Further changes are not ex pected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.
Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are
deriv ed from measuring internal test patterns. All specifications are representativ e of worst-case supply voltage and junction
temperature conditions.
All specific ations subject to change without notice.
Ad d itio nal Specif icati ons
Except for pin-to-pin input and output parameters, the a.c.
parameter delay specifications included in this document
are deriv ed from measuring internal test patterns. All speci-
fications are representative of worst-case supply voltage
and junction temperature conditions. The parameters
included are co mmon to popula r designs and typical appli-
cations. For design considerations requiring more detailed
timing information, see the appropriate family AC supple-
ments available on the Xilinx web site at:
http://www.xilinx.com/partinfo/databook.htm.
Ab solu te Maxim u m Rati ng s(1)
Recommended Operating Conditions(1)
Symbol Description Units
VCC Supply voltage relative to GND –0.5 to 4.0 V
VIN Input voltage relative to GND(2) –0.5 to 5.5 V
VTS Voltage applied to High-Z output(2) –0.5 to 5.5 V
VCCt Longest supply voltage rise time from 1V to 3V 50 ms
TSTG Storage temperature (ambie nt) –65 to +150 °C
TSOL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 °C
TJJunct ion temperature Ceramic package +150 °C
Plastic package +125 °C
Notes:
1. Stresses beyond those l isted under Abs olute Maximum Ratings may cause permanent damage to the device. T hese are stress
ratings onl y, and functional operation of the devi ce at these or any other conditions bey ond those list ed under Operating Conditions
is not imp lied. Exposure to Absolute Maxim um Ratings conditions for extended periods of time may affec t device reliab il ity.
2. Maxim um DC overshoot or unders hoot above VCC or belo w GND must be li m it ed to either 0.5V or 10 mA, whichever is easi er to
achieve. During t ransitions, the dev ice pins ma y undershoot to –2.0 V or ov ershoo t to VCC + 2.0V, provided this over- or undershoot
lasts less than 10 ns and with the forcing current being limited to 200 mA.
Symbol Description Min Max Units
VCC Suppl y voltage relative to GND, TJ = –55°C to +125°CPlastic 3.0 3.6 V
Suppl y voltage relative to GND, TC = –55°C to +125°C Ceramic 3.0 3.6 V
VIH High-level input voltage(2) 50% of VCC 5.5 V
VIL Low-level input voltage 0 30% of VCC V
TIN Input signal transition time - 250 ns
Notes:
1. At junct ion temperatures abo ve those listed as Operating Condi tions, all dela y parameters increa se by 0.35% per °C.
2. Input and output measurement threshold is ~50% of VCC.
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XQ4000XL DC Characteristics Over Recommended Operating Conditions
Power-On Power Supply Requirements
Xilinx FPGAs require a minimum rated power supply current
capacity to insure proper initialization, and the power supply
ramp-up time does affect the current required. A fast
ramp-up time requires more current than a slow ramp-up
time. The slowest ramp-up time is 50 ms. Current capacity
is not specified for a ramp-up time faster than 2 ms. The cur-
rent capacity varies linealy with ramp-up time, e.g., an
XQ4036XL with a ramp-up time of 25 ms would require a
capacity predicted by the point on the straight line drawn
from 1A at 120 µs to 500 mA at 50 ms at the 25 ms time
mark. This point is a pproximately 750 m A .
Symbol Description Min Max Units
VOH High-le vel output voltage at IOH = –4 mA, VCC min (LVTTL) 2.4 - V
High-level output voltage at IOH = –500 µA, (LVCMOS) 90% VCC -V
VOL Low-level output voltage at IOL = 12 mA, VCC min (LVTTL)(1) -0.4V
Low-l evel output voltage at IOL = 1500 µA, (LVCMOS) - 10% VCC V
VDR Data retention supply voltage (below which configuration data may be lost) 2.5 - V
ICCO Quiescent FP GA su pply curren t(2) -5mA
ILInput or outpu t leakage current –10 +10 µA
CIN Input capacitance (sampl e teste d) BGA, PQ, HQ, packages - 10 pF
PGA packages - 16 pF
IRPU Pad pull-up (when selected) at VIN = 0V (sample tested) 0.02 0.25 mA
IRPD Pad pull-down (when selected) at VIN = 3.6V (sample tested) 0.02 0.15 mA
IRLL Horizontal longline pull-up (when selected) at log ic Low 0.3 2.0 mA
Notes:
1. With up to 64 pi ns simultaneously sinking 12 mA.
2. With no output current l oads, no acti ve input or Longline pull-up resi stors, all I/O pi ns in a High-Z stat e and floating.
Product Descript io n
Ra m p-up Time
Fast (1 20 µs) Slow (50 ms)
XQ4013 - 36XL Minimum required current supply 1A 500 mA
XC4062XL Minimum required current supply 2A 500 mA
XC4085XL(1) M inimum required curre nt supply 2A(1) 500 mA
Notes:
1. The XC4085XL fast r am p-up time is 5 ms.
2. Devices are guaranteed to initialize properly with the minimum current listed above. A larger capacity power supply may result in a
la rg er init ialization c u rrent.
3. This specification applies to Commercial and Industrial grade products only.
4. Ramp-up Time is mea sured from 0VDC to 3.6VDC. Peak current required lasts less than 3 ms, and occurs near the internal power
on reset threshold v oltage. Afte r initialization and before configur ati on, ICC max is less t han 10 m A.
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Product Specification 1-800-255-7778
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XQ4000XL A C Switching Characteristic
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
der ived from m easuring i nter n al tes t patter ns. Listed bel ow
are representative values where one global clock input
drives one vertical clock line in each accessible c olumn, and
where all access ible I OB and CLB fl ip-fl ops are clocked by
the global clock net.
When few er vertical clock lines are connected, the clock dis-
tribution is faster ; when mul tiple clock lines per column are
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Dev elopment System) and bac k-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing paramete rs assum e worst-ca se operating conditions
(supply voltage and jun ction temperature)
Global Buffer Switching Characteristics
Global Early BUFGEs 1, 2, 5, and 6 to IOB Clock Characteristics
Global Early BUFGEs 3, 4, 7, and 8 to IOB Clock Characteristics
Symbol Description Device All
Min
-3 -1
UnitsMax Max
TGLS De lay from pad through Global Low Skew buffer, to any
cl ock K XQ4013XL 0.6 3.6 - ns
XQ4036XL 1.1 4.8 - ns
XQ4062XL 1.4 6.3 - ns
XQ4085XL 1.6 - 5.7 ns
Symbol Description Device All
Min
-3 -1
UnitsMax Max
TGE Delay fr om pad through Gl obal Early buffer, to any IOB
clock. Values are for BUFGEs 1, 2, 5 and 6. XQ4013XL 0.4 2.4 - ns
XQ4036XL 0.3 3.1 - ns
XQ4062XL 0.3 4.9 - ns
XQ4085XL 0.4 - 4.7 ns
Symbol Description Device All
Min
-3 -1
UnitsMax Max
TGE Delay fr om pad through Gl obal Early buffer, to any IOB
clock. Values are for BUFGEs 3, 4, 7 and 8. XQ4013XL 0.7 2.4 - ns
XQ4036XL 0.9 4.7 - ns
XQ4062XL 1.2 5.9 - ns
XQ4085XL 1.3 - 5.5 ns
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XQ4000XL CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
der ived from m easuring i nter n al tes t patter ns. Listed bel ow
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment S y stem) and back-ann otated to th e simu lation n etlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000XL devices and expressed in nanos ec-
onds unless otherwise noted.
CLB Switching Characteristics
Symbol Description
-3 -1
UnitsMin Max Min Max
Combinatorial Delays
TILO F/G inp uts to X/Y outputs - 1 .6 - 1.3 ns
TIHO F/G in puts vi a H ’ to X/Y outp uts - 2.7 - 2.2 ns
TITO F/G inp uts via transparent latch to Q outputs - 2 .9 - 2.2 ns
THH0O C inputs via SR/H0 via H to X/Y outputs - 2.5 - 2.0 ns
THH1O C inputs via H1 via H to X/Y outputs - 2 .4 - 1.9 ns
THH2O C inputs via DIN/H2 via H to X/Y outputs - 2 .5 - 2.0 ns
TCBYP C inputs via EC, DIN/H2 to YQ, XQ output (byp ass) - 1 .5 - 1.1 ns
CLB Fast C a rr y Logic
TOPCY Operand inputs (F1, F2, G1, G4) to COUT -2.7-2.0ns
TASCY Add/subtract input (F3) to COUT -3.3-2.5ns
TINCY Initialization inputs (F1, F3) to COUT -2.0-1.5ns
TSUM CIN through function generators to X/Y outputs - 2.8 - 2.4 ns
TBYP CIN to C OUT, bypass function generators - 0.26 - 0.20 ns
TNET Carry net delay, COUT to CIN - 0.32 - 0.25 ns
Sequential Delays
TCKO Clock K to flip-flop outputs Q - 2.1 - 1.6 ns
TCKLO Clock K to latch outputs Q - 2.1 - 1.6 ns
Setup Time Before C lock K
TICK F/G inputs 1.1 - 0.9 - ns
TIHCK F/G i n pu ts via H 2.2 - 1. 7 - ns
THH0CK C inputs via H0 through H 2.0 - 1.6 - ns
THH1CK C inputs via H1 through H 1.9 - 1.4 - ns
THH2CK C inputs via H2 through H 2.0 - 1.6 - ns
TDICK C inputs via DIN 0.9 - 0.7 - ns
TECCK C inputs via EC 1.0 - 0.8 - ns
TRCK C inputs via S/R, going Low (inactive) 0.6 - 0.5 - ns
TCCK CIN input via F/G 2.3 - 1.9 - ns
TCHCK CIN input via F/G and H 3.4 - 2.7 - ns
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Hold Time After Clock K
TCKI F/ G in puts 0 - 0 - ns
TCKIH F/ G inputs via H 0 - 0 - ns
TCKHH0 C inputs via SR/H0 through H 0 - 0 - ns
TCKHH1 C inputs via H1 through H 0 - 0 - ns
TCKHH2 C inputs via DIN/ H2 th rough H 0 - 0 - ns
TCKDI C inputs via DIN/H2 0 - 0 - ns
TCKEC C inputs via EC 0 - 0 - ns
TCKR C inputs via SR, going Low (inactive) 0 - 0 - ns
Clock
TCH Clock High time 3.0 - 2.5 - ns
TCL Clock Low time 3.0 - 2.5 - ns
Set/Reset Direct
TRPW Wi dth (High) 3.0 - 2.5 - ns
TRIO Delay from C in put s via S/R, go ing High to Q - 3 .7 - 2.8 ns
Global Set/Reset
TMRW Minimum GSR pulse width - 19.8 - 15.0 ns
TMRQ Delay from GSR input to any Q See page 17 for TRRI val ues per device.
FTOG To ggle frequency (MHz) (for export control) - 166 - 20 0 MHz
CLB Switching Characteristics (Continued)
Symbol Description
-3 -1
UnitsMin Max Min Max
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XQ4000XL RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
der ived from m easuring i nter n al tes t patter ns. Listed bel ow
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment S y stem) and back-ann otated to th e simu lation n etlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ 4000X L devices an d are expressed in n ano-
second s unles s otherwise noted.
Single-Port RAM Synchronous (Edge-Tr iggered) Write Operation Characteristics
Symb ol Single Port RAM Size
-3 -1
UnitsMin Max Min Max
Write Operation
TWCS Address write cycle time (clock K period) 16x2 9.0 - 7.7 - ns
TWCTS 32x1 9.0 - 7.7 - ns
TWPS Clock K pulse width (active edge ) 16x2 4.5 - 3.9 - ns
TWPTS 32x1 4.5 - 3.9 - ns
TASS Addres s setup time before clock K 16x2 2.2 - 1.7 - ns
TASTS 32x1 2.2 - 1.7 - ns
TAHS Address hold time after clock K 16x2 0 - 0 - n s
TAHTS 32x1 0 - 0 - ns
TDSS DIN setup time before clock K 16x2 2.0 - 1.7 - ns
TDSTS 32x1 2.5 - 2.1 - ns
TDHS DIN hold time after clock K 16x2 0 - 0 - ns
TDHTS 32x1 0 - 0 - ns
TWSS WE setup time before clock K 16x2 2. 0 - 1.6 - ns
TWSTS 32x1 1.8 - 1.5 - ns
TWHS WE ho ld time after clock K 16x2 0 - 0 - ns
TWHTS 32x1 0 - 0 - ns
TWOS Data valid after cloc k K 16x2 - 6.8 - 5.8 ns
TWOTS 32x1 - 8.1 - 6.9 ns
Read Operation
TRC Address read cycle time 16x2 4. 5 - 2.6 - ns
TRCT 32x1 6.5 - 3.8 - ns
TILO Data val id after address change (no Write Enable) 16x2 - 1.6 - 1.3 ns
TIHO 32x1 - 2.7 - 2.2 ns
TICK Address setup time before clock K 16x2 1.1 - 0.9 - ns
TIHCK 32x1 2.2 - 1.7 - ns
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Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
Symbol Dual Port RAM Size(1)
-3 -1
UnitsMin Max Min Max
Write Operation
TWCDS Address write cycle time (clock K period) 16x1 9.0 7.7 ns
TWPDS Clock K pul se width (active edge) 16x1 4.5 - 3.9 - n s
TASDS A ddress setup time before clock K 16x1 2.5 - 1.7 - ns
TAHDS Address hold time after clock K 16x1 0 - 0 - ns
TDSDS DIN setup time before clock K 16x1 2.5 - 2.0 - ns
TDHDS DIN hold time after clock K 16x1 0 - 0 - ns
TWSDS WE setup time before clock K 16x1 1.8 - 1.6 - ns
TWHDS WE hold time after clock K 16x1 0 - 0 - n s
TWODS Data val id after clock K 16x1 - 7.8 - 6.7 ns
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XQ4000XL CLB Single-Po rt RAM Synchron ous (Edge-Triggered) Write Timing
XQ4000XL CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing
DS029_01_011300
WCLK (K)
WE
ADDRESS
DATA IN
D
ATA OUT
OLD NEW
T
DSS
T
DHS
T
ASS
T
AHS
T
WSS
T
WPS
T
WHS
T
WOS
T
ILO
T
ILO
DS029_02_011300
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD NEW
T
DSDS
T
DHDS
T
ASDS
T
AHDS
T
WSS
T
WPDS
T
WHS
T
WODS
T
ILO
T
ILO
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XQ4000XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and inter nal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
struct ure, us e the valu es provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the sim ulation netlist. These path dela ys ,
provided as a guideline, hav e been extracted from the static
timing analyzer report. Values are expressed in nanosec-
onds unless otherwise noted.
Output Flip-Flop, Clock to Out(1,2,3)
Output Flip-Flop, Clock to Out, BUFGEs 1, 2, 5, and 6
Symbol Description Device All
Min
-3 -1
UnitsMax Max
TICKOF G lobal low skew clock to ou tput using OF F(4) XQ4013XL 1.5 8.6 - ns
XQ4036XL 2.0 9.8 - ns
XQ4062XL 2.3 11.3 - ns
XQ4085XL 2.5 - 9.5 ns
TSLOW For output SLOW option add All Devi ces 3.0 3.0 3.0 ns
Notes:
1. Listed above are representative values where one global clock input drives one ver tical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are cl ock ed by the global clock net.
2. Cloc k-to- out m ini mum de la y i s measur ed with the fastest r oute and the l ightes t lo ad, Cl oc k-to- out max im um del ay i s measur ed using
the farthes t distance and a reference load of one clock pin (IK or OK) per IOB as wel l as driv ing all accessibl e CLB flip-flops. For
design s with a small er numbe r of cloc k loads, the pad-t o-IOB cloc k pin dela y as determined by the static timing analyzer (TRCE) c an
be added to the A C parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for cl ock ed outputs f or FAST mode
configurations.
3. Output timing is measured a t ~50% VCC threshol d with 50 pF external cap acitiv e load.
4. OFF = Output Flip-Flop
Symbol Description Device All
Min
-3 -1
UnitsMax Max
TICKEOF Global early clock to output using OFF
Valu es are for BUFGEs 1, 2, 5, an d 6. XQ4013XL 1.3 7.4 - ns
XQ4036XL 1.2 8.1 - ns
XQ4062XL 1.2 9.9 - ns
XQ4085XL 1.3 - 8.5 ns
Notes:
1. Cloc k-to- out m ini mum de la y i s measur ed with the fastest r oute and the l ightes t lo ad, Cl oc k-to- out max im um del ay i s measur ed using
the farthes t distance and a reference load of one clock pin (IK or OK) per IOB as wel l as driv ing all accessibl e CLB flip-flops. For
design s with a small er numbe r of cloc k loads, the pad-t o-IOB cloc k pin dela y as determined by the static timing analyzer (TRCE) c an
be added to the A C parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for cl ock ed outputs f or FAST mode
configurations.
2. Output timing is measured a t ~50% VCC threshol d with 50 pF external cap acitiv e load.
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Output Flip-Flop, Clock to Out, BUFGEs 3, 4, 7, and 8
Capacitive Load Factor
Figure 1 shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the specified
output delay if the load capacitance is different than 50 pF.
For example, if the actual load capacitance is 120 pF, add
2.5 ns to the specified delay. If the load capacitance is
20 pF, subtract 0.8 ns from the specified output dela y.
Figure 1 is usable ov er the specified operating conditions of
voltage and temperature and is independent of the output
slew rate control.
Symbol Description Device All
Min
-3 -1
UnitsMax Max
TICKEOF Global early clock to output using OFF
Valu es are for BUFGEs 3, 4, 7, an d 8. XQ4013XL 1.8 8.8 - ns
XQ4036XL 1.8 9.7 - ns
XQ4062XL 2.0 10.9 - ns
XQ4085XL 2.2 - 9.3 ns
Notes:
1. Cloc k-to- out m ini mum de la y i s measur ed with the fastest r oute and the l ightes t lo ad, Cl oc k-to- out max im um del ay i s measur ed using
the farthes t distance and a reference load of one clock pin (IK or OK) per IOB as wel l as driv ing all accessibl e CLB flip-flops. For
design s with a small er numbe r of cloc k loads, the pad-t o-IOB cloc k pin dela y as determined by the static timing analyzer (TRCE) c an
be added to the A C parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for cl ock ed outputs f or FAST mode
configurations.
2. Output timing is measured a t ~50% VCC threshol d with 50 pF external cap acitiv e load.
Figure 1: Delay Factor at Various C apacitive Load s
DS029_03_011300
-2 020406080
Capacitance (pF)
Delta Delay (ns)
100 120 140
-1
0
1
2
3
QPRO XQ4000X L Series QML High-Reliab ility FPGAs
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Product Specification 1-800-255-7778
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XQ4000XL Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and inter nal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
struct ure, us e the valu es provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the sim ulation netlist. These path dela ys ,
provided as a guideline, hav e been extracted from the static
timing analyzer report. Values are expressed in nanosec-
onds unless otherwise noted.
Global Low Skew Clock, Input Setup and Hold Times(1,2)
Symbol Description Device(1)
-3 -1
UnitsMin Min
No Delay
TPSN/TPHN Global early clock and IFF(3)
Global early clock and FCL(4) X Q4013 XL 1. 2 / 3.2 - ns
XQ4036 XL 1. 2 / 5.5 - ns
XQ4062 XL 1. 2 / 7.0 - ns
XQ4085 XL - 0.9 / 7.1 ns
Partial Delay
TPSP/TPHP Global early clock and IFF(3)
Global early clock and FCL(4) X Q4013 XL 6. 1 / 0.0 - ns
XQ4036 XL 6. 4 / 1.0 - ns
XQ4062 XL 6. 7 / 1.2 - ns
XQ4085 XL - 9.8 / 1.2 ns
Full Delay
TPSD/TPHD Global early clock and IFF(3) XQ4013XL 6. 4 / 0.0 - ns
XQ4036 XL 6. 6 / 0.0 - ns
XQ4062 XL 6. 8 / 0.0 - ns
XQ4085 XL - 9.6 / 0.0 ns
Notes:
1. The XQ4013 XL, XQ4036XL, and XQ4062XL hav e significantly faster partial and full delay setup times than other devices.
2. Input setup t ime is measur ed with t he f ast est r oute and the lightest load. I nput hol d ti me is m easured using t he f urthest dist ance and
a reference load of one clo ck pin per IOB as well as driving al l accessibl e CLB fli p-flops . For d esigns with a smal ler number of cl ock
loads, the pad- to-IOB cloc k pin delay as determined by the static ti m ing analyzer (TRCE) can be used as a worst-case pin-to-pin
no-delay input hold specification.
3. IFF = Input Flip-Flop or Latch
4. FCL = Fast Capture Latch
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Global Early Clock BUFEs 1, 2, 5, and 6 Setup and Hold for IFF and FCL(1,2)
Symbo l Description D evice
-3 -1
Min Min
No Delay
TPSEN/TPHEN
TPFSEN/TPFHEN
Global early clock and IFF(3)
Global early clock and FCL(4) XQ4013XL 1.2 / 4.7 -
XQ4036XL 1.2 / 6.7 -
XQ4062XL 1.2 / 8.4 -
XQ 4085X L - 0.9 / 6.6
Partial Delay
TPSEPN/TPHEP
TPFSEP/TPFHEP
Global early clock and IFF(3)
Global early clock and FCL(4) XQ4013XL 6.4 / 0.0 -
XQ4036XL 7.0 / 0.8 -
XQ4062XL 9.0 / 0.8 -
XQ4085XL - 11.0 / 0.0
Full Delay
TPSEPD/TPHED Global early clock and IFF(3) XQ 4013XL 12.0 / 0.0 -
XQ 4036X L 13.8 / 0.0 -
XQ 4062X L 13.1 / 0.0 -
XQ4085XL - 13.6 / 0.0
Notes:
1. The XQ4013 XL, XQ4036XL, and XQ4062XL hav e significantly faster partial and full delay setup times than other devices.
2. Input setup t ime is measur ed with t he f ast est r oute and the lightest load. I nput hol d ti me is m easured using t he f urthest dist ance and
a reference load of one clo ck pin per IOB as well as driving al l accessibl e CLB fli p-flops . For d esigns with a smal ler number of cl ock
loads, the pad- to-IOB cloc k pin delay as determined by the static ti m ing analyzer (TRCE) can be used as a worst-case pin-to-pin
no-delay input hold specification.
3. IFF = Input Flip-Flop or Latch
4. FCL = Fast Capture Latch
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Product Specification 1-800-255-7778
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Global Early Clock BUFEs 3, 4, 7, and 8 Setup and Hold for IFF and FCL(1,2)
Symbo l Description D evice
-3 -1
Min Min
No Delay
TPSEN/TPHEN
TPFSEN/TPFHEN
Global early clock and IFF(3)
Global early clock and FCL(4) XQ4013XL 1.2 / 4.7 -
XQ4036XL 1.2 / 6.7 -
XQ4062XL 1.2 / 8.4 -
XQ 4085X L - 0.9 / 6.6
Partial Delay
TPSEPN/TPHEP
TPFSEP/TPFHEP
Global early clock and IFF(3)
Global early clock and FCL(4) XQ4013XL 5.4 / 0.0 -
XQ4036XL 6.4 / 0.8 -
XQ4062XL 8.4 / 1.5 -
XQ4085XL - 11.0 / 0.0
Full Delay
TPSEPD/TPHED Global early clock and IFF(3) XQ 4013XL 10.0 / 0.0 -
XQ 4036X L 12.2 / 0.0 -
XQ 4062X L 13.1 / 0.0 -
XQ4085XL - 13.6 / 0.0
Notes:
1. The XQ4013 XL, XQ4036XL, and XQ4062XL hav e significantly faster partial and full delay setup times than other devices.
2. Input setup t ime is measur ed with t he f ast est r oute and the lightest load. I nput hol d ti me is m easured using t he f urthest dist ance and
a reference load of one clo ck pin per IOB as well as driving al l accessibl e CLB fli p-flops . For d esigns with a smal ler number of cl ock
loads, the pad- to-IOB cloc k pin delay as determined by the static ti m ing analyzer (TRCE) can be used as a worst-case pin-to-pin
no-delay input hold specification.
3. IFF = Input Flip-Flop or Latch
4. FCL = Fast Capture Latch
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XQ4000XL IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
der ived from m easuring i nter n al tes t patter ns. Listed bel ow
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment S y stem) and back-ann otated to th e simu lation n etlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature).
Symbol Description Device
-3 -1
UnitsMinMaxMinMax
Clocks
TECIK Clock enabl e (EC) to cloc k (IK) All device s 0.1 - 0 .1 - ns
TOKIK Delay from FCL enab le (OK) activ e edge to IFF
clock (IK) activ e edge All devices 2.2 - 1. 6 - ns
Setup Times
TPICK Pad to clock (IK), no delay A ll devices 1.7 - 1.3 - ns
TPICKF P ad to clock (I K), via transparent f ast capture latch,
no delay All device s 2.3 - 1.8 - ns
TPOCK P ad to fast capture latch enable (OK), no delay All devices 1.2 - 0.9 - ns
Hold Times
All Hold Times All devices 0 - 0 - ns
Global Set/Reset
TMRW Minimum GSR pulse width A ll devices - 19. 8 - 15. 0 ns
TRRI Delay from GSR input to any Q(2) XQ4013XL - 15.9 - - ns
XQ4036XL - 22.5 - - ns
XQ4062XL - 29.1 - - ns
XQ4085XL - - - 26.0 ns
Propagation Delays
TPID Pad to I1, I2 All devices - 1.6 - 1.7 ns
TPLI Pad to I1, I2 via transparent input latch, no delay All devices - 3.1 - 2.4 ns
TPFLI Pad t o I1, I2 via t ransparent FCL and input latch, no
delay All devices - 3.7 - 2.8 ns
TIKRI Clock (IK) to I1, I2 (flip-fl op) All devices - 1.7 - 1.3 ns
TIKLI Cloc k (IK) to I1, I2 (latch enable, active Low) All devices - 1.8 - 1.4 ns
TOKLI FCL enable (O K ) active e dge to I1, I2
(via tran sp arent standard input latch) All devices - 3.6 - 2.7 ns
Notes:
1. IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
2. Indi cates Minimum Am ount of Time t o Assure Valid Data.
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Product Specification 1-800-255-7778
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XQ40 00 XL IOB Out put Sw itchin g Cha ract erist ic Gu ide lin es
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
der ived from m easuring i nter n al tes t patter ns. Listed bel ow
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment S y stem) and back-ann otated to th e simu lation n etlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). For Propagation
Delays, slew-rat e = fast unless otherwise noted. Values are
expressed in nanoseconds unles s otherwise noted.
Symbol Description
-3 -1
UnitsMin Max Min Max
Clocks
TCH Clock High 3.0 - 2.5 - ns
TCL Clock Low 3.0 - 2.5 - ns
Propagation D e lays
TOKPOF Clock (OK) to pad - 5.0 - 3.8 ns
TOPF O utp ut (O) to pad - 4.1 - 3.1 ns
TTSHZ High-Z to pad High-Z (slew-rate independent) - 4. 4 - 3 .0 ns
TTSONF High-Z to pad active and valid - 4.1 - 3.3 ns
TOFPF Output (O) to pad via fast output MUX - 5.5 - 4 .2 ns
TOKFPF Selec t (OK) to pad vi a f a st MUX - 5.1 - 3.9 ns
Setup and Hold Times
TOOK Output (O) to clock (OK) setup time 0.5 - 0.3 - ns
TOKO Output (O) to clock (OK) hold time 0 - 0 - ns
TECOK Cl ock Enable (EC) to clock (OK ) setup time 0 - 0 - ns
TOKEC Clock Enable (EC) to clock (OK ) hold time 0.3 - 0.1 - ns
Global Set/Reset
TMRW Minimum GSR pulse width 19.8 - 15.0 - ns
TRPO Delay from GSR input to any pad(2)
XQ4013XL - 20.5 - - ns
XQ4036XL - 27.1 - - ns
XQ4062XL - 33.7 - - ns
XQ4085XL - - 29.5 ns
Slew Rate Ad justment
TSLOW For output SLOW option add - 3.0 - 2.0 ns
Notes:
1. Output timing is measured a t ~50% VCC threshold, with 50 pF external capacitive loads.
2. Indi cates Minimum Am ount of Time t o Assure Valid Data.
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1-800-255-7778 Product Specification
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CB228 Pinouts
Table 2: CB228 Package Pinouts
Pin Name CB228
VTT
GND P1
BUFGP_TL_A16_GCK1_IO P2
A17_IO P3
IO P4
IO P5
TDI_IO P6
TCK_IO P7
IO P8
IO P9
IO P10
IO P11
IO P12
IO P13
GND P14
IO_FCLK1 P15
IO P16
TMS_IO P17
IO P18
IO P19
IO P20
IO P21
IO P22
IO P23
IO P24
IO P25
IO P26
GND P27
VCC P28
IO P29
IO P30
IO P31
IO P32
IO P33
IO P34
IO P35
IO P36
VCC P37
IO P38
IO P39
IO P40
IO_FCLK2 P41
GND P42
IO P43
IO P44
IO P45
IO P46
IO P47
IO P48
IO P49
IO P50
IO P51
IO P52
IO P53
BUFGS_BL_GCK2_IO P54
M1 P55
GND P56
M0 P57
VCC P58
M2 P59
BUFGP_BL_GCK3_IO P60
HDC_IO P61
IO P62
IO P63
IO P64
LDC_IO P65
IO P66
IO P67
IO P68
IO P69
IO P70
IO P71
GND P72
IO P73
IO P74
IO P75
IO P76
IO P77
IO P78
Table 2: CB228 Packag e Pinouts (Continued)
Pin Name CB228
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Product Specification 1-800-255-7778
R
IO P79
IO P80
IO P81
IO P82
IO P83
/ERR_INIT_IO P84
VCC P85
GND P86
IO P87
IO P88
IO P89
IO P90
IO P91
IO P92
IO P93
IO P94
VCC P95
IO P96
IO P97
IO P98
IO P99
GND P100
IO P101
IO P102
IO P103
IO P104
IO P105
IO P106
IO P107
IO P108
IO P109
IO P110
IO P111
BUFGS_BR_GCK4_IO P112
GND P113
DONE P114
VCC P115
/PROGRAM P116
D7_IO P117
BUFGP_BR_GCK5_IO P118
Table 2: CB228 Package Pinouts (Continued)
Pin Name CB228 IO P119
IO P120
IO P121
IO P122
D6_IO P123
IO P124
IO P125
IO P126
IO P127
IO P128
GND P129
IO P130
IO P131
IO_FCLK3 P132
IO P133
D5_IO P134
/CS0_IO P135
IO P136
IO P137
IO P138
IO P139
D4_IO P140
IO P141
VCC P142
GND P143
D3_IO P144
/RS_IO P145
IO P146
IO P147
IO P148
IO P149
D2_IO P150
IO P151
VCC P152
IO P153
IO_FCLK4 P154
IO P155
IO P156
GND P157
IO P158
Table 2: CB228 Packag e Pinouts (Continued)
Pin Name CB228
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IO P159
IO P160
IO P161
IO P162
IO P163
D1_IO P164
BUSY_/RDY_RCLK_IO P165
IO P166
IO P167
D0_DIN_IO P168
BUFGS_TR_GCK6_DOUT_IO P169
CCLK P170
VCC P171
TDO P172
GND P173
A0_/WS_IO P174
BUFGP_TR_GCK7_A1_IO P175
IO P176
IO P177
CSI_A2_IO P178
A3_IO P179
IO P180
IO P181
IO P182
IO P183
IO P184
IO P185
GND P186
IO P187
IO P188
IO P189
IO P190
VCC P191
A4_IO P192
A5_IO P193
IO P194
IO P195
A21_IO P196
A20_IO P197
A6_IO P198
Table 2: CB228 Package Pinouts (Continued)
Pin Name CB228 A7_IO P199
GND P200
VCC P201
A8_IO P202
A9_IO P203
A19_IO P204
A18_IO P205
IO P206
IO P207
A10_IO P208
A11_IO P209
VCC P210
IO P211
IO P212
IO P213
IO P214
GND P215
IO P216
IO P217
IO P218
IO P219
A12_IO P220
A13_IO P221
IO P222
IO P223
IO P224
IO P225
A14_IO P226
BUFGS_TL_GCK8_A15_IO P227
VCC P228
Table 2: CB228 Packag e Pinouts (Continued)
Pin Name CB228
QPRO XQ4000X L Series QML High-Reliab ility FPGAs
DS029 (v1.3) June 25, 2000 www.xilinx.com 21
Product Specification 1-800-255-7778
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Ordering Information
Revisio n Hist ory
The following table shows the revision histor y for this document
Dev ice Type
XQ4085XL
XQ4062XL
XQ4036XL
XQ4013XL Package Type
CB = Top Brazed Ceramic Quad Flat P ack
PG = Cer a mic P in Grid Ar ray
PQ/H Q = Plas tic Quad Flat Back
BG = Pla st ic Ball Grid Array
Tem peratu re R ange
M = Milit a ry C eram ic ( TC = –55oC to +125 oC)
N = Milit ary Plastic ( TJ = –55°C to +125°C)
Mil-PRF-38535
(QML) Processed
Num b e r of Pi ns
XQ 4062XL -3 PG 475 M
Example for QPRO™ m ilitary temp erature par t :
Speed Grade
-3
-1 (XQ4085 XL only)
Date Version Description
05/01/98 1.0 Original document release.
01/01/99 1.1 Addition of new packages, clarification of parameters.
02/09/00 1.2 Addition of XQ408 5X L-1 speed grade part .
06/25/00 1.3 Updated timin g specifications to match with commercial data sheet. Updated form at.
Device Type
XQ4 013X L = 98513
XQ4 036X L = 98510
XQ4 062X L = 98511
XQ4 085X L = 99575
Package T ype
X = Pin Grid
Y = Ceramic Q uad Fla t Pack (Bas e Mark )
Z = Ceramic Quad Flat Pa ck (Lid Mark)
T = Plastic Quad Flat Pa ck
U = Plas t ic Ball Gr id
Lea d Fi ni s h
C = Gold
B = Sold er
Generic Standard
Microcircuit Drawing (SMD)
Prefix
5962 98511 01 Q X C
Q = QML C ert if ied
N = QML Plastic (N - Grade)
Example for SMD part:
Speed Grade
01 = -3 for XQ4103XL/ 4036X L/4062XL
01 = -1 for XQ4085XL
