128K x 32 Synchronous-Pipelined Cache RAM
CY7C1339
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Ma y 8, 2000
Features
• Supports 100-MHz bus for Pentiumand Power PC™
operations with zer o w ait states
• Fully registered inputs and outputs for pipelined oper-
ation
• 128K by 32 com m on I/ O architecture
• 3 .3 V co re p ower s u pp ly
• 2.5V / 3.3V I/O operat ion
• Fast clock-to-output times
—3.5 ns (f or 166-MHz device)
—4.0 ns (f or 133-MHz device)
—5.5 ns (f or 100-MHz device)
• User-selectable burst counter supporti ng IntelPen-
tium interl eaved or linear burst sequences
• Sep arate processor and contr oller address strobes
• Synchronous self-timed writes
• Asy nchronous output enable
• JEDEC-standard 100 TQFP pinout
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1339 is a 3.3V, 128K by 32 synchr onous-pipelined
cache SRAM designed to support zero wait state secondar y
cache with minimal glue logic.
The CY7C1339 I/O pins can operate at eit her the 2.5V or the
3.3V level; the I/O pins are 3. 3V tolerant when VDDQ=2.5V.
All sync hronous i nputs pass through i nput regi ster s control led
by the risi ng edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 3.5 ns (166-MHz
device).
The CY7C1339 supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the P owerPC. The burst
sequence is selected through the MODE pin. Accesses can
be initiated by asserting either the Processor Address St robe
(ADSP) or the Controller Address Strobe (ADSC) at clock rise .
Address advancement through the burst sequence is con-
trolled by the ADV input. A 2-bit on-chip wraparound burst
counter captures the first address in a burst sequence and
automatically increments the address for the rest of the burst
access.
Byte write operations are qualified with the four Byte Write
Select (BW[3:0]) inputs. A G lobal Writ e Enable (GW) overrides
all b yte write inpu ts and writes data to all four b ytes. All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state con trol . In order to pro vide prop-
er data during depth expansion, OE is m asked duri ng the first
clock of a read c ycle when emergi ng from a deselect ed state.
Intel and Penti um are trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
CLK
ADV
ADSC
A[16:0]
GW
BWE
BW3
BW2
BW1
BW0
CE1
CE3
CE2
OE
ZZ
BURST
COUNTER
DQ[31:24]
BYTEWRITE
REGISTERS
ADDRESS
REGISTER
DQ
OUTPUT
REGISTERS INPUT
REGISTERS
128KX32
MEMORY
ARRAY
CLK CLK
Q0
Q1
Q
D
CE
CE
CLR
SLEEP
CONTROL
DQ[23:16]
BYTEWRITE
REGISTERS
D Q
DQ
DQ[15:8]
BYTEWRITE
REGISTERS
DQ[7:0]
BYTEWRITE
REGISTERS
DQ
ENABLE
REGISTER
DQ
CE
CLK
ENABLE DELAY
REGISTER
DQ
CLK
32 32
17
15
15
17
(A[1;0])2
MODE
ADSP
Logic Block Diagram
DQ[31:0]
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CY7C1339
2
Pin Configuration
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
A16
NC
DQ15
DQ14
VDDQ
VSSQ
DQ13
DQ12
DQ11
DQ10
VSSQ
VDDQ
DQ9
DQ8
VSS
NC
VDD
ZZ
DQ7
DQ6
VDDQ
VSSQ
DQ5
DQ4
DQ3
DQ2
VSSQ
VDDQ
DQ1
DQ0
NC
NC
DQ16
DQ17
VDDQ
VSSQ
DQ18
DQ19
DQ20
DQ21
VSSQ
VDDQ
DQ22
DQ23
NC
VDD
NC
VSS
DQ24
DQ25
VDDQ
VSSQ
DQ26
DQ27
DQ28
DQ29
VSSQ
VDDQ
DQ30
DQ31
NC
A6
A7
CE1
CE2
BW3
BW2
BW1
BW0
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
MODE
BYTE0
BYTE1
BYTE3
BYTE2
100
10
r
100-Pin TQ FP
CY7C1339
Select ion Guid e
7C1339-166 7C1339-133 7C1339-100
Maximum Access Time (ns) 3.5 4.0 5.5
Maxim um Operating Current (mA) Commercial 420 375 325
Maximum CMOS Standby Current (mA) Commercial 10 10 10
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CY7C1339
3
Pin Definitions
Pin Number Name I/O Description
50–44, 81,
82, 99, 100,
32–37
A[16:0] Input-
Synchronous Address Input s used to select one of the 64K address locations. Sampl ed at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, C E2, and CE3
are sampled active. A[1:0] feed the 2-bit counter.
96–93 BW[3:0] Input-
Synchronous Byte W rite Select Inputs, active LOW. Qualified with BWE to co n du c t byte wr ite s
to the SRAM. Sampl ed on the rising edge of CLK.
88 GW Input-
Synchronous Global Write Enabl e Input, acti ve LO W . When asserted LOW on the risi ng edge of
CLK, a global write is conducted (ALL byt es are written, regardless of the values
on BW[3:0] and BWE).
87 BWE Input-
Synchronous Byte Write Enable Input, act ive LOW. Sampled on the rising edge of CLK. This
signal must be asserted LO W to conduct a byt e write.
89 CLK Input-Clock Clock in put. Used to capture al l synchronous inpu ts to the de vice. Also used to
increment t he burst c ounter when ADV is asserted LOW, du ring a bu rst o peratio n.
98 CE1Input-
Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conj unction wit h CE2 and CE3 to select/deselect the de vice. ADSP is ignored if
CE1 is HIGH.
97 CE2Input-
Synchronous Chip Enable 2 Input, active HI GH. Sam pled on the rising edge of CLK. Used in
conj unction wit h CE1 and CE3 to select/deselect the device.
92 CE3Input-
Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conj unction wit h CE1 and CE2 to sele ct/desel ect the device .
86 OE Input-
Asynchronous Output Enable, asynchronous input, activ e LO W. Contr ols the direction of the I/O
pins. When LOW, the I/ O pins behave as outputs. W hen deserted HIGH, I/O pins
are t hree-st ated, and a ct as i nput dat a pins . OE is m ask ed during t he fi rst cl oc k of
a read cycle when emergin g fro m a dese lected state.
83 ADV Input-
Synchronous Adva nce I nput sig nal, sa mpled on the risi ng edge of CLK. When asserted, it auto-
mat ically incr em ents the address in a b urst cycle .
84 ADSP Input-
Synchronous Address Strobe from Proce ssor , sampled on the rising edge of CLK. When assert-
ed LOW , A[16:0] is captur ed in t he ad dress r egist ers. A[1:0] are also loaded i nto t he
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ASDP is ignored when CE1 is deserted HIGH.
85 ADSC Input-
Synchronous Address Strobe from Cont roll er , samp led on t he rising e dge of CLK. W hen assert-
ed LOW , A[16:0] is captur ed in t he ad dress r egist ers . A[1:0] are also loa ded int o the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
64 ZZ Input-
Asynchronous ZZ “sleep” Input . Thi s activ e HIGH input places the device in a non-time-critic al
“sleep” condi ti on with data integ rit y preserved. Leaving ZZ floating or NC will de-
fault the device into an active state. ZZ has an internal pull down.
29, 2 8, 25-22,
19, 18,13,12,
9–6, 3, 2, 79,
78, 75–72,
69, 68, 63, 62
59–56, 53, 52
DQ[31:0] I/O-
Synchronous Bidirectional Data I/O li nes. As input s, the y feed into an on-chip data regi ster that
is trigger ed b y the rising edge of CLK. As outp uts, they deliv er the data contai ned
in the memory location specif ied by A[16:0] during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE i s asserted
LOW , t he pins be hav e as outputs. When HIGH, DQ[31:0] are placed in a three-state
condition.
15, 41, 65, 91 VDD Power Supply P o wer suppl y i nputs to t he c ore of the de vice . Shou ld be conn ected t o 3.3V po wer
supply.
17, 40, 67, 90 VSS Ground G round for the core of the de vice. Should be connected to gr ound of the system.
4, 11, 20, 27,
54, 61, 70, 77 VDDQ I/O Power
Supply Power suppl y for the I/O ci rcuitry. Should be connected to a 3.3 V or 2.5V po wer
supply.
5, 10, 21, 26,
55, 60, 71, 76 VSSQ I/O Ground Ground for th e I/O circuitry. Should be connected to ground of the system.
31 MODE Input-
Static Selects burst order. Whe n ti ed to GND selects linear burst sequen ce. When tied
to VDDQ or l eft f loating selects interlea ved burst sequence. This is a strap pin an d
shoul d remai n static duri ng de vi ce opera tion. When lef t floati ng or NC , def au lts to
interleaved burst ord er. Mode pin has an internal pul l up.
1, 14, 16, 30,
38, 39, 42, 43,
51, 66, 80
NC -No Connects.
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CY7C1339
4
Introduction
Functional Overview
All synchrono us inp uts pass th rough inp ut regi sters con tr olle d
by the rising edge of the clock. All data outputs pass through
outpu t regist ers contr olled b y the rising ed ge of the clock. Max-
imum access delay from the clock rise (tCO) is 3.5 ns (166-MHz
device).
The CY7C133 9 supports secondary cache in sys tems util izin g
either a linear or interleaved bur st sequence. The i nterleaved
burst ord er supports Pentium and i486 processors. The linear
burst sequence is suited for processors that utilize a linear
burst sequence. The burst order i s user select able, and is de-
termined by sampl ing the MODE input. Accesses can be initi-
ated with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two- bit on-ch ip wrap around burst co unter captu res the first ad-
dress in a burst sequence and automatically increments the
address for the rest of t h e burst a cce ss.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[3:0]) input s. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self-timed wri te ci rcuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE ) provide for easy bank se-
lection and output three-state control. ADSP is ignor ed if CE1
is HIGH.
Singl e Read Accesses
This access is initiated when the fol lowing condi tions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE 2, CE3 ar e all ass erted acti ve, a nd (3) the write s ignals
(GW, B W E) are all deser ted HIGH . ADSP is i g nored if C E 1 is
HIGH. The address presented to the address inputs (A[16:0]) is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The cor-
responding data is allowed to propagate to the input of the
Output Regist ers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.5 ns (166-MHz device) if OE is active
LO W. The only e x ceptio n occurs when the SRAM is emerg ing
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once t he SRAM is deselect ed at cl ock ri se by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Singl e Writ e Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE1, CE 2, CE3 a re all a sserted act iv e. Th e addres s pr esente d
to A [16:0] is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BW E, and BW[3:0]) and ADV inputs are ig-
no red during this fi rst cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second cloc k rise , the
data presented t o the DQ[31:0] inputs is written into the corre-
sponding address location in the RAM core. If GW is HIGH,
then the write oper ation is contro ll ed by BW E and BW[3:0] sig-
nals. The CY7C1339 provides byte write capability that is de-
scribed in the Write Cycle Descriptions table. Asserting the
Byte Write Enable input (BWE) with the selected Byte Write
(BW[3:0]) input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1339 is a common I/O device, the Output
Enable (OE) must be deser ted HIGH before presenti ng data
to the DQ[31:0] inputs . Doing so wi ll three- stat e the out put driv -
ers. As a safety precaution, DQ[31:0] are automatically
three- stated whenever a write c ycle is de tected, regardless of
the stat e of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deserted HIGH, (3) CE1, CE2, CE3 are all asserted activ e, and
(4) t he approp riate c ombinati on of t he writ e input s (GW, BWE,
and BW[3:0]) are asserted active to conduct a write to the de-
sired byte(s). ADSC- triggered write ac cess es r equir e a singl e
clock cycle to complete. The address presented to A[16:0] is
loaded into the address register and the address advancement
logic whil e being delivered to the RAM core. The ADV inp u t is
ignored during this cycle. If a global write is conducted, the
data pr esented to t he DQ[31:0] is writ ten in to the c orrespondi ng
address l oca tion in the RAM core . If a b yte write is conduc ted ,
only the select ed bytes are wr itten. Bytes not selected during
a byte write operation will remain unaltered. A synchronous
self- timed write me chanism has been provided to simpli fy the
write operations .
Because the CY7C1339 is a common I/O device, the Output
Enable (OE) must be deser ted HIGH before presenti ng data
to the DQ[31:0] inputs . Doing so wi ll three- stat e the out put driv -
ers. As a safety precaution, DQ[31:0] are automatically
three- stated whenever a write c ycle is de tected, regardless of
the stat e of OE.
Burst Sequences
The CY7C1339 pr ov ides a tw o-bit wrapar ound count er , f ed b y
A[1:0], that imp lements ei ther an in terleaved or linear burst se-
quence. The interleaved burst sequence is designed specifi-
cally to support Intel Pentium applications. The linear burst
sequence is designed to suppor t processors that follow a lin-
ear burst sequence. The burst sequence is user selectable
through the MODE input .
Asser ting ADV LO W at clock rise wil l aut om atically inc rement
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Interleaved Burs t Sequence
First
Address Second
Address Third
Address Fourth
Address
A[1:0] A[1:0] A[1:0] A[1:0]
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
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CY7C1339
5
Sleep Mode
The ZZ input pin is an asyn chronous input. Assertin g ZZ plac-
es the SRAM in a pow er conservation “sleep” mode. T w o cloc k
cycles are req uired t o ent er i nto or exi t from t his “sleep” mo d e .
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device m ust be desel ected prior to entering the “sleep” mode.
CE1, CE2, CE3, ADSP, and ADSC must remain inactive for t he
duration of tZZREC after t he ZZ input returns LOW.
Linear Burst S equence
First
Address Second
Address Third
Address Fourth
Address
A[1:0] A[1:0] A[1:0] A[1:0]
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Chara cteristics
Parameter Description Test Conditions Min. Max. Unit
IDDZZ Sn ooze mode
standby current ZZ > VDD − 0.2V 3 mA
tZZS Device operation to
ZZ ZZ > VDD − 0.2V 2tCYC ns
tZZREC ZZ re c overy time ZZ < 0.2 V 2t CYC ns
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CY7C1339
6
Cycle Des cr i p ti ons[1 , 2, 3]
Next Cycle Add. U sed ZZ CE3CE2CE1ADSP ADSC ADV OE DQ Write
Unselected None L X X 1 X 0 X X Hi-Z X
Unselected None L 1 X 0 0 X X X Hi-Z X
Unselected None L X 0 0 0 X X X Hi-Z X
Unselected None L 1 X 0 1 0 X X Hi-Z X
Unselected None L X 0 0 1 0 X X Hi-Z X
Begin Read External L 0 1 0 0 X X X Hi-Z X
Begin Read External L 0 1 0 1 0 X X Hi-Z Read
Continue Read Next L X X X 1 1 0 1 Hi-Z Read
Continue Read Next L X X X 1 1 0 0 DQ Read
Continue Read Next L X X 1 X 1 0 1 Hi-Z Read
Continue Read Next L X X 1 X 1 0 0 DQ Read
Suspend Read Current L X X X 1 1 1 1 Hi-Z Rea d
Suspend Read Current L X X X 1 1 1 0 DQ Read
Suspend Read Current L X X 1 X 1 1 1 Hi-Z Read
Suspend Read Current L X X 1 X 1 1 0 DQ Read
Begin Write Current L X X X 1 1 1 X Hi-Z Write
Begin Write Current L X X 1 X 1 1 X Hi-Z Write
Begin Write External L 0 1 0 1 0 X X Hi-Z Write
Conti n ue W rite Next L X X X 1 1 0 X Hi-Z Wr i te
Conti n ue W rite Next L X X 1 X 1 0 X Hi- Z W ri te
Suspend W rite Current L X X X 1 1 1 X Hi-Z Write
Suspend W rite Current L X X 1 X 1 1 X Hi-Z Write
ZZ “Sleep” None H X X X X X X X Hi-Z X
Note:
1. X=”Don't Care,” 1=HIGH, 0=LOW.
2. Write is defined by BWE, BW[3:0], and GW. See Write Cycle Descriptions table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
This Material Copyrighted By Its Respective Manufacturer
CY7C1339
7
Maximum Ratings
(Above which the useful l ife may be impaired. For user guide-
li nes, not tes ted.)
Storage Temperature .....................................−65°C to +1 5 0 °C
Ambient Temperature with
Power Applied..................................................−55°C to +1 2 5 °C
Supply Volt age on VDD Relative to GND.........−0.5V to +4.6V
DC Voltage Applied to Output s
in High Z State[7] ....................................... −0.5V to VDD + 0.5V
DC Input Voltage[7].................................... −0.5V to VDD + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage ... .. ...... .. .. ...................... ..... >2001 V
(per MIL- STD-883, Method 3015 )
Latch-Up Curr ent...... .................................. ............ >200 mA
Note:
4. X=”Don't Care,” 1=Logic HIGH, 0=Logic LOW.
5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, B WE, or BW[3:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ=High-Z when OE is inactive or
when the device is deselected, and DQ=data when OE is active.
7. Minimum voltage equals −2.0V for pulse durations of less than 20 ns.
8. TA is the case temperature.
Wr i te C ycl e D escr i p ti o n s[4 , 5, 6]
Function GW BWE BW3BW2BW1BW0
Read 11XXXX
Read 101111
Write Byte 0 - DQ[7:0] 101110
Write Byte 1 - DQ[15:8] 101101
Write Bytes 1, 0 101100
Write Byte 2 - DQ[23:16] 101011
Write Bytes 2, 0 101010
Write Bytes 2, 1 101001
Write Bytes 2, 1, 0 101000
Write Byte 3 - DQ[31:24] 100111
Write Bytes 3, 0 100110
Write Bytes 3, 1 100101
Write Bytes 3, 1, 0 100100
Write Bytes 3, 2 100011
Write Bytes 3, 2, 0 100010
Write Bytes 3, 2, 1 100001
Write All Bytes 100000
Write All Bytes 0 XXXXX
Operating Range
Range Ambient
Temperature[8] VDD VDDQ
Com’l 0°C to +70°C 3.3V
−5%/+10% 2.5V −5%
3.3V /+10%
Ind’l–40°C to +85°C 3.3V
−5%/+10% 2.5V −5%
3.3V /+10%
This Material Copyrighted By Its Respective Manufacturer
CY7C1339
8
Electrical Characteristics Over the Ope rating Range
Parameter Description Test Conditions Min. Max. Unit
VDD Power Supply Voltage 3.3V −5%/+10% 3.135 3.6 V
VDDQ I/O Suppl y Voltage 2.5V −5% to 3.3V +10% 2.375 3.6 V
VOH Output HIGH Voltage VDDQ = 3.3V, VDD = Min. , IOH = –4.0 mA 2.4 V
VDDQ = 2.5V, VDD = Min. , IOH = –2.0 mA 2.0 V
VOL Output LOW Voltage VDDQ = 3.3V, VDD = Min. , IOL = 8.0 mA 0.4 V
VDDQ = 2.5V, VDD = Min. , IOL = 2.0 mA 0.7 V
VIH Input HIGH Voltage VDDQ = 3.3V 2.0 VDD + 0.3V V
VIH Input HIGH Voltage VDDQ = 2.5V 1.7 VDD + 0.3V V
VIL Input LOW Vol tage[7] VDDQ = 3.3V –0.3 0.8 V
VIL Input LOW Vol tage[7] VDDQ = 2.5V –0.3 0.7 V
IXInput Load Current
except ZZ and MODE GND ≤ VI ≤ VDDQ −55µA
Input Current of MODE Input = VSS −30 µA
Input = VDDQ 5µA
Input Current of ZZ I nput = VSS −5µA
Input = VDDQ 30 µA
IOZ Out put Leakage
Current GND ≤ VI ≤ VDDQ, Output Di sabled −55µA
IDD VDD Operating Supply
Current VDD = Max., IOUT = 0 mA ,
f = fMAX = 1/tCYC 6-ns cycle, 166 MHz 420 mA
7.5-ns cycl e, 133 MHz 375 mA
10-ns cycle, 100 MHz 325 mA
ISB1 Autom a ti c C S
Power-Down
Current—TTL Inputs
Max. VDD, D evi ce D es el e c t e d ,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
6-ns cycle, 166 MHz 150 mA
7.5-ns cycl e, 133 MHz 125 mA
10-ns cycle, 100 MHz 115 mA
ISB2 Autom a ti c C S
Power-Down
Current—CMOS Inputs
Max. VDD, Device Deselected, VIN
≤ 0.3V or VIN > VDDQ – 0.3V, f = 0 All speeds 10 mA
ISB3 Autom a ti c C S
Power-Down
Current—CMOS Inputs
Max. VDD, Devi ce Desel ected, or
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
f = fMAX = 1/tCYC
6-ns cycle, 166 MHz 125 mA
7.5-ns cycl e, 133 MHz 95 mA
10-ns cycle, 100 MHz 85 mA
ISB4 Autom a ti c C S
Power-Down
Current—TTL Inputs
Max. VDD, D evi ce D es el e c t e d ,
VIN ≥ VIH or VIN ≤ VIL, f = 0 18 mA
Capacitance[9]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 3.3V.
VDDQ = 3.3V
4pF
CCLK Clock Input Capacitance 4pF
CI/O Input/Out put Capacitance 4pF
Note:
9. Tested initially and after any design or process changes that may affect these parameters.
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CY7C1339
9
AC Test Loads and Waveforms
OUTPUT
R=317Ω
R=351Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL=50Ω
Z0=50Ω
VL= 1. 5V
3.3V ALL INPUT PULSES[10]
2.5V
GND
90%
10% 90%
10%
≤2.5ns ≤2.5ns
(c)
Switching Characteristics Over the Operating Range[11,12,13]
-166 -133 -100
Parameter Description Min. Max. Min. Max. Min. Max. Unit
tCYC Clock Cycle Time 6.0 7.5 10 ns
tCH Clock HIGH 1.7 1.9 3.5 ns
tCL Clock LO W 1.7 1.9 3.5 ns
tAS Address Set-U p Before CLK Rise 2.0 2.5 2.5 ns
tAH Address Hold Af ter CLK Rise 0.5 0.5 0.5 ns
tCO Data Output Valid After CLK Rise 3.5 4.0 5.5 ns
tDOH Data Output Hold After CLK Rise 1.5 2.0 2.0 ns
tADS ADSP, ADSC Set-Up Bef ore CLK Rise 2.0 2.5 2.5 ns
tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 ns
tWES BWE, GW, B W[3:0] Set-Up Before CLK Rise 2.0 2.5 2.5 ns
tWEH BWE, GW, B W[3:0] Hold After CLK Rise 0.5 0.5 0.5 ns
tADVS ADV Set-Up Before CLK Rise 2.0 2.5 2.5 ns
tADVH ADV Hold After CLK Rise 0.5 0.5 0.5 ns
tDS Data Input Set-Up Bef ore CLK Rise 2.0 2.5 2.5 ns
tDH Data Input Hold Aft er CLK Rise 0.5 0.5 0.5 ns
tCES Chip Select Set -Up 2.0 2.5 2.5 ns
tCEH Chip Select Hold After CLK Rise 0.5 0.5 0.5 ns
tCHZ Clock to High-Z[12] 3.5 3.5 3.5 ns
tCLZ Clock to Low-Z[12] 0 0 0 ns
tEOHZ OE HIGH to Output High-Z[12, 13] 3.5 3.5 5.5 ns
tEOLZ OE LOW to Output Low-Z[12, 13] 0 0 0 ns
tEOV OE LOW to Output Valid[12] 3.5 4.0 5.5 ns
Notes:
10. Input waveform should have a slew rate of 1 V/ns.
11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse level s of 0 to 3.0V, and output
loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC test loads.
12. tCHZ, tCLZ, tEOV, tEOLZ, and t EOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mf from steady-state
voltage.
13. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ.
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CY7C1339
10
Swi tch i n g Wa vefo rms
Write Cycl e Tim i n g [14, 15]
Notes:
14. WE is the combination of BWE, BW[3:0], and GW to define a write cycle (see Write Cycle Descriptions table).
15. WDx stands for Write Data to Address X.
ADSP
CLK
ADSC
ADV
ADD
CE
1
OE
GW
WE
CE
2
CE
3
1a
Data In
tCYC
tCH
tCL
tADS
tADH
tADS tADH
tADVS tADVH
WD1 WD2 WD3
tAH
tAS
tWS tWH tWH
tWS
tCES tCEH
tCES tCEH
tCES tCEH
2b 3a
1a
Single Write Burst Write Unselected
ADSP ignored with CE1 inactive
CE1 masks ADSP
= DON’T CARE
= UNDEFINED
Pipe li ned Write
2a 2c 2d
tDH
tDS
High-Z
High-Z
Unselected with CE2
ADV Must Be Inactive for ADSP Write
ADSC initiated write
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CY7C1339
11
Read Cycle Timing[14, 16]
Note:
16. RDx stands for Read Data from Address X.
Swi tch i n g Wa vefo rms (continued)
ADSP
CLK
ADSC
ADV
ADD
CE1
OE
GW
WE
CE2
CE3
2a 2c
1a
Data Out
tCYC tCH
tCL
tADS tADH
tADS
tADH
tADVS
tADVH
RD1 RD2 RD3
tAH
tAS
tWS tWH
tWH
tWS
tCES tCEH
tCES tCEH
tCES tCEH
tCO
tDOE
2b 2c 2d 3a
1a
tOEHZ tDOH
tCLZ tCHZ
Singl e Read Burst Read Unselected
ADSP ignored with CE1 i nactive
Suspend Burst
CE1 masks ADSP
= DON’T CARE = UNDEFINED
Pipel ined Read
ADSC initiated read
Unselected wit h CE2
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CY7C1339
12
Read/Writ e Cycle Ti ming[14, 15, 16, 17]
Note:
17. Data bus is driven by SRAM, but data is not guaranteed.
Swi tch i n g Wa vefo rms (continued)
ADSP
CLK
ADSC
ADV
ADD
CE1
OE
GW
WE
CE2
CE3
1a
Da ta In/Ou t
tCYC tCH
tCL
tADS tADH
tADS
tADH
tADVS
tADVH
RD1 WD2 RD3
tAH
tAS
tWS tWH
tWH
tWS
tCES tCEH
tCES tCEH
tCES tCEH
tOELZ
tCO
tDOE
3a 3c 3d
1a
tOEHZ tDOH
tCHZ
Singl e Read Burst Read Unselected
ADSP ignored with CE1 inactive
CE1 masks ADSP
= DON’T CARE = UNDEFINED
Pipeli ned Read
Out 2a
In 3b
Out
Out Out Out
Single Write
tDS tDH
2a
Out
Se e No te 17
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CY7C1339
13
Notes:
18. Device originally deselected.
19. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device.
Swi tch i n g Wa vefo rms (continued)
Pipeline Timing[18, 19]
tAS
= DON’T CARE = UNDEFINED
tCLZ
tCHZ
tDOH
CLK
ADD
WE
CE1
Data In /O u t
ADSC
ADSP
ADV
CE
OE
D(C)
tCYC
tCH tCL
tADS tADH
tCEH
tCES
tWEH
tWES
tCO
ADSP ignored
with CE1 HIGH
RD1 RD2 RD3 RD4 WD1 WD2 WD3 WD4
1a
Out 2a
Out 3a
Out 4a
Out 1a
In 2a
In 3a
In 4a
In
Back to Back Reads
ADSP initiate d Reads
ADSC initiated Reads
In
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CY7C1339
14
Swi tch i n g Wa vefo rms (continued)
ADSP
CLK
ADSC
CE1
CE3
LOW
HIGH
ZZ tZZS
tZZREC
IDD IDD(active)
Three-state
I/O’s
NotefjdfdhfdjfdfjdjdjdjNo
Note:
20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
21. I/Os are in three-state when exiting ZZ sleep mode.
ZZ Mode Timing [20 , 21 ]
CE2
IDDZZ
HIGH
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CY7C1339
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibi lity for the use
of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it con vey or imply any lice nse under patent or other rights. C ypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in signific ant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Document #: 38-00723-C
Ordering Information
Speed
(MHz) Orderi ng Code Package
Name Package Typ e Operating
Range
166 CY7C1339-166AC A101 100-Lead Thin Quad Flat Pack Commercial
133 CY7C1339-133AC
100 CY7C1339-100AC
133 CY7C1339-133AI Industrial
Package Diagram
100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) A101
51-85050-A
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This Material Copyrighted By Its Respective Manufacturer
This Material Copyrighted By Its Respective Manufacturer