_______________General Description
The MAX113/MAX117 are microprocessor-compatible,
8-bit, 4-channel and 8-channel analog-to-digital con-
verters (ADCs). They operate from a single +3V supply
and use a half-flash technique to achieve a 1.8µs con-
version time (400ksps). A power-down pin (PWRDN)
reduces current consumption to 1µA typical. The
devices return from power-down mode to normal oper-
ating mode in less than 900ns, allowing large supply-
current reductions in burst-mode applications. (In burst
mode, the ADC wakes up from a low-power state at
specified intervals to sample the analog input signals.)
Both converters include a track/hold, enabling the ADC
to digitize fast analog signals.
Microprocessor (µP) interfaces are simplified because
the ADC can appear as a memory location or I/O port
without external interface logic. The data outputs use
latched, three-state buffer circuitry for direct connection
to an 8-bit parallel µP data bus or system input port.
The MAX113/MAX117 input/reference configuration
enables ratiometric operation.
The 4-channel MAX113 is available in a 24-pin DIP or
SSOP. The 8-channel MAX117 is available in a 28-pin
DIP or SSOP. For +5V applications, refer to the
MAX114/MAX118 data sheet.
________________________Applications
Battery-Powered Systems Portable Equipment
System-Health Monitoring Remote Data Acquisition
Communications Systems
____________________________Features
♦+3.0V to +3.6V Single-Supply Operation
♦4 (MAX113) or 8 (MAX117) Analog Input Channels
♦Low Power: 1.5mA (operating mode)
1µA (power-down mode)
♦Total Unadjusted Error ≤1LSB
♦Fast Conversion Time: 1.8µs per Channel
♦No External Clock Required
♦Internal Track/Hold
♦Ratiometric Reference Inputs
♦Internally Connected 8th Channel Monitors
Reference Voltage (MAX117)
MAX113/MAX117
+3V, 400ksps, 4/8-Channel,
8-Bit ADCs with 1µA Power-Down
________________________________________________________________
Maxim Integrated Products
1
4-BIT
DAC
4-BIT
FLASH
ADC
(4MSBs)
4-BIT
FLASH
ADC
(4LSBs)
TIMING AND
CONTROL
ADDRESS
LATCH
DECODE
REF+
16
THREE-
STATE
OUTPUT
DRIVERS
D7
D6
D5
D4
D3
D2
D1
D0
MUX
*IN7 *IN8
Σ
REF+
*IN6
*IN5
IN4
IN3
IN2
IN1
A0 A1 A2 REF- PWRDN RD
MODE INT WR/RDY
CS
MAX113/MAX117
*MAX117 ONLY
_________________________________________________________Functional Diagram
19-1081; Rev 1; 8/96
PART
MAX113CNG
MAX113CAG
MAX113C/D 0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGE PIN-PACKAGE
24 Narrow Plastic DIP
24 SSOP
Dice*
______________Ordering Information
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
MAX113ENG
MAX113EAG
MAX113MRG -55°C to +125°C
-40°C to +85°C
-40°C to +85°C 24 Narrow Plastic DIP
24 SSOP
24 Narrow CERDIP**
Ordering Information continued at end of data sheet.
*Dice are specified at TA= +25°C, DC parameters only.
**Contact factory for availability.
Pin Configuration appears at end of data sheet.
MAX113/MAX117
+3V, 400ksps, 4/8-Channel,
8-Bit ADCs with 1µA Power-Down
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +3V to +3.6V, REF+ = 3V, REF- = GND, Read Mode (MODE = GND), TA= TMIN to TMAX, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND..............................................................-0.3V to +7V
Digital Input Voltage to GND......................-0.3V to (VDD + 0.3V)
Digital Output Voltage to GND...................-0.3V to (VDD + 0.3V)
REF+ to GND..............................................-0.3V to (VDD + 0.3V)
REF- to GND...............................................-0.3V to (VDD + 0.3V)
IN_ to GND.................................................-0.3V to (VDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
24 Narrow Plastic DIP
(derate 13.33mW/°C above +70°C)................................1.08W
24 SSOP (derate 8.00mW/°C above +70°C).................640mW
24 Narrow CERDIP (derate 12.50mW/°C above +70°C) .....1W
28 Wide Plastic DIP
(derate 14.29mW/°C above +70°C)................................1.14W
28 SSOP (derate 9.52mW/°C above +70°C).................762mW
28 Wide CERDIP (derate 16.67mW/°C above +70°C)....1.33W
Operating Temperature Ranges
MAX113C_G/MAX117C_I ....................................0°C to +70°C
MAX113E_G/MAX117E_I..................................-40°C to +85°C
MAX113MRG/MAX117MJI..............................-55°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
VIN_ = 3Vp-p
MAX11_M, fSAMPLE = 340kHz, fIN = 30.725kHz
GND < VIN_ < VDD
MAX11_C/E, fSAMPLE = 400kHz, f IN = 30.273kHz
No-missing-codes guaranteed
CONDITIONS
VVREF- VDD
REF+ Input Voltage Range kΩ124R
REF
Reference Resistance
pF32CIN_Input Capacitance µA±3IIN_Input Leakage Current VVREF- VREF+
VIN_Input Voltage Range
V/µs0.28 0.5Input Slew Rate, Tracking
LSB±1TUETotal Unadjusted Error Bits8NResolution
MHz0.3Input Full-Power Bandwidth
dB
45
SINAD
Signal-to-Noise Plus
Distortion Ratio 45
LSB±1DNLDifferential Nonlinearity LSB±1Zero-Code Error LSB±1Full-Scale Error LSB±1/4Channel-to-Channel Mismatch
UNITSMIN TYP MAXSYMBOLPARAMETER
MAX11_M, fSAMPLE = 340kHz, fIN = 30.725kHz
MAX11_C/E, fSAMPLE = 400kHz, f IN = 30.273kHz dB
-50
THDTotal Harmonic Distortion -50
MAX11_M, fSAMPLE = 340kHz, fIN = 30.725kHz
MAX11_C/E, fSAMPLE = 400kHz, f IN = 30.273kHz dB
50
SFDR
Spurious-Free Dynamic
Range 50
VGND VREF+
REF- Input Voltage Range
ACCURACY (Note 1)
DYNAMIC PERFORMANCE
ANALOG INPUT
REFERENCE INPUT
MAX113/MAX117
+3V, 400ksps, 4/8-Channel,
8-Bit ADCs with 1µA Power-Down
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +3V to +3.6V, REF+ = 3V, REF- = GND, Read Mode (MODE = GND), TA= TMIN to TMAX, unless otherwise noted.)
Note 1: Accuracy measurements performed at VDD = +3.0V. Operation over supply range is guaranteed by power-supply rejection test.
Note 2: Guaranteed by design.
Note 3: Power-down current increases if logic inputs are not driven to GND or VDD.
WR
CS, RD, PWRDN, A0, A1, A2 µA
±3
IINH
D0–D7, RDY
D0–D7, RDY, digital outputs = 0V to VDD
ISOURCE = 20µA, INT, D0–D7
ISINK = 400µA, INT, D0–D7
MODE
MODE
ISINK = 20µA, INT, D0–D7
CS, WR, RD, PWRDN, A0, A1, A2
CS, WR, RD, PWRDN, MODE, A0, A1, A2
CS, WR, RD, PWRDN, MODE, A0, A1, A2
CONDITIONS
Input High Current ±1
pFCOUT
µAILKG
Three-State Capacitance
(Note 2)
VDD - 0.1
V0.4VOL
Output Low Voltage 0.1
pF58C
IN
Input Capacitance (Note 2) µA±1IINL
Input Low Current 15 100
V
2.4
VINH
Input High Voltage
MODE
2
CS, WR, RD, PWRDN, A0, A1, A2 V
UNITSMIN TYP MAXSYMBOLPARAMETER
0.8
VINL
Input Low Voltage 0.66
2.5 5 V3.0 3.6VDD
Supply Voltage
VDD = 3.0V to 3.6V, VREF = 3.0V
CS = RD = VDD, PWRDN = 0V (Note 3) LSB±1/16 ±1/4PSRPower-Supply Rejection µA110Power-Down VDD Current
VDD = 3.6V, CS = RD = 0V,
PWRDN = VDD 2.5 6
MAX11_C
RDY, ISINK = 1mA 0.4
ISOURCE = 400µA, INT, D0–D7 V
VDD - 0.4
VOH
Output High Voltage
1.5 3
VDD = 3.0V, CS = RD = 0V,
PWRDN = VDD
mA
1.5 3.5
IDD
VDD Supply Current MAX11_E/M
MAX11_C
MAX11_E/M
58
LOGIC INPUTS
LOGIC OUTPUTS
POWER REQUIREMENTS
±3Three-State Current
MAX113/MAX117
+3V, 400ksps, 4/8-Channel,
8-Bit ADCs with 1µA Power-Down
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS
(VDD = +3V, TA= +25°C, unless otherwise noted.) (Note 4)
Note 4: Input control signals are specified with tr = tf= 5ns, 10% to 90% of 3V, and timed from a voltage level of 1.3V. Timing
delays get shorter at higher supply voltages. See the Conversion Time vs. Supply Voltage graph in the
Typical Operating
Characteristics
to extrapolate timing delays at other power-supply voltages.
Note 5: See Figure 1 for load circuit. Parameter defined as the time required for the output to cross 0.66V or 2.0V.
Note 6: See Figure 2 for load circuit. Parameter defined as the time required for the data lines to change 0.5V.
Note 7: Also defined as the Minimum Address-Valid to Convert-Start Time.
0.8 100.66 10
WR Pulse Width tWR 0.6 10 µs
700
Minimum
Acquisition Time tACQ 450 ns(Note 7) 600
MAX117M
MIN MAXMIN TYP MAX
PARAMETER SYMBOL MIN MAX UNITSCONDITIONS MAX117C/E
TA= +25°C
ALL GRADES TA= TMIN to TMAX
250
Data Access Time
(WR-RD Mode) tACC2 180 ns
tRD > tINTL, CL= 100pF
(Note 5) 220
1.0
600
150
600
400
1.8
70
250
240
Data Access Time
After INT tID
Delay Between WR
and RD Pulses tRD 0.8 µs
RD Pulse Width
(WR-RD Mode) tREAD1 400 ns
100 ns
Multiplexer Address
Hold Time
Data Access Time
(WR-RD Mode) tACC1 400 ns
RD to INT Delay tRI 300 ns
WR to INT Delay tINTL 0.7 1.45 µs
tAH 50 ns
Pipelined mode, CL= 100pF
RD Pulse Width
(WR-RD Mode) tREAD2 180 ns
WR to INT Delay tIHWR 180 ns
0.9
500
130
tRD > tINTL, determined by
tACC2
tRD < tINTL, determined by
tACC1
500
tRD < tINTL, CL= 100pF
(Note 5) 340
CL= 50pF
Pipelined mode, CL= 50pF
1.6
60
220
200
150
0
0
140
tCRD +
150
180
130
0
0
120
tCRD +
130
170
Data Hold Time tDH 100 ns
CS to RD, WR
Setup Time tCSS 0 ns
CS to RD, WR
Hold Time tCSH 0 ns
CS to RDY Delay tRDY 100 ns
(Note 6)
Data Access Time
(RD Mode) tACC0 tCRD +
100 ns
RD to INT Delay
(RD Mode) tINTH 100 160 ns
CL= 100pF (Note 5)
CL= 50pF,
RL= 5.1kΩto VDD
CL= 50pF
2.42.06
Conversion Time
(WR-RD Mode) tCWR 1.8 µs
tRD < tINTL, CL= 100pF
(Note 5)
1.41.2
Power-Up Time tUP 0.9 µs
2.62.4
Conversion Time
(RD Mode) tCRD 2.0 µs
MAX113/MAX117
+3V, 400ksps, 4/8-Channel,
8-Bit ADCs with 1µA Power-Down
_______________________________________________________________________________________
5
1.6
0.4 -60 140
CONVERSION TIME
vs. AMBIENT TEMPERATURE
0.6
1.4
TEMPERATURE (°C)
tCRD (NORMALIZED TO VALUE
AT VDD = +3.3V, +25°C)
60
1.0
0.8
-20 20 100
1.2
VDD = 3.3V
VDD = 3.6V
VDD = 3.0V
MAX113/117-01
8.0
4.0 1k 10k 100k
EFFECTIVE BITS vs.
INPUT FREQUENCY (WR-RD MODE)
INPUT FREQUENCY (Hz)
EFFECTIVE BITS
1M
7.5
7.0
6.5
6.0
5.5
5.0
4.5 fSAMPLE = 400kHz
VIN = 2.98Vp-p
MAX113/117-02
-100 0 200
SIGNAL-TO-NOISE RATIO
FREQUENCY (kHz)
SNR (dB)
120
-80
40 80 160
-40
0
-20
-60
MAX113/117-03
fIN = 30.27kHz
VIN = 2.88Vp-p
fSAMPLE = 400ksps
SNR = 48.8dB
1400
800 2.8 4.0
CONVERSION TIME
vs. SUPPLY VOLTAGE
900
1300
SUPPLY VOLTAGE (V)
tCRD (ns)
3.6
1100
1000
3.0 3.4 3.8
1200
3.2
MAX113/117-04
4
5
01
AVERAGE POWER CONSUMPTION
vs. SAMPLING RATE USING PWRDN
1
3
SAMPLING RATE (ksps)
POWER DISSIPATION (mW)
1000
2
10 100
MAX113/117-06
5
0120 160 240 320
TOTAL UNADJUSTED ERROR
vs. POWER-UP TIME
1
4
MAX113/117-08
tUP (ns)
TUE (LSB)
200 280
3
2
VDD = 3.0V
VDD = 3.6V
__________________________________________Typical Operating Characteristics
(VDD = +3V, TA = +25°C, unless otherwise noted.)
VDD = 5.25V
4
0-60 140
SUPPLY CURRENT vs. TEMPERATURE
(EXCLUDING REFERENCE CURRENT)
1
2
3
MAX113/117-10
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
60 100-20 20
VDD = 3.3V
VDD = 3.0V
MAX113/MAX117
+3V, 400ksps, 4/8-Channel,
8-Bit ADCs with 1µA Power-Down
6 _______________________________________________________________________________________
______________________________________________________________Pin Description
Mode Selection Input. Internally pulled low with a 15µA current source. MODE = 0
activates read mode; MODE = 1 activates write-read mode (see
Digital Interface
section).
MODE5
Analog Input Channel 6IN6—
FUNCTION
Three-State Data Outputs D1, D2, D37, 8, 9 Three-State Data Output (LSB)D06
Lower limit of reference span. REF- sets the zero-code voltage. Range is GND ≤
VREF- < VREF+.
REF-13
GroundGND12
Interrupt Output. INT goes low to indicate end of conversion (see
Digital Interface
section).
INT
11
Read Input. RD must be low to access data (see
Digital Interface
section).RD
10
Write-Control Input/Ready-Status Output (see
Digital Interface
section)
WR/RDY
15
Upper limit of reference span. REF+ sets the full-scale input voltage. Range is
VREF- < VREF+ ≤VDD. Internally hardwired to IN8 (Table 1).
REF+14
Multiplexer Channel Address Input (MSB)A2— Three-State Data Output (MSB)D720
Positive Supply, +3.0V to +3.6VVDD
24 Power-Down Input. PWRDN reduces supply current when low.PWRDN
23 Multiplexer Channel Address Input (LSB)A022 Multiplexer Channel Address Input A121
Analog Input Channel 7IN7—
Three-State Data Outputs D4, D5, D617, 18, 19 Chip-Select Input. CS must be low for the device to recognize WR or RD inputs.CS
16
9, 10, 11
8
15
14
13
12
17
16
23
22
27
PIN
7
1
26
25
24
28
19, 20, 21
18
MAX113 NAME
MAX117
Analog Input Channel 5IN5— 2
Analog Input Channel 1
Analog Input Channel 2IN23 IN1
5
4 6
Analog Input Channel 3
Analog Input Channel 4IN41 IN3
3
2 4
MAX113/MAX117
+3V, 400ksps, 4/8-Channel,
8-Bit ADCs with 1µA Power-Down
_______________________________________________________________________________________ 7
_______________Detailed Description
Converter Operation
The MAX113/MAX117 use a half-flash conversion tech-
nique (see
Functional Diagram
) in which two 4-bit flash
ADC sections achieve an 8-bit result. Using 15 com-
parators, the flash ADC compares the unknown input
voltage to the reference ladder and provides the upper
four data bits. An internal digital-to-analog converter
(DAC) uses the four most significant bits (MSBs) to
generate both the analog result from the first flash con-
version and a residue voltage that is the difference
between the unknown input and the DAC voltage. The
residue is then compared again with the flash com-
parators to obtain the lower four data bits (LSBs).
An internal analog multiplexer enables the devices to
read four (MAX113) or eight (MAX117) different analog
voltages under microprocessor (µP) control. One of the
MAX117’s analog channels, IN8, is internally hard-
wired and always reads VREF+ when selected.
Power-Down Mode
In burst-mode or low-sample-rate applications, the
MAX113/MAX117 can be shut down between conver-
sions, reducing supply current to microamp levels (see
Typical Operating Characteristics
). A logic low on the
PWRDN pin shuts the devices down, reducing supply
current typically to 1µA when powered from a single
+3V supply. A logic high on PWRDN wakes up the
MAX113/MAX117, and the selected analog input enters
the track mode. The signal is fully acquired after 900ns
(this includes both the power-up delay and the
track/hold acquisition time), and a new conversion can
be started. If the power-down feature is not required,
connect PWRDN to VDD. For minimum current con-
sumption, keep digital inputs at the supply rails in
power-down mode. Refer to the
Reference
section for
information on reducing the reference current during
power-down.
___________________Digital Interface
The MAX113/MAX117 have two basic interface modes,
which are set by the MODE pin. When MODE is low,
the converters are in read mode; when MODE is high,
the converters are set up for write-read mode. The A0,
A1, and A2 inputs control channel selection, as shown
in Table 1. The address must be valid for a minimum
time, tACQ, before the next conversion starts.
DATA
OUTPUTS
DATA
OUTPUTS
CL
RL = 3k CL
a) HIGH-Z TO VOH b) HIGH-Z TO VOL
RL = 3k
VDD
Figure 1. Load Circuits for Data-Access Time Test
DATA
OUTPUTS
10pF
3k 10pF
a) VOH TO HIGH-Z b) VOL TO HIGH-Z
3k
VDD
DATA
OUTPUTS
Figure 2. Load Circuits for Data-Hold Time Test
Table 1. Truth Table for Input Channel
Selection
MAX113
00 IN1
IN201
IN4
IN3
11
10
IN6
IN5
——
IN8
(reads VREF+ if selected)
IN7
——
——
——
001
011
010
101
111
110
100
MAX117
000
SELECTED CHANNEL
A2 A1 A0A1 A0
MAX113/MAX117
Read Mode (MODE = 0)
In read mode, conversions and data access are con-
trolled by the RD input (Figure 3). The comparator
inputs track the analog input voltage for the duration of
tACQ. A conversion is initiated by driving CS and RD
low. With µPs that can be forced into a wait state, hold
RD low until output data appears. The µP starts the
conversion, waits, and then reads data with a single
read instruction.
In read mode, WR/RDY is configured as a status output
(RDY), so it can drive the ready or wait input of a µP.
RDY is an open-collector output (no internal pull-up)
that goes low after the falling edge of CS and goes high
at the end of the conversion. If not used, the WR/RDY
pin can be left unconnected. The INT output goes low
at the end of the conversion and returns high on the ris-
ing edge of CS or RD.
Write-Read Mode (MODE = 1)
Figures 4 and 5 show the operating sequence for write-
read mode. The comparator inputs track the analog
input voltage for the duration of tACQ. The conversion is
initiated by a falling edge of WR. When WR returns
high, the result of the four-MSBs flash is latched into the
output buffers and the conversion of the four-LSBs flash
starts. INT goes low, indicating conversion end, and the
lower four data bits are latched into the output buffers.
The data is then accessible after RD goes low (see
Timing Characteristics
).
A minimum acquisition time (tACQ) is required from INT
going low to the start of another conversion (WR going
low).
Options for reading data from the converter include
using internal delay, reading before delay, and pipelined
operation (discussed in the following sections).
Using Internal Delay
The µP waits for the INT output to go low before reading
the data (Figure 4). INT goes low after the rising edge of
WR, indicating that the conversion is complete and the
result is available in the output latch. With CS low, data
outputs D0–D7 can be accessed by pulling RD low. INT
is then reset by the rising edge of CS or RD.
Fastest Conversion:
Reading Before Delay
An external method of controlling the conversion time is
shown in Figure 5. The internally generated delay
(tINTL) varies slightly with temperature and supply volt-
age, and can be overridden with RD to achieve the
fastest conversion time. RD is brought low after the ris-
ing edge of WR, but before INT goes low. This com-
pletes the conversion and enables the output buffers
+3V, 400ksps, 4/8-Channel,
8-Bit ADCs with 1µA Power-Down
8 _______________________________________________________________________________________
tCSS
tRDY
tACQ tAH WITH EXTERNAL
PULL-UP
tCSH
tACQ
tINTH
tUP
tDH
tCRD
tACCO
D0–D7
RDY
RD
CS
PWRDN
INT
A0–A2
VALID DATA
(N)
ADDRESS VALID (N + 1)
ADDRESS VALID
(N)
tAH
tAH tACQ
tDH
tREAD2
tRD
D0–D7
RD
WR
CS
INT
VALID DATA
(N)
tINTL
tACC2
tWR
tCSS tCSH
tACQ
tCSS tCSH
A0–A2
tINTH
ADDRESS
VALID (N) ADDRESS VALID (N + 1)
Figure 3. Read Mode Timing (Mode = 0)
Figure 4. Write-Read Mode Timing (tRD > tINTL) (Mode = 1)
tCSS tACQ
tDH
tREAD1
tRD
tINTL
tACQ tAH
RD
WR
CS
INT
VALID DATA
(N)
tCSS tCSH
tINTH
tWR tCSH
tACC1
tCWR
tRI
A0–A2
D0–D7
ADDRESS
VALID (N) ADDRESS VALID (N + 1)
Figure 5. Write-Read Mode Timing (tRD < tINTL) (Mode = 1)
that contain the conversion result (D0–D7). INT also
goes low after the falling edge of RD and is reset on the
rising edge of RD or CS. The total conversion time is
therefore: tWR + tRD + tACC1 = 1800ns.
Pipelined Operation
Besides the two standard write-read-mode options,
“pipelined” operation can be achieved by connecting
WR and RD together (Figure 6). With CS low, driving
WR and RD low initiates a conversion and concurrently
reads the result of the previous conversion.
_____________Analog Considerations
Reference
Figures 7a, 7b, and 7c show typical reference connec-
tions. The voltages at REF+ and REF- set the ADC’s
analog input range (Figure 10). The voltage at REF-
defines the input that produces an output code of all
zeros, and the voltage at REF+ defines the input that
produces an output code of all ones.
The internal resistance from REF+ to REF- can be as
low as 1kΩ, and current will flow through it even when
the MAX113/MAX117 are shut down. Figure 7d shows
how an N-channel MOSFET can be connected to REF-
to break this current path during power-down. The FET
should have an on-resistance of less than 2Ωwith a 3V
gate drive. When REF- is switched, as in Figure 7d, a
new conversion can be initiated after waiting a time
equal to the power-up delay (tUP) plus the N-channel
FET’s turn-on time.
Although REF+ is frequently connected to VDD, the cir-
cuit of Figure 7d uses a low-current, low-dropout, 2.5V
voltage reference: the MAX872. Since the MAX872
cannot continuously furnish enough current for the ref-
erence resistance, this circuit is intended for applica-
tions where the MAX113/MAX117 are normally in stand-
by and are turned on in order to make measurements
at intervals greater than 100µs. C1 (the capacitor con-
nected to REF+) is slowly charged by the MAX872 dur-
ing the standby period, and furnishes the reference
current during the short measurement period.
The 4.7µF value of C1 ensures a voltage drop of less
than 1/2LSB when performing four to eight successive
conversions. Larger capacitors reduce the error still fur-
ther. Use ceramic or tantalum capacitors for C1.
MAX113/MAX117
+3V, 400ksps, 4/8-Channel,
8-Bit ADCs with 1µA Power-Down
_______________________________________________________________________________________ 9
tACQ
tINTL
RD, WR
INT
NEW DATA (N)
tWR
tACQ
tAH
tCSH
tIHWR
tCSS
tID
OLD DATA (N - 1)
D0–D7
ADDRESS
VALID (N) ADDRESS
VALID (N + 1)
A0–A2
CS
Figure 6. Pipelined Mode Timing (WR = RD) (Mode = 1)
REF-
MAX113
MAX117
VDD
IN_
REF+
VIN+
VIN- GND
+3V
0.1µF
4.7µF
Figure 7a. Power Supply as Reference
+3V
0.1µF
4REF-
MAX113
MAX117
REF+
IN_
8
1
3
7
0.1µF
4.7µF
2
6
GND
VDD
+2.5V
34.8k
3.01k
LM10
VIN+
VIN-
REF-
MAX113
MAX117
REF+
0.1µF 0.1µF
* CURRENT PATH MUST STILL
EXIST FROM VIN- TO GND
R*
IN_
VIN-
VDD
VIN+
GND
+3V
+2.5V
0.1µF
4.7µF
Figure 7b. External Reference, 2.5V Full Scale
Figure 7c. Input Not Referenced to GND
MAX113/MAX117
Initial Power-Up
When power is first applied, perform a conversion to
initialize the MAX113/MAX117. Disregard the output
data.
Bypassing
Use a 4.7µF electrolytic in parallel with a 0.1µF ceramic
capacitor to bypass VDD to GND. Minimize capacitor
lead lengths.
Bypass the reference inputs with 0.1µF capacitors, as
shown in Figures 7a, 7b, and 7c.
Analog Inputs
Figure 8 shows the equivalent circuit of the MAX113/
MAX117 input. When a conversion starts and WR is
low, VIN_ is connected to sixteen 0.6pF capacitors.
During this acquisition phase, the input capacitors
charge to the input voltage through the resistance of
the internal analog switches. In addition, about 22pF of
stray capacitance must be charged. The input can be
modeled as an equivalent RC network (Figure 9). As
source impedance increases, the capacitors take
longer to charge.
The typical 32pF input capacitance allows source resis-
tance as high as 1.5kΩwithout setup problems. For
larger resistances, the acquisition time (tACQ) must be
increased.
Internal protection diodes, which clamp the analog
input to VDD and GND, allow the channel input pins to
swing from GND - 0.3V to VDD + 0.3V without damage.
However, for accurate conversions near full scale and
zero scale the inputs must not exceed VDD by more
than 50mV or be lower than GND by 50mV.
+3V, 400ksps, 4/8-Channel,
8-Bit ADCs with 1µA Power-Down
10 ______________________________________________________________________________________
RON
RIN
VIN2
MAX113
MAX117
.
.
.T/H
MUX
2k
R
VIN_ 1
22pF
VIN
MAX113
MAX117
10pF
Figure 8. Equivalent Input Circuit
Figure 9. RC Network Equivalent Input Model
REF-
MAX113
MAX117
VDD
MAX872
REF+
+3V 0.1µF
C1
4.7µF
PWRDN
PWRDN
N-FET*
* IRML2402
0.1µF
Figure 7d. An N-channel MOSFET switches off the reference
load during power-down
OUTPUT CODE
INPUT VOLTAGE (LSBs)
FS
FS - 1LSB
FULL-SCALE
TRANSITION
123
11111111
11111110
11111101
00000011
00000010
00000001
00000000
1LSB =
VREF+ - VREF-
256
VREF-
VREF+
Figure 10. Transfer Function
If the analog input exceeds 50mV beyond the sup-
plies, limit the input current to no more than two
milliamperes, as excessive current will degrade the
conversion accuracy of the on channel.
Track/Hold
The track/hold enters hold mode when a conversion
starts (RD low or WR low). INT goes low at the end of
the conversion, at which point the track/hold enters
track mode. The next conversion can start after the
minimum acquisition time, tACQ.
Transfer Function
Figure 10 shows the MAX113/MAX117’s nominal trans-
fer function. Code transitions occur halfway between
successive-integer LSB values. Output coding is binary
with 1LSB = (VREF+ - VREF-) / 256.
Conversion Rate
The maximum sampling rate (fMAX) for the MAX113/
MAX117 is achieved in write-read mode (tRD < tINTL)
and is calculated as follows:
where tWR = the write pulse width, tRD = the delay
between write and read pulses, tRI = RD to INT delay,
and tACQ = minimum acquisition time.
Signal-to-Noise Ratio and
Effective Number of Bits
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to all
other ADC output signals. The output spectrum is limit-
ed to frequencies above DC and below one-half the
ADC sample rate.
The theoretical minimum analog-to-digital noise is
caused by quantization error, and results directly from
the ADC’s resolution: SNR = (6.02N + 1.76)dB, where
N is the number of bits of resolution. Therefore, a per-
fect 8-bit ADC can do no better than 50dB.
The FFT Plot (see
Typical Operating Characteristics
)
shows the result of sampling a pure 30.27kHz sinusoid
at a 400kHz rate. This FFT plot of the output shows the
output level in various spectral bands.
The effective resolution (or “effective number of bits”)
the ADC provides can be measured by transposing the
equation that converts resolution to SNR: N = (SINAD -
1.76) / 6.02 (see
Typical Operating Characteristics
).
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal (in the frequen-
cy band above DC and below one-half the sample rate)
to the fundamental itself. This is expressed as:
where V1is the fundamental RMS amplitude, and V2
through VNare the amplitudes of the 2nd through Nth
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
fundamental RMS amplitude to the amplitude of the
next largest spectral component (in the frequency band
above DC and below one-half the sample rate). Usually
the next largest spectral component occurs at some
harmonic of the input frequency. However, if the ADC is
exceptionally linear, it may occur only at a random
peak in the ADC’s noise floor. See the Signal-to-Noise
Ratio graph in
Typical Operating Characteristics
.
THD = 20log V V V ...V
V
223242N2
1
+++
f= 1
t + t + t + t
f 1
600ns 800ns 300ns 450ns
f 465kHz
MAX WR RD RI ACQ
MAX
MAX
=+++
=
MAX113/MAX117
+3V, 400ksps, 4/8-Channel,
8-Bit ADCs with 1µA Power-Down
______________________________________________________________________________________ 11
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MAX113/MAX117
+3V, 400ksps, 4/8-Channel,
8-Bit ADCs with 1µA Power-Down
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
___________________Chip Information
TRANSISTOR COUNT: 2011
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
VDD
PWRDN
A0
A1
IN1
IN2
IN3
IN4
TOP VIEW
D7
D6
D5
D4
D2
D1
D0
MODE
16
15
14
13
9
10
11
12
CS
WR/RDY
REF+
REF-
GND
INT
RD
D3
DIP/SSOP
MAX113
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
IN7
VDD
PWRDN
A0
A1
A2
REF-
D7
D6
D5
D4
CS
WR/RDY
REF+
GND
INT
RD
D3
D2
D1
D0
MODE
IN1
IN2
IN3
IN4
IN5
IN6
DIP/SSOP
MAX117
__Ordering Information (continued)
__________________________________________________________Pin Configurations
*Dice are specified at TA= +25°C, DC parameters only.
**Contact factory for availability.
28 Wide CERDIP**
28 SSOP
28 Wide Plastic DIP-40°C to +85°C
-40°C to +85°C
-55°C to +125°CMAX117MJI
MAX117EAI
MAX117EPI Dice*
28 SSOP
28 Wide Plastic DIP
PIN-PACKAGETEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°CMAX117C/D
MAX117CAI
MAX117CPI
PART
